From patchwork Sun Sep 15 11:43:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurentiu Mihalcea X-Patchwork-Id: 13804773 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26CF71C463D for ; Sun, 15 Sep 2024 11:44:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726400649; cv=none; b=MaG3COiTTCN/YgcgQtENEBa8uIKk8kVslaUweD56xecn9hJv4Wpe/r2aKQ69f0fG999MHhQEdSdo/l/ojwI1MwvwmMSsfzUXqYo9kNP30DCLoFfierS5NwKRrrnZueFh0uic/J3tzu2RGPUm0dFrv417+cjt5OkSSBk6li+Q/aI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726400649; c=relaxed/simple; bh=HgijeomsNGsoTD7HIIXQI6oJ83tlGGXVPPZwJNbDgRI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=L0xlSKqOt9MgAOLpRO6BO9J7CLexmZmzD+a71ET9Q8ZNKypdHfo7DJafSZKxwuQ7GVZdmZfPeZZIc5n3WPHtMKcewlP6a+CRMdwZJwsEcEiMg51Oylkx5IisANNtcMSrV2HEg1pk9fZ+TecDNMetARWj97DhnrDZbjRTsi+7rpg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=TkWoiE2O; arc=none smtp.client-ip=209.85.218.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TkWoiE2O" Received: by mail-ej1-f43.google.com with SMTP id a640c23a62f3a-a8a6d1766a7so453842766b.3 for ; Sun, 15 Sep 2024 04:44:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726400646; x=1727005446; darn=lists.linux.dev; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MMukAaRv6lsduEQXd5W1x8cQrcsYqXKgAlv5XHYkQXQ=; b=TkWoiE2OXxGRMa5Ie7vIAm7sWV0RdBJdABcCdBbWY+wno8yKYTQ6YG94QxPHHe5+ym 0calll95+p+N+nVhlwkT2wdvs53iL/vT55NNXkhpCwxY+C7uHk+0z5fp12FD/RO1cG3K S6QKf4xS2dN/9yoxN/wkx8Glcb+tE30ckQeYFGb9VkP6fLhs4jNw3iE0qdTN19KWhgcX eDJt3txF/SFW9Fs1r/PIzgFEERDWPxV9IVZdH4VTt7ctkErmXuW1SWkDKNQr4uiKcl9z gEKaJvUkcDyE8nrmt5tteFaTpRqAOczLxttSOUy0C+4RHwQtYZrvEijHNbmDmXiNa7dQ ka3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726400646; x=1727005446; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MMukAaRv6lsduEQXd5W1x8cQrcsYqXKgAlv5XHYkQXQ=; b=eyua8PNXHVBNljb6dFmEbuCt4vzvfF7xIgQhCI1esxxhGAqe35v2MfYkWCw2j66pX8 4DCfhpC8drDJ8n3WP/1eDJ3uNIWNRP2+1Hwo7+tu/KpQ52aQ2Tr9MSA/1wGvtepS0Rxy chaA3OVGB0s1CCB0w4MEWnQeIGh9KsKr1FGowQ8KHhA7YdpLYPulIUwvxapnchw3TUib rfQhyoYrko9WLik9c/4KDMI0/wRr79PnhXimnhQ2gMauXnTw2E9fVVduG07+1U7R9cuy qH0pO0cGTac/jChfvgvvKvhkyyu0ODYT60DuZWZ+Ecoja2SmgtMkVMiLKtLtBYqgVTbO fz/Q== X-Forwarded-Encrypted: i=1; AJvYcCUtdw/r/jEFiL6VpbeekedNnynfTOdBrzs2LU3g//a+nAvOnAN8o5UIDwTHu6WO9vrWE/o=@lists.linux.dev X-Gm-Message-State: AOJu0YyYzKUe+rBdQIvB7r+1zBk8Rf+26S/151t6xOugnojra1hMgKaz vBduvAwZzCOFFgnDWJu8IUXfUogWPiwQqKLvuu0LfsBM+hKGpewE7Z2JP23m X-Google-Smtp-Source: AGHT+IE31cvGT/N6V95eA06b6sHMWCe5xvfNaDUEwVbsa4UyYKFSiLYAh+OpvI2B3F+xUi2OqHNUUQ== X-Received: by 2002:a17:907:26c3:b0:a72:50f7:3c6f with SMTP id a640c23a62f3a-a9029432757mr1209442066b.14.1726400645566; Sun, 15 Sep 2024 04:44:05 -0700 (PDT) Received: from playground.localdomain ([86.127.146.72]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a906109676esm188778266b.33.2024.09.15.04.44.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Sep 2024 04:44:04 -0700 (PDT) From: Laurentiu Mihalcea X-Google-Original-From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Philipp Zabel , Liu Ying , Sascha Hauer , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/3] dt-bindings: reset: add schema for imx8ulp SIM reset Date: Sun, 15 Sep 2024 07:43:09 -0400 Message-Id: <20240915114311.75496-2-laurentiu.mihalcea@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240915114311.75496-1-laurentiu.mihalcea@nxp.com> References: <20240915114311.75496-1-laurentiu.mihalcea@nxp.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add schema for imx8ulp's SIM reset controller. Signed-off-by: Liu Ying Signed-off-by: Laurentiu Mihalcea --- .../reset/nxp,imx8ulp-avd-sim-reset.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/nxp,imx8ulp-avd-sim-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/nxp,imx8ulp-avd-sim-reset.yaml b/Documentation/devicetree/bindings/reset/nxp,imx8ulp-avd-sim-reset.yaml new file mode 100644 index 000000000000..f6797966fd35 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nxp,imx8ulp-avd-sim-reset.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/nxp,imx8ulp-avd-sim-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8ULP System Integration Module Reset Controller + +maintainers: + - Liu Ying + +description: + Some instances of i.MX8ULP's SIM may offer control over the reset of some + components of a certain domain (example - AVD-SIM). + +properties: + compatible: + items: + - enum: + - nxp,imx8ulp-avd-sim-reset + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#reset-cells': + const: 1 + + mux-controller: + $ref: /schemas/mux/reg-mux.yaml# + +required: + - compatible + - reg + - clocks + - '#reset-cells' + - mux-controller + +additionalProperties: false + +examples: + - | + #include + syscon@2da50000 { + compatible = "nxp,imx8ulp-avd-sim-reset", "syscon"; + reg = <0x2da50000 0x38>; + clocks = <&pcc5 IMX8ULP_CLK_AVD_SIM>; + #reset-cells = <1>; + + mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x8 0x00000200>; + }; + }; From patchwork Sun Sep 15 11:43:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurentiu Mihalcea X-Patchwork-Id: 13804774 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF62D433AD for ; Sun, 15 Sep 2024 11:45:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726400702; cv=none; b=OWCm2cWZBdoKJ6EJTlViq71a/ZypIls4cPbc+ooqRdU0feT4JFFeZ5s76UbMjo6L9LaUlulaw2P3AQnblkTvPWH46tZmQ62N0yYE+XOnY1MCqgo4CwcupZBDFjuyv7i5ORqzYkwCRk6/ZV5XVOYHDqc/xBJgl5qEmz0LG20viW0= ARC-Message-Signature: i=1; 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Sun, 15 Sep 2024 04:44:58 -0700 (PDT) From: Laurentiu Mihalcea X-Google-Original-From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Philipp Zabel , Liu Ying , Sascha Hauer , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/3] reset: add driver for imx8ulp SIM reset controller Date: Sun, 15 Sep 2024 07:43:10 -0400 Message-Id: <20240915114311.75496-3-laurentiu.mihalcea@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240915114311.75496-1-laurentiu.mihalcea@nxp.com> References: <20240915114311.75496-1-laurentiu.mihalcea@nxp.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Certain components can be reset via the SIM module. Add reset controller driver for the SIM module to allow drivers for said components to control the reset signal(s). Signed-off-by: Liu Ying Signed-off-by: Laurentiu Mihalcea Reviewed-by: Daniel Baluta --- drivers/reset/Kconfig | 7 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-imx8ulp-sim.c | 106 ++++++++++++++++++++++++++++++ 3 files changed, 114 insertions(+) create mode 100644 drivers/reset/reset-imx8ulp-sim.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 5484a65f66b9..492081354d03 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -113,6 +113,13 @@ config RESET_IMX8MP_AUDIOMIX help This enables the reset controller driver for i.MX8MP AudioMix +config RESET_IMX8ULP_SIM + tristate "i.MX8ULP SIM Reset Driver" + depends on ARCH_MXC + help + This enables the SIM (System Integration Module) reset driver + for i.MX8ULP SoC. + config RESET_INTEL_GW bool "Intel Reset Controller Driver" depends on X86 || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 4411a2a124d7..38354e701811 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_RESET_GPIO) += reset-gpio.o obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o obj-$(CONFIG_RESET_IMX8MP_AUDIOMIX) += reset-imx8mp-audiomix.o +obj-$(CONFIG_RESET_IMX8ULP_SIM) += reset-imx8ulp-sim.o obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o obj-$(CONFIG_RESET_K210) += reset-k210.o obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o diff --git a/drivers/reset/reset-imx8ulp-sim.c b/drivers/reset/reset-imx8ulp-sim.c new file mode 100644 index 000000000000..04ff11d41e10 --- /dev/null +++ b/drivers/reset/reset-imx8ulp-sim.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_DPI_N 0 +#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_ESC_N 1 +#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_BYTE_N 2 + +#define IMX8ULP_SIM_RESET_NUM 3 + +#define AVD_SIM_SYSCTRL0 0x8 + +struct imx8ulp_sim_reset { + struct reset_controller_dev rcdev; + struct regmap *regmap; +}; + +static const u32 imx8ulp_sim_reset_bits[IMX8ULP_SIM_RESET_NUM] = { + [IMX8ULP_SIM_RESET_MIPI_DSI_RST_DPI_N] = BIT(3), + [IMX8ULP_SIM_RESET_MIPI_DSI_RST_ESC_N] = BIT(4), + [IMX8ULP_SIM_RESET_MIPI_DSI_RST_BYTE_N] = BIT(5), +}; + +static inline struct imx8ulp_sim_reset * +to_imx8ulp_sim_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct imx8ulp_sim_reset, rcdev); +} + +static int imx8ulp_sim_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct imx8ulp_sim_reset *simr = to_imx8ulp_sim_reset(rcdev); + const u32 bit = imx8ulp_sim_reset_bits[id]; + + return regmap_update_bits(simr->regmap, AVD_SIM_SYSCTRL0, bit, 0); +} + +static int imx8ulp_sim_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct imx8ulp_sim_reset *simr = to_imx8ulp_sim_reset(rcdev); + const u32 bit = imx8ulp_sim_reset_bits[id]; + + return regmap_update_bits(simr->regmap, AVD_SIM_SYSCTRL0, bit, bit); +} + +static const struct reset_control_ops imx8ulp_sim_reset_ops = { + .assert = imx8ulp_sim_reset_assert, + .deassert = imx8ulp_sim_reset_deassert, +}; + +static const struct of_device_id imx8ulp_sim_reset_dt_ids[] = { + { .compatible = "nxp,imx8ulp-avd-sim-reset", }, + { /* sentinel */ }, +}; + +static int imx8ulp_sim_reset_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct imx8ulp_sim_reset *simr; + int ret; + + simr = devm_kzalloc(dev, sizeof(*simr), GFP_KERNEL); + if (!simr) + return -ENOMEM; + + simr->regmap = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(simr->regmap)) + return dev_err_probe(&pdev->dev, PTR_ERR(simr->regmap), + "failed to get regmap\n"); + + simr->rcdev.owner = THIS_MODULE; + simr->rcdev.nr_resets = IMX8ULP_SIM_RESET_NUM; + simr->rcdev.ops = &imx8ulp_sim_reset_ops; + simr->rcdev.of_node = dev->of_node; + + ret = devm_of_platform_populate(dev); + if (ret) + return ret; + + return devm_reset_controller_register(dev, &simr->rcdev); +} + +static struct platform_driver imx8ulp_sim_reset_driver = { + .probe = imx8ulp_sim_reset_probe, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = imx8ulp_sim_reset_dt_ids, + }, +}; +module_platform_driver(imx8ulp_sim_reset_driver); + +MODULE_AUTHOR("Liu Ying "); +MODULE_DESCRIPTION("NXP i.MX8ULP System Integration Module Reset driver"); +MODULE_LICENSE("GPL"); From patchwork Sun Sep 15 11:43:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurentiu Mihalcea X-Patchwork-Id: 13804775 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C32BA1EA65 for ; Sun, 15 Sep 2024 11:45:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726400705; cv=none; b=f2c9TuPxoGs1xQtpjM+UXwTvyz+Yi3uL85xgWSKsmWFg+1ryjY8MawFD4qz0I7qNZCAiIKk2Oiy6V+apXD5oOxE/PuJkyFurZ+E7x4TL9ig9gpCJQIwRPEpMz+/hDrpUv0PDUfDGHf3Eim1JsvUqfNXiLA245WfcIo38fM9RbXo= ARC-Message-Signature: i=1; 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Sun, 15 Sep 2024 04:45:01 -0700 (PDT) From: Laurentiu Mihalcea X-Google-Original-From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Shawn Guo , Philipp Zabel , Liu Ying , Sascha Hauer , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/3] arm64: dts: imx8ulp: add AVD-SIM node Date: Sun, 15 Sep 2024 07:43:11 -0400 Message-Id: <20240915114311.75496-4-laurentiu.mihalcea@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240915114311.75496-1-laurentiu.mihalcea@nxp.com> References: <20240915114311.75496-1-laurentiu.mihalcea@nxp.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add node for imx8ulp's AVD-SIM module. This also includes its children. Signed-off-by: Liu Ying Signed-off-by: Laurentiu Mihalcea --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index e32d5afcf4a9..1ffa4da23042 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -614,6 +614,19 @@ per_bridge5: bus@2d800000 { #size-cells = <1>; ranges; + avd_sim: syscon@2da50000 { + compatible = "nxp,imx8ulp-avd-sim-reset", "syscon"; + reg = <0x2da50000 0x38>; + clocks = <&pcc5 IMX8ULP_CLK_AVD_SIM>; + #reset-cells = <1>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x8 0x00000200>; + }; + }; + cgc2: clock-controller@2da60000 { compatible = "fsl,imx8ulp-cgc2"; reg = <0x2da60000 0x10000>;