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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6cb254ead6fsm4583356d6.26.2024.09.25.08.25.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2024 08:25:15 -0700 (PDT) From: Gregory Price To: linux-acpi@vger.kernel.org, x86@kernel.org Cc: linux-kernel@vger.kernel.org, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, rafael@kernel.org, lenb@kernel.org, dan.j.williams@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, rrichter@amd.com, ytcoode@gmail.com, gourry@gourry.net, dave.jiang@intel.com, haibo1.xu@intel.com Subject: [RFC PATCH 1/2] x86/mm: if memblock size is adjusted, update the cached value Date: Wed, 25 Sep 2024 00:52:41 -0400 Message-ID: <20240925045242.3735-1-gourry@gourry.net> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When parsing CFMWS, we need to know the current block size expected to avoid accidentally adjusting the size upward. This causes a value to be cached in a static global. Update the static global if the value is subsequently updated. Print a warning that this has occurred for debugging purposes if blocksize is changed at an unexpected time. Signed-off-by: Gregory Price --- arch/x86/mm/init_64.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index ff253648706f..0db7ce11e5c5 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -1424,6 +1424,7 @@ void mark_rodata_ro(void) /* Adjustable memory block size */ static unsigned long set_memory_block_size; +static unsigned long memory_block_size_probed; int __init set_memory_block_size_order(unsigned int order) { unsigned long size = 1UL << order; @@ -1432,6 +1433,19 @@ int __init set_memory_block_size_order(unsigned int order) return -EINVAL; set_memory_block_size = size; + + /* + * If the block size has already been probed, we need to change it. + * This can happen during ACPI/CFMWS parsing, since it needs to + * probe the system for the existing block size to avoid increasing + * the block size if lower memory happens to be misaligned + */ + if (memory_block_size_probed) { + memory_block_size_probed = size; + pr_warn("x86/mm: Memory block size changed: %ldMB\n", + size >> 20); + } + return 0; } @@ -1471,7 +1485,6 @@ static unsigned long probe_memory_block_size(void) return bz; } -static unsigned long memory_block_size_probed; unsigned long memory_block_size_bytes(void) { if (!memory_block_size_probed) From patchwork Wed Sep 25 04:52:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory Price X-Patchwork-Id: 13812254 Received: from mail-qv1-f54.google.com (mail-qv1-f54.google.com [209.85.219.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1E086E614 for ; Wed, 25 Sep 2024 15:25:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727277921; cv=none; b=Y2UYr1e4ga1R5EbVD4GJib+DFysqHlsje7BWalgZzgN16vvg/IramVjuUeFU88BQykzaGdJyv/001M1m5Ybs8qkWQtojtYB6XNx6Dt07np9yJDfqpeNAqEWZ3CJTZoHIdXqmES71mQfnNNJkevlf4ON4ii0gcDim9T6F8L0dBws= ARC-Message-Signature: i=1; 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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6cb254ead6fsm4583356d6.26.2024.09.25.08.25.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2024 08:25:17 -0700 (PDT) From: Gregory Price To: linux-acpi@vger.kernel.org, x86@kernel.org Cc: linux-kernel@vger.kernel.org, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, rafael@kernel.org, lenb@kernel.org, dan.j.williams@intel.com, alison.schofield@intel.com, Jonathan.Cameron@huawei.com, rrichter@amd.com, ytcoode@gmail.com, gourry@gourry.net, dave.jiang@intel.com, haibo1.xu@intel.com Subject: [RFC PATCH 2/2] acpi,srat: reduce memory block size if CFMWS has a smaller alignment Date: Wed, 25 Sep 2024 00:52:42 -0400 Message-ID: <20240925045242.3735-2-gourry@gourry.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240925045242.3735-1-gourry@gourry.net> References: <20240925045242.3735-1-gourry@gourry.net> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The CXL Fixed Memory Window allows for memory aligned down to the size of 256MB. However, by default, memory blocks increase in size as total System RAM capacity increases. On x86, this caps out at 2G when 64GB of System RAM is reached. When the CFMWS regions are not 2GB aligned, this results in lost capacity on either side of the alignment - regardless of if the memory is mapped as normal system ram or hotplug. In ACPI, when the CFMWS is parsed, reduce the block size to the smallest amount detected if it is less than 2GB. Suggested-by: Dan Williams Signed-off-by: Gregory Price --- drivers/acpi/numa/srat.c | 44 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/acpi/numa/srat.c b/drivers/acpi/numa/srat.c index 44f91f2c6c5d..5074e6158dc7 100644 --- a/drivers/acpi/numa/srat.c +++ b/drivers/acpi/numa/srat.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -333,6 +334,35 @@ acpi_parse_memory_affinity(union acpi_subtable_headers *header, return 0; } +/* + * CXL allows CFMW to be aligned along 256MB boundaries, but larger + * memory systems typically default to ~2GB memory boundaries for + * memblocks. Calculate the largest supported alignment for all CFMWS. + * + * Only adjust downward if less than 2G, and error on invalid alignment. + */ +static int __init acpi_align_cfmws(union acpi_subtable_headers *header, + void *arg, const unsigned long table_end) +{ + struct acpi_cedt_cfmws *cfmws = (struct acpi_cedt_cfmws *)header; + u64 start = cfmws->base_hpa; + u64 size = cfmws->window_size; + unsigned long *fin_bz = arg; + unsigned long bz; + + for (bz = SZ_2G; bz >= SZ_256M; bz >>= 1) { + if (IS_ALIGNED(start, bz) && IS_ALIGNED(size, bz)) + break; + } + + if (bz < *fin_bz && bz >= SZ_256M) + *fin_bz = bz; + else if (bz < SZ_256M) + pr_err("CFMWS: [BIOS BUG] base/size alignment violates spec\n"); + + return 0; +} + static int __init acpi_parse_cfmws(union acpi_subtable_headers *header, void *arg, const unsigned long table_end) { @@ -501,6 +531,8 @@ acpi_table_parse_srat(enum acpi_srat_type id, int __init acpi_numa_init(void) { int i, fake_pxm, cnt = 0; + unsigned long block_sz = memory_block_size_bytes(); + unsigned long cfmw_align = block_sz; if (acpi_disabled) return -EINVAL; @@ -552,6 +584,18 @@ int __init acpi_numa_init(void) } last_real_pxm = fake_pxm; fake_pxm++; + + /* + * First parse the CFMWS to determine if the memory block size + * should be smaller than 2G. We don't care about larger sizes, + * this simply avoids losing memory to smaller alignements. + */ + acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, acpi_align_cfmws, + &cfmw_align); + if (cfmw_align < block_sz && cfmw_align >= SZ_256M) + set_memory_block_size_order(ffs(cfmw_align)-1); + + /* Then we need to make a pass to fill the numa nodes */ acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, acpi_parse_cfmws, &fake_pxm);