From patchwork Wed Sep 25 15:37:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13812272 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9D9CCCF9E7 for ; Wed, 25 Sep 2024 15:43:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 30C7310EA64; Wed, 25 Sep 2024 15:43:40 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=igalia.com header.i=@igalia.com header.b="W0WsIQUx"; dkim-atps=neutral Received: from fanzine2.igalia.com (fanzine.igalia.com [178.60.130.6]) by gabe.freedesktop.org (Postfix) with ESMTPS id 74FF710EA52; Wed, 25 Sep 2024 15:43:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=zPvVsOHukMZnajyg/RPQ+3mmZw7xkw50bkFZLNoHM5U=; b=W0WsIQUxRD87HD7c6zEYyqVMsE aE4zH2CN0/d+oEbYjHHHRfXYnQPIXGbxH1GGxm1Rfjqnd2uqJxTWH4U4pH1ZovWA5xh2+3rTtfN0t KTBDdU/tSiwmuV1Cox+X6Y/Fui++i8sC8bGtfncoOGyi6vSNgLDJZovkRLYjjRWUDYw5OexNbxxB6 YzAHOHIdcv/F81wk9fT5MY36ZErHhezQ35hEX9yC205oCRbJkYF4coWLxIiuxNXWE/5vt9oVI8Hlj lYaO785ANFvh8UXMYKXqNTjS0McmeStwe4mBLUaiqfkusxDK9TsjDjMaqSR0irHT9NI2xN0whLxMH bdUp1MJQ==; Received: from [189.6.17.125] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1stUAw-000y8P-TX; Wed, 25 Sep 2024 17:43:35 +0200 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 1/2] drm/amd/display: increase max surfaces in line with planes and streams Date: Wed, 25 Sep 2024 12:37:18 -0300 Message-ID: <20240925154324.348774-2-mwen@igalia.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240925154324.348774-1-mwen@igalia.com> References: <20240925154324.348774-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" 091a97e542cf ("drm/amd/display: Fix warning. Set MAX_SURFACES to 3") reduced the max number of surfaces since, at that time, there was no use for more. However, HW and driver evolves and there are now driver versions that allow two overlay planes (max_slave_planes). Moreover, commit 3cfd03b79425 ("drm/amd/display: update max streams per surface") states 6 is the max surfaces supported asics can have. Therefore, update MAX_SURFACES to match MAX_SURFACE_NUM, MAX_PLANES and MAX_STREAMS. It also addresses array-index-out-of-bounds reported in the link. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3594 Signed-off-by: Melissa Wen Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 3992ad73165b..08b00b263533 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -57,7 +57,7 @@ struct dmub_notification; #define DC_VER "3.2.301" -#define MAX_SURFACES 3 +#define MAX_SURFACES 6 #define MAX_PLANES 6 #define MAX_STREAMS 6 #define MIN_VIEWPORT_SIZE 12 From patchwork Wed Sep 25 15:37:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 13812273 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E77C0CCF9E4 for ; Wed, 25 Sep 2024 15:43:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6641910E121; Wed, 25 Sep 2024 15:43:48 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=igalia.com header.i=@igalia.com header.b="rDKkAfhN"; dkim-atps=neutral Received: from fanzine2.igalia.com (fanzine.igalia.com [178.60.130.6]) by gabe.freedesktop.org (Postfix) with ESMTPS id 54EDB10E122; Wed, 25 Sep 2024 15:43:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=1gZCCExOJ8BLuVIACQp6NZYsnDxOnwhLvgUxXVihlYE=; b=rDKkAfhNx83p4ILiehc8uXAq4C AaESzC7uqmsOlQJq4J4UiuU1KuQ4MpTRBRc5NIUL3jL9d0+xpCTJZIb2uW7T+GCh9xOKkuGTuJfrW y3XhHxy8mUpEqfaMI4TuD8wIzsHoy59VWEoCYMnSN9U4LwxV8d2BATRMOitRfF4WVMBxld7ngTJm7 u+Y6mrgkA0BuFkVEE3N6oTv2/zC4p+ijZdsQL3kRFrQr0bqB39ZIbIJlgc8/TpaizWjC6Yz3cwX+b uLSln+aWj7Hq9DTrqUTJ1yJb/do5AHRxl2Oo21tO+ux5ZbtvN3l3HLazgh/w8OMXoMK6ZfU5sKEoH JcGHAjog==; Received: from [189.6.17.125] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1stUB0-000y8P-R1; Wed, 25 Sep 2024 17:43:39 +0200 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 2/2] drm/amd/display: add warnings for MAX_SURFACES mismatch Date: Wed, 25 Sep 2024 12:37:19 -0300 Message-ID: <20240925154324.348774-3-mwen@igalia.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240925154324.348774-1-mwen@igalia.com> References: <20240925154324.348774-1-mwen@igalia.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" So that, in the future, when the max number of planes and streams increases, they might be synced with the number of surfaces to prevent array-index-out-of-bounds issues. Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6d12def3e8b3..95db2b1cc91a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3098,6 +3098,13 @@ static void dm_gpureset_commit_state(struct dc_state *dc_state, for (k = 0; k < dc_state->stream_count; k++) { bundle->stream_update.stream = dc_state->streams[k]; + if (MAX_SURFACES < dc_state->stream_status->plane_count) { + drm_warn(dm->ddev, "Not enough dc_surface_update for the " + "number of planes. Please increase " + "MAX_SURFACES inline to MAX_PLANES.\n"); + continue; + } + for (m = 0; m < dc_state->stream_status->plane_count; m++) { bundle->surface_updates[m].surface = dc_state->stream_status->plane_states[m]; @@ -8923,6 +8930,13 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, if (!dc_plane) continue; + if (MAX_SURFACES < planes_count) { + drm_warn(dev, "Not enough dc_surface_update for the " + "number of planes. Please increase " + "MAX_SURFACES inline to MAX_PLANES.\n"); + continue; + } + bundle->surface_updates[planes_count].surface = dc_plane; if (new_pcrtc_state->color_mgmt_changed) { bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction; @@ -9874,6 +9888,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) WARN_ON(!status->plane_count); + if (MAX_SURFACES < status->plane_count) { + drm_warn(dev, "Not enough dc_surface_update for the " + "number of planes. Please increase " + "MAX_SURFACES inline to MAX_PLANES.\n"); + continue; + } /* * TODO: DC refuses to perform stream updates without a dc_surface_update. * Here we create an empty update on each plane.