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Fri, 8 Mar 2019 14:12:36 +0100 Received: from lmecxl0923.lme.st.com (10.48.0.237) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 8 Mar 2019 14:12:36 +0100 From: Ludovic Barre To: Mark Brown , Marek Vasut , Boris Brezillon , Rob Herring Subject: [PATCH 1/2] spi: spi-mem: stm32-qspi: avoid memory corruption at low frequency Date: Fri, 8 Mar 2019 14:12:20 +0100 Message-ID: <1552050741-27739-2-git-send-email-ludovic.Barre@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552050741-27739-1-git-send-email-ludovic.Barre@st.com> References: <1552050741-27739-1-git-send-email-ludovic.Barre@st.com> MIME-Version: 1.0 X-Originating-IP: [10.48.0.237] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-08_11:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190308_051243_355216_620BF189 X-CRM114-Status: GOOD ( 10.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Alexandre Torgue , linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, Ludovic Barre , Maxime Coquelin , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ludovic Barre This patch solves a memory corruption seen at 8 MHz. To avoid such issue, timeout counter is disabled. Signed-off-by: Ludovic Barre --- drivers/spi/spi-stm32-qspi.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c index 3b2a9a6..7354f9d 100644 --- a/drivers/spi/spi-stm32-qspi.c +++ b/drivers/spi/spi-stm32-qspi.c @@ -76,7 +76,6 @@ #define QSPI_PSMAR 0x28 #define QSPI_PIR 0x2c #define QSPI_LPTR 0x30 -#define LPTR_DFT_TIMEOUT 0x10 #define STM32_QSPI_MAX_MMAP_SZ SZ_256M #define STM32_QSPI_MAX_NORCHIP 2 @@ -372,8 +371,7 @@ static int stm32_qspi_setup(struct spi_device *spi) flash->presc = presc; mutex_lock(&qspi->lock); - writel_relaxed(LPTR_DFT_TIMEOUT, qspi->io_base + QSPI_LPTR); - cr = FIELD_PREP(CR_FTHRES_MASK, 3) | CR_TCEN | CR_SSHIFT | CR_EN; + cr = FIELD_PREP(CR_FTHRES_MASK, 3) | CR_SSHIFT | CR_EN; writel_relaxed(cr, qspi->io_base + QSPI_CR); /* set dcr fsize to max address */ From patchwork Fri Mar 8 13:12:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ludovic BARRE X-Patchwork-Id: 10844679 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EE31B1390 for ; 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Fri, 08 Mar 2019 14:12:39 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 79E5D31; Fri, 8 Mar 2019 13:12:38 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4FBD25572; Fri, 8 Mar 2019 13:12:38 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas24.st.com (10.75.90.94) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 8 Mar 2019 14:12:38 +0100 Received: from lmecxl0923.lme.st.com (10.48.0.237) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Fri, 8 Mar 2019 14:12:37 +0100 From: Ludovic Barre To: Mark Brown , Marek Vasut , Boris Brezillon , Rob Herring Subject: [PATCH 2/2] spi: spi-mem: stm32-qspi: add suspend/resume support Date: Fri, 8 Mar 2019 14:12:21 +0100 Message-ID: <1552050741-27739-3-git-send-email-ludovic.Barre@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552050741-27739-1-git-send-email-ludovic.Barre@st.com> References: <1552050741-27739-1-git-send-email-ludovic.Barre@st.com> MIME-Version: 1.0 X-Originating-IP: [10.48.0.237] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-08_11:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190308_051244_019864_ED7A4304 X-CRM114-Status: GOOD ( 13.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Alexandre Torgue , linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, Ludovic Barre , Maxime Coquelin , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ludovic Barre This patch adds suspend and resume support for spi-stm32-qspi drivers. Signed-off-by: Ludovic Barre --- drivers/spi/spi-stm32-qspi.c | 39 +++++++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c index 7354f9d..3e8ca10 100644 --- a/drivers/spi/spi-stm32-qspi.c +++ b/drivers/spi/spi-stm32-qspi.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -101,6 +102,9 @@ struct stm32_qspi { struct completion data_completion; u32 fmode; + u32 cr_reg; + u32 dcr_reg; + /* * to protect device configuration, could be different between * 2 flash access (bk1, bk2) @@ -355,7 +359,7 @@ static int stm32_qspi_setup(struct spi_device *spi) struct spi_controller *ctrl = spi->master; struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl); struct stm32_qspi_flash *flash; - u32 cr, presc; + u32 presc; if (ctrl->busy) return -EBUSY; @@ -371,11 +375,12 @@ static int stm32_qspi_setup(struct spi_device *spi) flash->presc = presc; mutex_lock(&qspi->lock); - cr = FIELD_PREP(CR_FTHRES_MASK, 3) | CR_SSHIFT | CR_EN; - writel_relaxed(cr, qspi->io_base + QSPI_CR); + qspi->cr_reg = FIELD_PREP(CR_FTHRES_MASK, 3) | CR_SSHIFT | CR_EN; + writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR); /* set dcr fsize to max address */ - writel_relaxed(DCR_FSIZE_MASK, qspi->io_base + QSPI_DCR); + qspi->dcr_reg = DCR_FSIZE_MASK; + writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR); mutex_unlock(&qspi->lock); return 0; @@ -489,6 +494,31 @@ static int stm32_qspi_remove(struct platform_device *pdev) return 0; } +static int __maybe_unused stm32_qspi_suspend(struct device *dev) +{ + struct stm32_qspi *qspi = dev_get_drvdata(dev); + + clk_disable_unprepare(qspi->clk); + pinctrl_pm_select_sleep_state(dev); + + return 0; +} + +static int __maybe_unused stm32_qspi_resume(struct device *dev) +{ + struct stm32_qspi *qspi = dev_get_drvdata(dev); + + pinctrl_pm_select_default_state(dev); + clk_prepare_enable(qspi->clk); + + writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR); + writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR); + + return 0; +} + +SIMPLE_DEV_PM_OPS(stm32_qspi_pm_ops, stm32_qspi_suspend, stm32_qspi_resume); + static const struct of_device_id stm32_qspi_match[] = { {.compatible = "st,stm32f469-qspi"}, {} @@ -501,6 +531,7 @@ static struct platform_driver stm32_qspi_driver = { .driver = { .name = "stm32-qspi", .of_match_table = stm32_qspi_match, + .pm = &stm32_qspi_pm_ops, }, }; module_platform_driver(stm32_qspi_driver);