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From: "Andrei Cherechesu (OSS)" To: xen-devel@lists.xenproject.org Cc: andrei.cherechesu@oss.nxp.com, S32@nxp.com, Andrei Cherechesu , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Jan Beulich , s32@nxp.com Subject: [PATCH v2 1/8] xen/arm: Add NXP LINFlexD UART Driver Date: Mon, 30 Sep 2024 14:47:07 +0300 Message-ID: <20240930114715.642978-2-andrei.cherechesu@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930114715.642978-1-andrei.cherechesu@oss.nxp.com> References: <20240930114715.642978-1-andrei.cherechesu@oss.nxp.com> X-ClientProxiedBy: AM0PR10CA0016.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:208:17c::26) To PA4PR04MB9565.eurprd04.prod.outlook.com (2603:10a6:102:26b::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PA4PR04MB9565:EE_|AS8PR04MB8357:EE_ X-MS-Office365-Filtering-Correlation-Id: dfbdb444-a6bd-408d-2995-08dce145aac2 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|52116014|1800799024|366016|38350700014; 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S32G3 Reference Manual: https://www.nxp.com/webapp/Download?colCode=RMS32G3. Signed-off-by: Andrei Cherechesu Signed-off-by: Peter van der Perk Acked-by: Julien Grall --- xen/arch/arm/include/asm/linflex-uart.h | 63 ++++ xen/drivers/char/Kconfig | 8 + xen/drivers/char/Makefile | 1 + xen/drivers/char/linflex-uart.c | 381 ++++++++++++++++++++++++ 4 files changed, 453 insertions(+) create mode 100644 xen/arch/arm/include/asm/linflex-uart.h create mode 100644 xen/drivers/char/linflex-uart.c diff --git a/xen/arch/arm/include/asm/linflex-uart.h b/xen/arch/arm/include/asm/linflex-uart.h new file mode 100644 index 0000000000..95dcbcb476 --- /dev/null +++ b/xen/arch/arm/include/asm/linflex-uart.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * xen/arch/arm/include/asm/linflex-uart.h + * + * Common constant definition between early printk and the UART driver + * for NXP LINFlexD UART. + * + * Andrei Cherechesu + * Copyright 2018, 2021, 2024 NXP + */ + +#ifndef __ASM_ARM_LINFLEX_UART_H +#define __ASM_ARM_LINFLEX_UART_H + +/* 32-bit register offsets */ +#define LINCR1 (0x0) +#define LINIER (0x4) +#define LINSR (0x8) +#define UARTCR (0x10) +#define UARTSR (0x14) +#define LINFBRR (0x24) +#define LINIBRR (0x28) +#define BDRL (0x38) +#define BDRM (0x3C) +#define UARTPTO (0x50) + +#define LINCR1_INIT BIT(0, U) +#define LINCR1_MME BIT(4, U) +#define LINCR1_BF BIT(7, U) + +#define LINSR_LINS GENMASK(15, 12) +#define LINSR_LINS_INIT BIT(12, U) + +#define LINIER_DRIE BIT(2, U) +#define LINIER_DTIE BIT(1, U) + +#define UARTCR_UART BIT(0, U) +#define UARTCR_WL0 BIT(1, U) +#define UARTCR_PC0 BIT(3, U) +#define UARTCR_TXEN BIT(4, U) +#define UARTCR_RXEN BIT(5, U) +#define UARTCR_PC1 BIT(6, U) +#define UARTCR_TFBM BIT(8, U) +#define UARTCR_RFBM BIT(9, U) +#define UARTCR_RDFLRFC GENMASK(12, 10) +#define UARTCR_TDFLTFC GENMASK(15, 13) +#define UARTCR_ROSE BIT(23, U) +#define UARTCR_OSR_SHIFT (24) +#define UARTCR_OSR GENMASK(27, UARTCR_OSR_SHIFT) + +#define UARTSR_DTFTFF BIT(1, U) +#define UARTSR_DRFRFE BIT(2, U) + +#endif /* __ASM_ARM_LINFLEX_UART_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/drivers/char/Kconfig b/xen/drivers/char/Kconfig index 3f836ab301..e175d07c02 100644 --- a/xen/drivers/char/Kconfig +++ b/xen/drivers/char/Kconfig @@ -13,6 +13,14 @@ config HAS_CADENCE_UART This selects the Xilinx Zynq Cadence UART. If you have a Xilinx Zynq based board, say Y. +config HAS_LINFLEX + bool "NXP LINFlexD UART driver" + default y + depends on ARM_64 + help + This selects the NXP LINFlexD UART. If you have an NXP S32G or S32R + based board, say Y. + config HAS_IMX_LPUART bool "i.MX LPUART driver" default y diff --git a/xen/drivers/char/Makefile b/xen/drivers/char/Makefile index e7e374775d..d3b987da1d 100644 --- a/xen/drivers/char/Makefile +++ b/xen/drivers/char/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_HAS_SCIF) += scif-uart.o obj-$(CONFIG_HAS_EHCI) += ehci-dbgp.o obj-$(CONFIG_XHCI) += xhci-dbc.o obj-$(CONFIG_HAS_IMX_LPUART) += imx-lpuart.o +obj-$(CONFIG_HAS_LINFLEX) += linflex-uart.o obj-$(CONFIG_ARM) += arm-uart.o obj-y += serial.o obj-$(CONFIG_XEN_GUEST) += xen_pv_console.o diff --git a/xen/drivers/char/linflex-uart.c b/xen/drivers/char/linflex-uart.c new file mode 100644 index 0000000000..2fa195cbf6 --- /dev/null +++ b/xen/drivers/char/linflex-uart.c @@ -0,0 +1,381 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * xen/drivers/char/linflex-uart.c + * + * Driver for NXP LINFlexD UART. + * + * Andrei Cherechesu + * Copyright 2018, 2021-2022, 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LINFLEX_CLK_FREQ (125000000) +#define LINFLEX_MAX_BAUDRATE (2000000) +#define LINFLEX_BAUDRATE (115200) +#define LINFLEX_LDIV_MULTIPLIER (16) + +static struct linflex_uart { + uint32_t baud, clock_hz; + uint32_t irq; + char __iomem *regs; + struct irqaction irqaction; + struct vuart_info vuart; +} linflex_com; + +static uint32_t linflex_uart_readl(const struct linflex_uart *uart, + uint32_t off) +{ + return readl(uart->regs + off); +} + +static void linflex_uart_writel(const struct linflex_uart *uart, uint32_t off, + uint32_t val) +{ + writel(val, uart->regs + off); +} + +static void linflex_uart_writeb(const struct linflex_uart *uart, uint32_t off, + uint8_t val) +{ + writeb(val, uart->regs + off); +} + +static uint32_t linflex_uart_get_osr(uint32_t uartcr) +{ + return (uartcr & UARTCR_OSR) >> UARTCR_OSR_SHIFT; +} + +static bool linflex_uart_tx_fifo_mode(const struct linflex_uart *uart) +{ + return !!(linflex_uart_readl(uart, UARTCR) & UARTCR_TFBM); +} + +static bool linflex_uart_rx_fifo_mode(const struct linflex_uart *uart) +{ + return !!(linflex_uart_readl(uart, UARTCR) & UARTCR_RFBM); +} + +static uint32_t linflex_uart_ldiv_multiplier(const struct linflex_uart *uart) +{ + uint32_t uartcr, mul = LINFLEX_LDIV_MULTIPLIER; + + uartcr = linflex_uart_readl(uart, UARTCR); + if ( uartcr & UARTCR_ROSE ) + mul = linflex_uart_get_osr(uartcr); + + return mul; +} + +static void linflex_uart_flush(struct serial_port *port) +{ + const struct linflex_uart *uart = port->uart; + + if ( linflex_uart_tx_fifo_mode(uart) ) + while ( linflex_uart_readl(uart, UARTCR) & UARTCR_TDFLTFC ) + cpu_relax(); + + if ( linflex_uart_rx_fifo_mode(uart) ) + while ( linflex_uart_readl(uart, UARTCR) & UARTCR_RDFLRFC ) + cpu_relax(); +} + +static void __init linflex_uart_init_preirq(struct serial_port *port) +{ + struct linflex_uart *uart = port->uart; + uint32_t ibr, fbr, divisr, dividr, ctrl; + + /* Disable RX/TX before init mode */ + ctrl = linflex_uart_readl(uart, UARTCR); + ctrl &= ~(UARTCR_RXEN | UARTCR_TXEN); + linflex_uart_writel(uart, UARTCR, ctrl); + + /* + * Smoothen the transition from early_printk by waiting + * for all pending characters to transmit + */ + linflex_uart_flush(port); + + /* Init mode */ + ctrl = LINCR1_INIT; + linflex_uart_writel(uart, LINCR1, ctrl); + + /* Waiting for init mode entry */ + while ( (linflex_uart_readl(uart, LINSR) & LINSR_LINS) != LINSR_LINS_INIT ) + cpu_relax(); + + /* Set Master Mode */ + ctrl |= LINCR1_MME; + linflex_uart_writel(uart, LINCR1, ctrl); + + if ( uart->baud > LINFLEX_MAX_BAUDRATE ) + uart->baud = LINFLEX_MAX_BAUDRATE; + + /* Provide data bits, parity, stop bit, etc */ + divisr = uart->clock_hz; + dividr = uart->baud * linflex_uart_ldiv_multiplier(uart); + + ibr = divisr / dividr; + fbr = ((divisr % dividr) * 16 / dividr) & 0xF; + + linflex_uart_writel(uart, LINIBRR, ibr); + linflex_uart_writel(uart, LINFBRR, fbr); + + /* Set preset timeout register value */ + linflex_uart_writel(uart, UARTPTO, 0xF); + + /* Setting UARTCR[UART] bit is required for writing other bits in UARTCR */ + linflex_uart_writel(uart, UARTCR, UARTCR_UART); + + /* 8 bit data, no parity, UART mode, Buffer mode */ + linflex_uart_writel(uart, UARTCR, UARTCR_PC1 | UARTCR_PC0 | UARTCR_WL0 | + UARTCR_UART); + + /* end init mode */ + ctrl = linflex_uart_readl(uart, LINCR1); + ctrl &= ~LINCR1_INIT; + linflex_uart_writel(uart, LINCR1, ctrl); + + /* Enable RX/TX after exiting init mode */ + ctrl = linflex_uart_readl(uart, UARTCR); + ctrl |= UARTCR_RXEN | UARTCR_TXEN; + linflex_uart_writel(uart, UARTCR, ctrl); +} + +static void linflex_uart_interrupt(int irq, void *data) +{ + struct serial_port *port = data; + const struct linflex_uart *uart = port->uart; + uint32_t sts; + + sts = linflex_uart_readl(uart, UARTSR); + + if ( sts & UARTSR_DRFRFE ) + serial_rx_interrupt(port); + + if ( sts & UARTSR_DTFTFF ) + serial_tx_interrupt(port); +} + +static void __init linflex_uart_init_postirq(struct serial_port *port) +{ + struct linflex_uart *uart = port->uart; + uint32_t temp; + + uart->irqaction.handler = linflex_uart_interrupt; + uart->irqaction.name = "linflex_uart"; + uart->irqaction.dev_id = port; + + if ( setup_irq(uart->irq, 0, &uart->irqaction) != 0 ) + { + printk("linflex-uart: Failed to allocate IRQ %d\n", uart->irq); + return; + } + + /* Enable interrupts */ + temp = linflex_uart_readl(uart, LINIER); + temp |= (LINIER_DRIE | LINIER_DTIE); + linflex_uart_writel(uart, LINIER, temp); + printk("linflex-uart: IRQ %d enabled\n", uart->irq); +} + +static int linflex_uart_tx_ready(struct serial_port *port) +{ + const struct linflex_uart *uart = port->uart; + + if ( linflex_uart_tx_fifo_mode(uart) ) + return (linflex_uart_readl(uart, UARTSR) & UARTSR_DTFTFF) == 0 ? 1 : 0; + + /* + * Buffer Mode => TX is waited to be ready after sending a char, + * so we can assume it is always ready before. + */ + return 1; +} + +static void linflex_uart_putc(struct serial_port *port, char c) +{ + const struct linflex_uart *uart = port->uart; + uint32_t uartsr; + + if ( c == '\n' ) + linflex_uart_putc(port, '\r'); + + linflex_uart_writeb(uart, BDRL, c); + + /* Buffer Mode */ + if ( !linflex_uart_tx_fifo_mode(uart) ) + { + while ( (linflex_uart_readl(uart, UARTSR) & UARTSR_DTFTFF) == 0 ) + cpu_relax(); + + uartsr = linflex_uart_readl(uart, UARTSR) | (UARTSR_DTFTFF); + linflex_uart_writel(uart, UARTSR, uartsr); + } +} + +static int linflex_uart_getc(struct serial_port *port, char *pc) +{ + const struct linflex_uart *uart = port->uart; + uint32_t ch, uartsr, rx_fifo_mode; + + rx_fifo_mode = linflex_uart_rx_fifo_mode(uart); + + if ( rx_fifo_mode ) + while ( linflex_uart_readl(uart, UARTSR) & UARTSR_DRFRFE ) + cpu_relax(); + else + while ( !(linflex_uart_readl(uart, UARTSR) & UARTSR_DRFRFE) ) + cpu_relax(); + + ch = linflex_uart_readl(uart, BDRM); + *pc = ch & 0xff; + + if ( !rx_fifo_mode ) { + uartsr = linflex_uart_readl(uart, UARTSR) | UARTSR_DRFRFE; + linflex_uart_writel(uart, UARTSR, uartsr); + } + + return 1; +} + +static int __init linflex_uart_irq(struct serial_port *port) +{ + const struct linflex_uart *uart = port->uart; + + return ((uart->irq > 0) ? uart->irq : -1); +} + +static const struct vuart_info *linflex_vuart_info(struct serial_port *port) +{ + const struct linflex_uart *uart = port->uart; + + return &uart->vuart; +} + +static void linflex_uart_start_tx(struct serial_port *port) +{ + const struct linflex_uart *uart = port->uart; + uint32_t temp; + + temp = linflex_uart_readl(uart, LINIER); + linflex_uart_writel(uart, LINIER, temp | LINIER_DTIE); +} + +static void linflex_uart_stop_tx(struct serial_port *port) +{ + const struct linflex_uart *uart = port->uart; + uint32_t temp; + + temp = linflex_uart_readl(uart, LINIER); + temp &= ~(LINIER_DTIE); + linflex_uart_writel(uart, LINIER, temp); +} + +static struct uart_driver __read_mostly linflex_uart_driver = { + .init_preirq = linflex_uart_init_preirq, + .init_postirq = linflex_uart_init_postirq, + .tx_ready = linflex_uart_tx_ready, + .putc = linflex_uart_putc, + .flush = linflex_uart_flush, + .getc = linflex_uart_getc, + .irq = linflex_uart_irq, + .start_tx = linflex_uart_start_tx, + .stop_tx = linflex_uart_stop_tx, + .vuart_info = linflex_vuart_info, +}; + +static int __init linflex_uart_init(struct dt_device_node *dev, const void *data) +{ + const char *config = data; + struct linflex_uart *uart; + paddr_t addr, size; + uint32_t baud = 0; + int res; + + if ( strcmp(config, "") ) + { + baud = simple_strtoul(config, &config, 10); + if ( strcmp(config, "") ) + printk("linflex-uart: Only baud rate is configurable, discarding other options: %s\n", + config); + } + else + { + /* Configuration not provided, use a default one */ + baud = LINFLEX_BAUDRATE; + printk("linflex-uart: Baud rate not provided, using %d as default\n", + baud); + } + + uart = &linflex_com; + + res = dt_device_get_paddr(dev, 0, &addr, &size); + if ( res ) + { + printk("linflex-uart: Unable to retrieve the base address of the UART\n"); + return res; + } + + res = platform_get_irq(dev, 0); + if ( res < 0 ) + { + printk("linflex-uart: Unable to retrieve the IRQ\n"); + return -EINVAL; + } + uart->irq = res; + + uart->regs = ioremap_nocache(addr, size); + if ( !uart->regs ) + { + printk("linflex-uart: Unable to map the UART memory\n"); + return -ENOMEM; + } + + uart->baud = baud; + uart->clock_hz = LINFLEX_CLK_FREQ; + + uart->vuart.base_addr = addr; + uart->vuart.size = size; + uart->vuart.data_off = BDRL; + uart->vuart.status_off = UARTSR; + uart->vuart.status = UARTSR_DTFTFF; + + /* Register with generic serial driver */ + serial_register_uart(SERHND_DTUART, &linflex_uart_driver, uart); + + dt_device_set_used_by(dev, DOMID_XEN); + + return 0; +} + +static const struct dt_device_match linflex_uart_dt_compat[] __initconst = +{ + DT_MATCH_COMPATIBLE("nxp,s32g2-linflexuart"), + DT_MATCH_COMPATIBLE("nxp,s32g3-linflexuart"), + DT_MATCH_COMPATIBLE("fsl,s32v234-linflexuart"), + { /* sentinel */ }, +}; + +DT_DEVICE_START(linflex_uart, "NXP LINFlexD UART", DEVICE_SERIAL) + .dt_match = linflex_uart_dt_compat, + .init = linflex_uart_init, +DT_DEVICE_END + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Sep 30 11:47:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrei Cherechesu X-Patchwork-Id: 13815925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2B0ACF64A0 for ; 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Signed-off-by: Andrei Cherechesu Signed-off-by: Peter van der Perk Acked-by: Julien Grall --- xen/arch/arm/Kconfig.debug | 12 ++++++ xen/arch/arm/arm64/debug-linflex.inc | 58 ++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) create mode 100644 xen/arch/arm/arm64/debug-linflex.inc diff --git a/xen/arch/arm/Kconfig.debug b/xen/arch/arm/Kconfig.debug index 2fa0acd2a3..7660e599c0 100644 --- a/xen/arch/arm/Kconfig.debug +++ b/xen/arch/arm/Kconfig.debug @@ -44,6 +44,14 @@ choice Say Y here if you wish the early printk to direct their output to a i.MX LPUART. + config EARLY_UART_CHOICE_LINFLEX + select EARLY_UART_LINFLEX + depends on ARM_64 + bool "Early printk via NXP LINFlexD UART" + help + Say Y here if you wish the early printk to direct their + output to an NXP LINFlexD UART. + config EARLY_UART_CHOICE_MESON select EARLY_UART_MESON depends on ARM_64 @@ -89,6 +97,9 @@ config EARLY_UART_EXYNOS4210 config EARLY_UART_IMX_LPUART select EARLY_PRINTK bool +config EARLY_UART_LINFLEX + select EARLY_PRINTK + bool config EARLY_UART_MESON select EARLY_PRINTK bool @@ -167,6 +178,7 @@ config EARLY_PRINTK_INC default "debug-cadence.inc" if EARLY_UART_CADENCE default "debug-exynos4210.inc" if EARLY_UART_EXYNOS4210 default "debug-imx-lpuart.inc" if EARLY_UART_IMX_LPUART + default "debug-linflex.inc" if EARLY_UART_LINFLEX default "debug-meson.inc" if EARLY_UART_MESON default "debug-mvebu.inc" if EARLY_UART_MVEBU default "debug-pl011.inc" if EARLY_UART_PL011 diff --git a/xen/arch/arm/arm64/debug-linflex.inc b/xen/arch/arm/arm64/debug-linflex.inc new file mode 100644 index 0000000000..cf4f5ce224 --- /dev/null +++ b/xen/arch/arm/arm64/debug-linflex.inc @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * xen/arch/arm/arm64/debug-linflex.inc + * + * NXP LINFlexD UART specific debug code + * + * Andrei Cherechesu + * Copyright 2018, 2021, 2023-2024 NXP + */ + +#include +#include + +/* + * wait LINFlexD UART to be ready to transmit + * xb: register which contains the UART base address + * c: scratch register number + */ +.macro early_uart_ready xb, c + ldr w\c, [\xb, #UARTCR] /* <= Control Register */ + and w\c, w\c, #UARTCR_TFBM /* Check Buffer/FIFO (0/1) Mode */ + cbz w\c, 2f /* Buffer Mode => return */ +1: + ldrb w\c, [\xb, #UARTSR] /* <= Status Register */ + tst w\c, #UARTSR_DTFTFF /* FIFO Mode => Check DTF bit */ + b.ne 1b +2: +.endm + +/* + * LINFlexD UART transmit character + * xb: register which contains the UART base address + * wt: register which contains the character to transmit + */ +.macro early_uart_transmit xb, wt + strb \wt, [\xb, #BDRL] + + ldr \wt, [\xb, #UARTCR] /* <= Control Register */ + and \wt, \wt, #UARTCR_TFBM /* Check Buffer/FIFO (0/1) Mode */ + cbnz \wt, 2f /* FIFO Mode => goto exit */ + +3: /* Buffer Mode */ + ldrb \wt, [\xb, #UARTSR] /* <= Status Register */ + and \wt, \wt, #UARTSR_DTFTFF /* Check Transmission Completed */ + cbz \wt, 3b + + ldr \wt, [\xb, #UARTSR] /* <= Status Register */ + orr \wt, \wt, #UARTSR_DTFTFF /* Clear DTF bit */ + str \wt, [\xb, #UARTSR] +2: +.endm + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Sep 30 11:47:09 2024 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7Ngxtn/jbSYmDMNZnmH5DldOaodu+aNHgW7UImEj+kbiIhKllx+I+1qSjWyiODHEd53SR+thcG+7SNO4bHOuf3cpjxQ4cuhYsVkZ/U18Ue5wGpB/F2jtBZ3PV0jTMDq8XrKmVdigecBXyP/YrO4Omg8tkco2mKH4FyYrVz/vEJD1cx/8xeb9ow7k4GkoJTjHmZ1FAVXxHP0cmN8bwtT/6zF/dFxHXxpzGFoaRMaZi2Z6OBwg7d3BIpYisk72TfgmgZLXRJ+X95wfIJdM4LO2hDKbMHXfM9489O45lMLqxKpkRnxxeXVBBMik40WnLvnrbzBzJeikuZNqtm8ued2svrQHtm8295ONNIUXcu0IgiJWhNJrjNyzS3bT8PaSvNg54dlbkiL2h+J8f4XHY/zevwR2G/G76CYBCb8YUHmb3rVTzJKUC2kaOwpGKm+xZRy0jEEclDFOyhfbjVhvgYh2y6dOicXsUo4cVwnPZTRoPpIm850Bnq3JU67ZbqwA/sQkNEKeTeei2J1762eKoHMmO111/qrBRz6ip8/mLxzyd4KxIAt7hrkmkQ4/zZoecTGcL+OkT42Hk9/Gt0Y4A7d+K5+h9smfpzgiJkI81DmzoqS9BnQz6Oqb5ZgjcIr31Hovyin8m6ms33qOjo7VjwLEDJdi4ZPVcsN7HqMbn0oYbxhrkmCZl3bbtYrNnMBe4je+56VroLWLLmUX8T8jTpNe8GXyQswFhZeA6SbQOeRgxJmjuVOD9CssehkoqGnc3Ynf81wK6aUJpU1fvL/FRX6eLyt0zwT5RBLSw2W+sgUAfcWt/MNmc5PjISA/qqC5+oWYblF8IE1pzf0Y8keXGUm5yoz1i1pYsngB1+ndH+NRVsgENkqDriGt4l9/lbRB/rYrCJXDNjYopgSun9GbJlIqV+pt5O/Q61JGlqf0P4CSwXfQtruWAsrZjFNQ6yN6MrO0XFj/dBhWNWrUxoOMtRn4JhXzxdjQKhQO7mTrLxKmNOqsBmqybJUBKRXk+NksJOfjF0LFZY4d/gZFYtrvq73XZA+pKbEH46blr5UE/3Nw/ZKIHM1H9b4S3Z80x6/WDymGCNnvMSpROwt4579iDQ5N8yaSyVGSDNRljzapycw5Ofq4ZHFbBy9FbPvV3FGr1AIXElb+oScj3xfyhSbrpFGvURaG7BL76wpZQDhHN0QQnQH7N6gqqqcMyc6seZU9/5WPt96+Uy313fgdSO4L21AHjsph731pipj6QQ+/ZjMrKjAgeSGxE6bs9HSW7XFNhFRDOdLbcaXe0QqzsyDZgnLI7X/qS1xDbs4eHyKLFWzMzwILptoJm69p8s2mvkWqD84DxytWLPE7p6dkcE1atB0zAdDaUfvUWF8irKC3Un2jMRKWFFCUGQoct56sOTqBzuCvw+v6jHIW0PR0xrwFkokPVAiCF/DJAdpIn5G0t4vVBA/hr+RlI+m3KxkY7d37UrKSZ1ODgFzio/EFyZKa22WdgZkK86UA5oIV6xbMtQWFhIXJkLWKLnimgAN1fzM6jZ4oNobxZy37m5ndO5r/jZ9lKrGC53HrAmjyPjsXO5vw9SEC608Sp/gWLKTIHd6GkudpX1wOu6x1eROTQruXc3Vriw== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1219c388-7294-4ce3-2c00-08dce145ac24 X-MS-Exchange-CrossTenant-AuthSource: PA4PR04MB9565.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2024 11:47:33.9135 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WNmPZTRZGzEXgxXI0ncRT7H0U892NdjTA78EqCQqYusXWUb2EDPqy6NsoZsK+FrH7yuuTeGU7JfCYHL3j9fZgEtxA76xq3QKof/izrUvn8I= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB8357 From: Andrei Cherechesu Introduce the SCMI layer to have some basic degree of awareness about SMC calls that are based on the ARM System Control and Management Interface (SCMI) specification (DEN0056E). The SCMI specification includes various protocols for managing system-level resources, such as: clocks, pins, reset, system power, power domains, performance domains, etc. The clients are named "SCMI agents" and the server is named "SCMI platform". Only support the shared-memory based transport with SMCs as the doorbell mechanism for notifying the platform. Also, this implementation only handles the "arm,scmi-smc" compatible, requiring the following properties: - "arm,smc-id" (unique SMC ID) - "shmem" (one or more phandles pointing to shmem zones for each channel) The initialization is done as 'presmp_initcall', since we need SMCs and PSCI should already probe EL3 FW for supporting SMCCC. If no "arm,scmi-smc" compatible node is found in Dom0's DT, the initialization fails silently, as it's not mandatory. Otherwise, we get the 'arm,smc-id' DT property from the node, to know the SCMI SMC ID we handle. The 'shmem' memory ranges are not validated, as the SMC calls are only passed through to EL3 FW if coming from Dom0 and as if Dom0 would be natively running. Signed-off-by: Andrei Cherechesu Reviewed-by: Stefano Stabellini --- xen/arch/arm/Kconfig | 10 ++ xen/arch/arm/Makefile | 1 + xen/arch/arm/include/asm/scmi-smc.h | 52 +++++++++ xen/arch/arm/scmi-smc.c | 163 ++++++++++++++++++++++++++++ 4 files changed, 226 insertions(+) create mode 100644 xen/arch/arm/include/asm/scmi-smc.h create mode 100644 xen/arch/arm/scmi-smc.c diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 323c967361..adf53e2de1 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -245,6 +245,16 @@ config PARTIAL_EMULATION not been emulated to their complete functionality. Enabling this might result in unwanted/non-spec compliant behavior. +config SCMI_SMC + bool "Enable forwarding SCMI over SMC calls from Dom0 to EL3 firmware" + default y + help + This option enables basic awareness for SCMI calls using SMC as + doorbell mechanism and Shared Memory for transport ("arm,scmi-smc" + compatible only). The value of "arm,smc-id" DT property from SCMI + firmware node is used to trap and forward corresponding SCMI SMCs + to firmware running at EL3, if the call comes from Dom0. + endmenu menu "ARM errata workaround via the alternative framework" diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 7792bff597..b85ad9c13f 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -45,6 +45,7 @@ obj-y += platform_hypercall.o obj-y += physdev.o obj-y += processor.o obj-y += psci.o +obj-$(CONFIG_SCMI_SMC) += scmi-smc.o obj-y += setup.o obj-y += shutdown.o obj-y += smp.o diff --git a/xen/arch/arm/include/asm/scmi-smc.h b/xen/arch/arm/include/asm/scmi-smc.h new file mode 100644 index 0000000000..c6c0079e86 --- /dev/null +++ b/xen/arch/arm/include/asm/scmi-smc.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * xen/arch/arm/include/asm/scmi-smc.h + * + * ARM System Control and Management Interface (SCMI) over SMC + * Generic handling layer + * + * Andrei Cherechesu + * Copyright 2024 NXP + */ + +#ifndef __ASM_SCMI_SMC_H__ +#define __ASM_SCMI_SMC_H__ + +#include +#include + +#ifdef CONFIG_SCMI_SMC + +bool scmi_is_enabled(void); +bool scmi_is_valid_smc_id(uint32_t fid); +bool scmi_handle_smc(struct cpu_user_regs *regs); + +#else + +static inline bool scmi_is_enabled(void) +{ + return false; +} + +static inline bool scmi_is_valid_smc_id(uint32_t fid) +{ + return false; +} + +static inline bool scmi_handle_smc(struct cpu_user_regs *regs) +{ + return false; +} + +#endif /* CONFIG_SCMI_SMC */ + +#endif /* __ASM_SCMI_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/scmi-smc.c b/xen/arch/arm/scmi-smc.c new file mode 100644 index 0000000000..373ca7ba5f --- /dev/null +++ b/xen/arch/arm/scmi-smc.c @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * xen/arch/arm/scmi-smc.c + * + * ARM System Control and Management Interface (SCMI) over SMC + * Generic handling layer + * + * Andrei Cherechesu + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define SCMI_SMC_ID_PROP "arm,smc-id" + +static bool scmi_support; +static uint32_t scmi_smc_id; + +/* Check if SCMI layer correctly initialized and can be used. */ +bool scmi_is_enabled(void) +{ + return scmi_support; +} + +/* + * Check if provided SMC Function Identifier matches the one known by the SCMI + * layer, as read from DT prop 'arm,smc-id' during initialiation. + */ +bool scmi_is_valid_smc_id(uint32_t fid) +{ + return (fid == scmi_smc_id); +} + +/* + * Generic handler for SCMI-SMC requests, currently only forwarding the + * request to FW running at EL3 if it came from Dom0. Is called from the vSMC + * layer for SiP SMCs, since SCMI calls are usually provided this way. + * Can also be called from `platform_smc()` plat-specific callback. + * + * Returns true if SMC was handled (regardless of response), false otherwise. + */ +bool scmi_handle_smc(struct cpu_user_regs *regs) +{ + struct arm_smccc_res res; + + /* Only the hardware domain should use SCMI calls */ + if ( !is_hardware_domain(current->domain) ) + { + gprintk(XENLOG_ERR, "SCMI: Unprivileged d%d cannot use SCMI.\n", + current->domain->domain_id); + return false; + } + + /* For the moment, forward the SCMI Request to FW running at EL3 */ + arm_smccc_1_1_smc(scmi_smc_id, + get_user_reg(regs, 1), + get_user_reg(regs, 2), + get_user_reg(regs, 3), + get_user_reg(regs, 4), + get_user_reg(regs, 5), + get_user_reg(regs, 6), + get_user_reg(regs, 7), + &res); + + set_user_reg(regs, 0, res.a0); + set_user_reg(regs, 1, res.a1); + set_user_reg(regs, 2, res.a2); + set_user_reg(regs, 3, res.a3); + + return true; +} + +static int __init scmi_check_smccc_ver(void) +{ + if ( smccc_ver < ARM_SMCCC_VERSION_1_1 ) + { + printk(XENLOG_ERR + "SCMI: No SMCCC 1.1 support, SCMI calls forwarding disabled\n"); + return -ENOSYS; + } + + return 0; +} + +static int __init scmi_dt_init_smccc(void) +{ + static const struct dt_device_match scmi_ids[] __initconst = + { + /* We only support "arm,scmi-smc" binding for now */ + DT_MATCH_COMPATIBLE("arm,scmi-smc"), + { /* sentinel */ }, + }; + const struct dt_device_node *scmi_node; + const char *smc_id_prop = SCMI_SMC_ID_PROP; + int ret; + + /* If no SCMI firmware node found, fail silently as it's not mandatory */ + scmi_node = dt_find_matching_node(NULL, scmi_ids); + if ( !scmi_node ) + return -EOPNOTSUPP; + + ret = dt_property_read_u32(scmi_node, smc_id_prop, &scmi_smc_id); + if ( !ret ) + { + printk(XENLOG_ERR "SCMI: No valid \"%s\" property in \"%s\" DT node\n", + smc_id_prop, scmi_node->full_name); + return -ENOENT; + } + + scmi_support = true; + + return 0; +} + +/* Initialize the SCMI layer based on SMCs and Device-tree */ +static int __init scmi_init(void) +{ + int ret; + + if ( !acpi_disabled ) + { + printk("SCMI is not supported when using ACPI\n"); + return -EINVAL; + } + + ret = scmi_check_smccc_ver(); + if ( ret ) + goto err; + + ret = scmi_dt_init_smccc(); + if ( ret == -EOPNOTSUPP ) + return ret; + if ( ret ) + goto err; + + printk(XENLOG_INFO "Using SCMI with SMC ID: 0x%x\n", scmi_smc_id); + + return 0; + +err: + printk(XENLOG_ERR "SCMI: Initialization failed (ret = %d)\n", ret); + return ret; +} + +presmp_initcall(scmi_init); + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Mon Sep 30 11:47:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrei Cherechesu X-Patchwork-Id: 13815926 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB4DACF6497 for ; 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Try to handle the SiP SMC first through the `platform_smc()` callback (if implemented). If not handled, check if the SCMI layer is available and that the SMC is a valid SCMI message. Handle it then within the SCMI layer which forwards it to EL3 FW, only if the SMC comes from Dom0. Signed-off-by: Andrei Cherechesu Reviewed-by: Stefano Stabellini Acked-by: Julien Grall --- xen/arch/arm/vsmc.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index 7f2f5eb9ce..0de194a132 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -224,6 +225,22 @@ static bool handle_sssc(struct cpu_user_regs *regs) } } +/* Secure Calls defined by the Silicon Provider (SiP) */ +static bool handle_sip(struct cpu_user_regs *regs) +{ + uint32_t fid = (uint32_t)get_user_reg(regs, 0); + + /* Firstly, let each platform define custom handling for these SMCs */ + if ( platform_smc(regs) ) + return true; + + /* Otherwise, if valid SCMI SMC, forward the call to EL3 */ + if ( scmi_is_enabled() && scmi_is_valid_smc_id(fid) ) + return scmi_handle_smc(regs); + + return false; +} + /* * vsmccc_handle_call() - handle SMC/HVC call according to ARM SMCCC. * returns true if that was valid SMCCC call (even if function number @@ -288,7 +305,7 @@ static bool vsmccc_handle_call(struct cpu_user_regs *regs) handled = handle_sssc(regs); break; case ARM_SMCCC_OWNER_SIP: - handled = platform_smc(regs); + handled = handle_sip(regs); break; case ARM_SMCCC_OWNER_TRUSTED_APP ... ARM_SMCCC_OWNER_TRUSTED_APP_END: case ARM_SMCCC_OWNER_TRUSTED_OS ... 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From: "Andrei Cherechesu (OSS)" To: xen-devel@lists.xenproject.org Cc: andrei.cherechesu@oss.nxp.com, S32@nxp.com, Andrei Cherechesu , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , s32@nxp.com Subject: [PATCH v2 5/8] xen/arm: platforms: Add NXP S32CC platform code Date: Mon, 30 Sep 2024 14:47:11 +0300 Message-ID: <20240930114715.642978-6-andrei.cherechesu@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930114715.642978-1-andrei.cherechesu@oss.nxp.com> References: <20240930114715.642978-1-andrei.cherechesu@oss.nxp.com> X-ClientProxiedBy: AM0PR10CA0016.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:208:17c::26) To PA4PR04MB9565.eurprd04.prod.outlook.com (2603:10a6:102:26b::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PA4PR04MB9565:EE_|AS8PR04MB8357:EE_ X-MS-Office365-Filtering-Correlation-Id: 98730b9b-71fb-4a3c-42ef-08dce145ad66 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|52116014|1800799024|366016|38350700014; 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S32CC platforms use the NXP LINFlexD UART driver for console by default, and rely on Dom0 having access to SCMI services for system-level resources from firmware at EL3. Platform-related quirks will be addressed in following commits. Signed-off-by: Andrei Cherechesu Reviewed-by: Stefano Stabellini --- xen/arch/arm/platforms/Kconfig | 11 +++++++++++ xen/arch/arm/platforms/Makefile | 1 + xen/arch/arm/platforms/s32cc.c | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+) create mode 100644 xen/arch/arm/platforms/s32cc.c diff --git a/xen/arch/arm/platforms/Kconfig b/xen/arch/arm/platforms/Kconfig index 76f7e76b1b..9837cba475 100644 --- a/xen/arch/arm/platforms/Kconfig +++ b/xen/arch/arm/platforms/Kconfig @@ -37,6 +37,14 @@ config MPSOC help Enable all the required drivers for Xilinx Ultrascale+ MPSoC +config S32CC + bool "NXP S32CC platforms support" + depends on ARM_64 + select HAS_LINFLEX + select SCMI_SMC + help + Enable all the required drivers for NXP S32CC platforms + config NO_PLAT bool "No Platforms" help @@ -56,3 +64,6 @@ config MPSOC_PLATFORM bool default (ALL64_PLAT || MPSOC) +config S32CC_PLATFORM + bool + default (ALL64_PLAT || S32CC) diff --git a/xen/arch/arm/platforms/Makefile b/xen/arch/arm/platforms/Makefile index bec6e55d1f..2c304b964d 100644 --- a/xen/arch/arm/platforms/Makefile +++ b/xen/arch/arm/platforms/Makefile @@ -10,5 +10,6 @@ obj-$(CONFIG_ALL64_PLAT) += thunderx.o obj-$(CONFIG_ALL64_PLAT) += xgene-storm.o obj-$(CONFIG_ALL64_PLAT) += brcm-raspberry-pi.o obj-$(CONFIG_ALL64_PLAT) += imx8qm.o +obj-$(CONFIG_S32CC_PLATFORM) += s32cc.o obj-$(CONFIG_MPSOC_PLATFORM) += xilinx-zynqmp.o obj-$(CONFIG_MPSOC_PLATFORM) += xilinx-zynqmp-eemi.o diff --git a/xen/arch/arm/platforms/s32cc.c b/xen/arch/arm/platforms/s32cc.c new file mode 100644 index 0000000000..f99a2d56f6 --- /dev/null +++ b/xen/arch/arm/platforms/s32cc.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * xen/arch/arm/platforms/s32cc.c + * + * NXP S32CC Platform-specific settings + * + * Andrei Cherechesu + * Copyright 2021-2024 NXP + */ + +#include + +static const char * const s32cc_dt_compat[] __initconst = +{ + "nxp,s32g2", + "nxp,s32g3", + "nxp,s32r45", + NULL +}; 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If the SCMI firmware node is not found in Dom0's DT during initialization, it fails silently as it's not mandatory. The SCMI SMCs trapping at EL2 now lets Dom0 perform SCMI ops for interacting with system-level resources almost as if it would be running natively. Signed-off-by: Andrei Cherechesu --- SUPPORT.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/SUPPORT.md b/SUPPORT.md index 23dd7e6424..d8ffddfc44 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -927,6 +927,14 @@ Add/Remove device tree nodes using a device tree overlay binary (.dtbo). Status: Tech Preview +### Arm: SCMI over SMC calls forwarding to EL3 Firmware + +Enable SCMI calls using SMC as doorbell mechanism and Shared Memory for +transport ("arm,scmi-smc" compatible only) to reach EL3 Firmware if issued +by Dom0. Some platforms use SCMI for access to system-level resources. + + Status: Supported + ## Virtual Hardware, QEMU This section describes supported devices available in HVM mode using a From patchwork Mon Sep 30 11:47:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrei Cherechesu X-Patchwork-Id: 13815923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1F2B1CF649C for ; Mon, 30 Sep 2024 11:47:55 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.807258.1218653 (Exim 4.92) (envelope-from ) id 1svEsU-0002Kg-9O; Mon, 30 Sep 2024 11:47:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 807258.1218653; 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Also add the linflex-uart.c driver to the list of other UART drivers in the ARM section. Signed-off-by: Andrei Cherechesu Acked-by: Stefano Stabellini --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fb0ebf0939..2e273a5c78 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -249,6 +249,7 @@ F: xen/drivers/char/arm-uart.c F: xen/drivers/char/cadence-uart.c F: xen/drivers/char/exynos4210-uart.c F: xen/drivers/char/imx-lpuart.c +F: xen/drivers/char/linflex-uart.c F: xen/drivers/char/meson-uart.c F: xen/drivers/char/mvebu-uart.c F: xen/drivers/char/omap-uart.c @@ -428,6 +429,13 @@ L: minios-devel@lists.xenproject.org T: git https://xenbits.xenproject.org/git-http/mini-os.git F: config/MiniOS.mk +NXP S32CC FAMILY SUPPORT +M: Andrei Cherechesu +L: NXP S32 Linux Team +F: xen/arch/arm/include/asm/linflex-uart.h +F: xen/arch/arm/platforms/s32cc.c +F: xen/drivers/char/linflex-uart.c + OCAML TOOLS M: Christian Lindig M: David Scott