From patchwork Tue Oct 1 19:58:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13818696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C52ECEACFB for ; Tue, 1 Oct 2024 19:58:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CB1CA10E66D; Tue, 1 Oct 2024 19:58:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Sc6BYdhU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id E7BD010E66D for ; Tue, 1 Oct 2024 19:58:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1727812689; x=1759348689; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=hQreyJi9B1hMytvtD5+7CProKN0mTqDO3ZGAnBMDKag=; b=Sc6BYdhUV2acgfx8adeAZ7k2pb1GUjujdnzkkg+2gz4HwAOatAe5UCQD kQQ9rBO+HioESrLhEFvuc6XcpKAnFSdVMCFnD68bm3Rh7AnY2utr6psXx 3VFs3vVM0koNWXYA1KA+45X3ukauRosBwFSr/skXmQJ9Zu73JVeiSdIun 6nJm9uTjViEVp0cT4vzKN0vtTLajFyIaB2jWbNzwJDxcbz+KKAHF3vjG8 UcfPW8PbwFghXfZFW4TCDTbI3u2y7paXvjGRR0bDzjdRfDs0tmdwB7AC7 qW+t0MNGicXbCw3zCnfC1Ru+t+jmAaSEtlU0udusEMBYOpfiWsY9i7Vwa w==; X-CSE-ConnectionGUID: 7aw+bz5GSXagTLRjm7n1Ww== X-CSE-MsgGUID: dX7no23PRkqI2iSxEJYVSQ== X-IronPort-AV: E=McAfee;i="6700,10204,11212"; a="26852031" X-IronPort-AV: E=Sophos;i="6.11,169,1725346800"; d="scan'208";a="26852031" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2024 12:58:09 -0700 X-CSE-ConnectionGUID: LFGW5ne7Rrql8SJr4M6mrg== X-CSE-MsgGUID: C3SWl3ZtRQuKfW1SS9pu4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,169,1725346800"; d="scan'208";a="73899353" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 01 Oct 2024 12:58:06 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 01 Oct 2024 22:58:06 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 1/4] drm/i915/irq: Nuke stale comments Date: Tue, 1 Oct 2024 22:58:00 +0300 Message-ID: <20241001195803.3371-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241001195803.3371-1-ville.syrjala@linux.intel.com> References: <20241001195803.3371-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Remove the tall tales about getting passed pipe indices into the .vblank_{enable,disable}() hooks. This hasn't been true since commit 08fa8fd0faa5 ("drm/i915: Switch to per-crtc vblank vfuncs"). Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 8c548ee56c12..0ea1fcc61dde 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -1259,9 +1259,6 @@ void gen11_display_irq_handler(struct drm_i915_private *i915) enable_rpm_wakeref_asserts(&i915->runtime_pm); } -/* Called from drm generic code, passed 'crtc' which - * we use as a pipe index - */ int i8xx_enable_vblank(struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->dev); @@ -1394,9 +1391,6 @@ int bdw_enable_vblank(struct drm_crtc *_crtc) return 0; } -/* Called from drm generic code, passed 'crtc' which - * we use as a pipe index - */ void i8xx_disable_vblank(struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->dev); From patchwork Tue Oct 1 19:58:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13818697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44285CE7D1A for ; Tue, 1 Oct 2024 19:58:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DAF5510E676; Tue, 1 Oct 2024 19:58:12 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Mko1PLUY"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id AB72F10E676 for ; Tue, 1 Oct 2024 19:58:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1727812692; x=1759348692; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=2NclccO89l5xJFaKyu/Jdyzw1RumdLxjqMPzzFHdhaE=; b=Mko1PLUYp0W+pW3zTsVmJ493eq+n4Nhw+RlkleQJoIcEVz4rwrOG1SLL 631R98eqifV5p+QQ/aN4G1ZkTfkaYahi2a6qQh39hqW4Y78r24yzWYQiP 4k1pW0QBJzYAgBedELfltAlR2H6oYB2wYx9r0R+TkfLqJfj46vnhb7nwv 13ebgq3cHtWmlHi/ivpzAkJAY9r9kRiIEBVTSO0tUfMzUKRV19kKkW261 U3Eg5TU7WXts72EymXxMeCuqTZlYKccoWWPR110Cz9qIUgdgm8ccHH3cn ZZhnpMoYAsSvg5hCzJD89RKNokGzpjpxN3o1mcBj6l9ZO/Mo9uywPTMC4 Q==; X-CSE-ConnectionGUID: /0j5cGpgQoSefS7CRDLeWA== X-CSE-MsgGUID: FjC9EnAlQ++i4rHDBkQFgQ== X-IronPort-AV: E=McAfee;i="6700,10204,11212"; a="26852033" X-IronPort-AV: E=Sophos;i="6.11,169,1725346800"; d="scan'208";a="26852033" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2024 12:58:11 -0700 X-CSE-ConnectionGUID: 3NMn84QCRpOYQIT0n0lubg== X-CSE-MsgGUID: vqoi8FFsS4SlSn11jfllhQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,169,1725346800"; d="scan'208";a="73899362" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 01 Oct 2024 12:58:09 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 01 Oct 2024 22:58:09 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 2/4] drm/i915/irq: Pair up the vblank enable/disable functions Date: Tue, 1 Oct 2024 22:58:01 +0300 Message-ID: <20241001195803.3371-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241001195803.3371-1-ville.syrjala@linux.intel.com> References: <20241001195803.3371-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The current way of organizing all .vblank_enable() functions before all .vblabk_disable() functions is infuriating. It's really hard to compare the enable() vs. disable() for the same platform to make sure they properly mirror each other. Reorganize the functions so that the enable+disable for the same platoform are next to each. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- .../gpu/drm/i915/display/intel_display_irq.c | 92 +++++++++---------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 0ea1fcc61dde..43a0b3565bc8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -1272,6 +1272,17 @@ int i8xx_enable_vblank(struct drm_crtc *crtc) return 0; } +void i8xx_disable_vblank(struct drm_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->dev); + enum pipe pipe = to_intel_crtc(crtc)->pipe; + unsigned long irqflags; + + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); +} + int i915gm_enable_vblank(struct drm_crtc *crtc) { struct drm_i915_private *i915 = to_i915(crtc->dev); @@ -1288,6 +1299,16 @@ int i915gm_enable_vblank(struct drm_crtc *crtc) return i8xx_enable_vblank(crtc); } +void i915gm_disable_vblank(struct drm_crtc *crtc) +{ + struct drm_i915_private *i915 = to_i915(crtc->dev); + + i8xx_disable_vblank(crtc); + + if (--i915->display.irq.vblank_enabled == 0) + intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); +} + int i965_enable_vblank(struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->dev); @@ -1302,6 +1323,18 @@ int i965_enable_vblank(struct drm_crtc *crtc) return 0; } +void i965_disable_vblank(struct drm_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->dev); + enum pipe pipe = to_intel_crtc(crtc)->pipe; + unsigned long irqflags; + + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + i915_disable_pipestat(dev_priv, pipe, + PIPE_START_VBLANK_INTERRUPT_STATUS); + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); +} + int ilk_enable_vblank(struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->dev); @@ -1323,6 +1356,19 @@ int ilk_enable_vblank(struct drm_crtc *crtc) return 0; } +void ilk_disable_vblank(struct drm_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->dev); + enum pipe pipe = to_intel_crtc(crtc)->pipe; + unsigned long irqflags; + u32 bit = DISPLAY_VER(dev_priv) >= 7 ? + DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); + + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + ilk_disable_display_irq(dev_priv, bit); + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); +} + static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc, bool enable) { @@ -1391,52 +1437,6 @@ int bdw_enable_vblank(struct drm_crtc *_crtc) return 0; } -void i8xx_disable_vblank(struct drm_crtc *crtc) -{ - struct drm_i915_private *dev_priv = to_i915(crtc->dev); - enum pipe pipe = to_intel_crtc(crtc)->pipe; - unsigned long irqflags; - - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); - i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); -} - -void i915gm_disable_vblank(struct drm_crtc *crtc) -{ - struct drm_i915_private *i915 = to_i915(crtc->dev); - - i8xx_disable_vblank(crtc); - - if (--i915->display.irq.vblank_enabled == 0) - intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); -} - -void i965_disable_vblank(struct drm_crtc *crtc) -{ - struct drm_i915_private *dev_priv = to_i915(crtc->dev); - enum pipe pipe = to_intel_crtc(crtc)->pipe; - unsigned long irqflags; - - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); - i915_disable_pipestat(dev_priv, pipe, - PIPE_START_VBLANK_INTERRUPT_STATUS); - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); -} - -void ilk_disable_vblank(struct drm_crtc *crtc) -{ - struct drm_i915_private *dev_priv = to_i915(crtc->dev); - enum pipe pipe = to_intel_crtc(crtc)->pipe; - unsigned long irqflags; - u32 bit = DISPLAY_VER(dev_priv) >= 7 ? - DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); - - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); - ilk_disable_display_irq(dev_priv, bit); - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); -} - void bdw_disable_vblank(struct drm_crtc *_crtc) { struct intel_crtc *crtc = to_intel_crtc(_crtc); From patchwork Tue Oct 1 19:58:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13818698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A70FCEACFF for ; Tue, 1 Oct 2024 19:58:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D910310E67A; Tue, 1 Oct 2024 19:58:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="eSaIbDr5"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6F6AB10E67A for ; Tue, 1 Oct 2024 19:58:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1727812694; x=1759348694; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=JQ3efqQO0k6i4EOrDS/1PUF9UiStPZxE4Z5gEty9b38=; b=eSaIbDr5AWNLlyt0y3SMHvAbB/KFuo0sZd/QaRxznPEirbV3o+TWD4Mg SVPFEm05DTfvE545cXyZiV0KvaNGb4tnurE4mIi8fXZ51AELoAinsYqsf YbjmwqxnGbEx+boQ5bGXPVKiGZeejhAmkhkvA9w+XCRkoQ4wpZJsIQIow iLkfh9KKVl2uXUaPWKTQuqGf8rkAWgvkLuIWXzXClbh8HxS1kU3VzvFgP xUCXUlkB0xlJBpEoR/XBbZq5ABUx4ie5U9PkA1+/Rc+8SPEwJxduijE0q wjmlM5JGTXohGEbifAkDdip3YYg4BZWkXwYzNQ9208O8R9ANVX9iam/Ye Q==; X-CSE-ConnectionGUID: OI2DCik8Smu+8qtdBRc95A== X-CSE-MsgGUID: 0YSxw6eaQhCBuwIUa2oCEw== X-IronPort-AV: E=McAfee;i="6700,10204,11212"; a="26852040" X-IronPort-AV: E=Sophos;i="6.11,169,1725346800"; d="scan'208";a="26852040" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2024 12:58:14 -0700 X-CSE-ConnectionGUID: sJAKcba+Qjyf9eZVkOHPUw== X-CSE-MsgGUID: whZV4c7TSyOiaDRtANiVIQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,169,1725346800"; d="scan'208";a="73899368" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 01 Oct 2024 12:58:12 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 01 Oct 2024 22:58:11 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 3/4] drm/i915: Extract i915gm_irq_cstate_wa_{disable, enable}() Date: Tue, 1 Oct 2024 22:58:02 +0300 Message-ID: <20241001195803.3371-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241001195803.3371-1-ville.syrjala@linux.intel.com> References: <20241001195803.3371-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Extract the i915gm/i945gm vblank irq C-state workaround to separate functions. We'll need to reuse these in order to guarantee timely CRC interrupt delivery as well. The irq.vblank_enabled count is currently protected by the drm vblanl locks, so let's assert that the innermost of those is held, in anticipation of other callers. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- .../gpu/drm/i915/display/intel_display_irq.c | 34 +++++++++++++------ 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 43a0b3565bc8..feeb3a29972a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -1259,6 +1259,28 @@ void gen11_display_irq_handler(struct drm_i915_private *i915) enable_rpm_wakeref_asserts(&i915->runtime_pm); } +static void i915gm_irq_cstate_wa_enable(struct drm_i915_private *i915) +{ + lockdep_assert_held(&i915->drm.vblank_time_lock); + + /* + * Vblank interrupts fail to wake the device up from C2+. + * Disabling render clock gating during C-states avoids + * the problem. There is a small power cost so we do this + * only when vblank interrupts are actually enabled. + */ + if (i915->display.irq.vblank_enabled++ == 0) + intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); +} + +static void i915gm_irq_cstate_wa_disable(struct drm_i915_private *i915) +{ + lockdep_assert_held(&i915->drm.vblank_time_lock); + + if (--i915->display.irq.vblank_enabled == 0) + intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); +} + int i8xx_enable_vblank(struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->dev); @@ -1287,14 +1309,7 @@ int i915gm_enable_vblank(struct drm_crtc *crtc) { struct drm_i915_private *i915 = to_i915(crtc->dev); - /* - * Vblank interrupts fail to wake the device up from C2+. - * Disabling render clock gating during C-states avoids - * the problem. There is a small power cost so we do this - * only when vblank interrupts are actually enabled. - */ - if (i915->display.irq.vblank_enabled++ == 0) - intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); + i915gm_irq_cstate_wa_enable(i915); return i8xx_enable_vblank(crtc); } @@ -1305,8 +1320,7 @@ void i915gm_disable_vblank(struct drm_crtc *crtc) i8xx_disable_vblank(crtc); - if (--i915->display.irq.vblank_enabled == 0) - intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); + i915gm_irq_cstate_wa_disable(i915); } int i965_enable_vblank(struct drm_crtc *crtc) From patchwork Tue Oct 1 19:58:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13818699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B370CEACFF for ; Tue, 1 Oct 2024 19:58:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E41B210E67B; Tue, 1 Oct 2024 19:58:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Q/V0+8X1"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 45F0110E67B for ; Tue, 1 Oct 2024 19:58:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1727812697; x=1759348697; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=2Z/zXi3X/u4dsBDtQhfTK2Z82hzMr/RsuNeGYbPpo0g=; b=Q/V0+8X1AKITonwhWPe5hMl7Fpj3xXGw17PIdMc/frgiHiAQPpxB+k9U U+61VRXNmk4V/O1J6gqFHGv1kmvBST5BxG/TcU17HJA2DRjg+BATWgaKN Sql5fLaTD72LNA/unj4y7pym4H3Q3HAR6lpGCfs3eVArRimRd+Fn8Ck5U JJo6aGfDnZIscmNrHKTjpJS7ABpCpFIalP6hAD6MuQ0DZKEbfda7037+I Ai1+qqplUa21iS6pH6G4FAoAFdK8uzT2ak7O5Q1cTaoc8iPa9BIMuxZmn UdppuWyja1YG0zeBCbrT1X7Px40O4XAhz9aEBLjJ1bFeO2SaZd+WwL1LZ w==; X-CSE-ConnectionGUID: A0eDNd+wQUykNbeXazzjXg== X-CSE-MsgGUID: QccR7cm/S7y3kxcJHrhQEA== X-IronPort-AV: E=McAfee;i="6700,10204,11212"; a="26852043" X-IronPort-AV: E=Sophos;i="6.11,169,1725346800"; d="scan'208";a="26852043" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Oct 2024 12:58:17 -0700 X-CSE-ConnectionGUID: 7Juupkv2SwCCAmhAn2XhDw== X-CSE-MsgGUID: hqIJMOcSS0alvQgzO03R3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,169,1725346800"; d="scan'208";a="73899377" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 01 Oct 2024 12:58:15 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 01 Oct 2024 22:58:14 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 4/4] drm/i915: Apply the i915gm/i945gm irq C-state w/a to CRC interrupts Date: Tue, 1 Oct 2024 22:58:03 +0300 Message-ID: <20241001195803.3371-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241001195803.3371-1-ville.syrjala@linux.intel.com> References: <20241001195803.3371-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Turns out CRC interrupts also fail to wake up i915gm/i945gm from C2+. I suppose this is a generic problem, but for most other interrupts the system will be busy enough already prior to the irq being issued. But CRC interrupts are like vblank interrupts and only fire once per frame, so plenty of time to fall asleep in between them. Apply the same core clock gating trick to CRC interrupts that we use for vblank interrupts. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 14 +++++++++++++- drivers/gpu/drm/i915/display/intel_display_irq.h | 2 ++ drivers/gpu/drm/i915/display/intel_pipe_crc.c | 4 ++++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index feeb3a29972a..fa5a42fc8501 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -1264,7 +1264,7 @@ static void i915gm_irq_cstate_wa_enable(struct drm_i915_private *i915) lockdep_assert_held(&i915->drm.vblank_time_lock); /* - * Vblank interrupts fail to wake the device up from C2+. + * Vblank/CRC interrupts fail to wake the device up from C2+. * Disabling render clock gating during C-states avoids * the problem. There is a small power cost so we do this * only when vblank interrupts are actually enabled. @@ -1281,6 +1281,18 @@ static void i915gm_irq_cstate_wa_disable(struct drm_i915_private *i915) intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); } +void i915gm_irq_cstate_wa(struct drm_i915_private *i915, bool enable) +{ + spin_lock_irq(&i915->drm.vblank_time_lock); + + if (enable) + i915gm_irq_cstate_wa_enable(i915); + else + i915gm_irq_cstate_wa_disable(i915); + + spin_unlock_irq(&i915->drm.vblank_time_lock); +} + int i8xx_enable_vblank(struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->dev); diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h index bf9d269d0e3f..4b493cff7b8e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.h +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h @@ -78,4 +78,6 @@ void valleyview_pipestat_irq_handler(struct drm_i915_private *i915, u32 pipe_sta void intel_display_irq_init(struct drm_i915_private *i915); +void i915gm_irq_cstate_wa(struct drm_i915_private *i915, bool enable); + #endif /* __INTEL_DISPLAY_IRQ_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c index 82ceede0b2b1..304da826dee1 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c @@ -32,6 +32,7 @@ #include "i915_reg.h" #include "intel_atomic.h" #include "intel_de.h" +#include "intel_display_irq.h" #include "intel_display_types.h" #include "intel_pipe_crc.h" #include "intel_pipe_crc_regs.h" @@ -285,6 +286,9 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable) struct drm_modeset_acquire_ctx ctx; int ret; + if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv)) + i915gm_irq_cstate_wa(dev_priv, enable); + drm_modeset_acquire_init(&ctx, 0); state = drm_atomic_state_alloc(&dev_priv->drm);