From patchwork Thu Oct 3 08:14:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13820768 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2517137923 for ; Thu, 3 Oct 2024 08:14:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727943276; cv=none; b=ROV1kR8+G5FBrnA5THJsu48FB27Gd8m5Z+t+A9EtSllHaOsdk6krZzbR4knTTSTz8EbStOkQUy4AOt4XHPi/I4x2ZUCDjMSKAHH/F2mbY3QTDlhsutubmAXTb2S23e71m2Pw7VPELpt/MeG3Obw5q6BzL4wGxUec7SUdLcMsIrE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727943276; c=relaxed/simple; bh=I5gkxxh+/Kn7rSd5JE9ZVp0kaBODXFkfmbSKaf1DYHc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Dxl005bugOrzKTb2skyoZutiLFSP4pyDorGZcRgVCqWM8Rk+Yjt0vPe8VlxQTtfyeDFZrSe+Ajm5+VgJv6WTmKoFr+EHQtnx0sWQXKKALnmhwWQQh7oZSiKPgcPn2wQjzyrEycukfrcTwgT2C5+Gl48AY1Q80vXLldzJdmA+ZxU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=QFLInN7m; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="QFLInN7m" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-42f7e1fcb8dso1007055e9.2 for ; Thu, 03 Oct 2024 01:14:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727943272; x=1728548072; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=UHrfObhoXZxOjnZcmfI2vEOVJIbBll+cRB8dRqaKEJs=; b=QFLInN7mDPxZ76Y+DBfNKyYAwLcqBTwBfTF0ESMF/3HEzU6TFDo+PRi+u1RcGJ3oOD dXBNFPwT860Q4yskSJ2RsjMqpGEoElAb/cDgTDjJ6wyvveU2g2VMeH/y1HT8bg1OZPTy 8ZiG+IeEDAIUDHKS+Il9T2b/DUOP78vmxmcAPv/7zu2PVaiz3aCllkMIHAf0J/JVht55 1aKXgTQfCaJjPhID2q2qCAbR0oozS9dHUbsG/9MTnoZ2U89wmtWVE7nrvj5ILILcR1zB 5mFfWxbgDelegfrkXoWjeYaLxZ3SAPzPli0pEiB4ExwCjUM99TfQHUPXA248fmV0CX6J RHsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727943272; x=1728548072; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UHrfObhoXZxOjnZcmfI2vEOVJIbBll+cRB8dRqaKEJs=; b=XcHOcryUAgvVyqJGGQz1dSx87gIfmO3BId9zroS6RrljpUXaJXCatEZNWhP7ngpL4c m1f1PEV9rahtSJEBN8EGds4lNzR27zS87vCHtbI/9kONDQo6qmUsNihYzLOz1uiJOMcs /tjGp86Vtf8OU2c76Ca2udb2obYucUhXNKF8BY02iIzLidA14UCLBw+7gHPQF1zbGruZ r859EjplNFocoAcalTSJPlG8zOPC5uNdwJYv3TAorAAAYztnZgKSgRCAEqSgboCfV6T7 q3nq/0oEbtF64hBbgEK0I4eVPlBS6q52iy0WF5qHiZV5OdT0RzMer8Wpos7GKoAbFKwt ZBIQ== X-Gm-Message-State: AOJu0YwgnhsMZKATco0+nLQ5FkTIdYB5qXXmxJ5F4Wj0biCSon8Vb4sO PBUBEQaubD08dJFp/qNjBwY41sqUKzx1/GgibFw+WpHDkG/iAiZnGTD/tiqzXUE= X-Google-Smtp-Source: AGHT+IHMjRyVUMPEi+gSZ/24bRWlnva5QunmQXCmdsDcU6Mhxs+a79NfsNMAh1FZ1Yq85tIJ65W/ig== X-Received: by 2002:a05:6000:1ac6:b0:374:c962:a18a with SMTP id ffacd0b85a97d-37cfb8d068fmr2143166f8f.4.1727943271910; Thu, 03 Oct 2024 01:14:31 -0700 (PDT) Received: from [127.0.1.1] ([178.197.211.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d082d230dsm702027f8f.94.2024.10.03.01.14.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 01:14:31 -0700 (PDT) From: Krzysztof Kozlowski Date: Thu, 03 Oct 2024 10:14:18 +0200 Subject: [PATCH 1/5] dt-bindings: display/msm: merge SC8280XP DPU into SC7280 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241003-dt-binding-display-msm-merge-v1-1-91ab08fc76a2@linaro.org> References: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> In-Reply-To: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Neil Armstrong , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=5123; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=I5gkxxh+/Kn7rSd5JE9ZVp0kaBODXFkfmbSKaf1DYHc=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBm/lJgpCz5PczWvVC4MOIIKhlQ6KLXaZenlrYJI drKKpzFNpOJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZv5SYAAKCRDBN2bmhouD 10fcD/4547yeLqXfKNqq/CjO1tHYFMiWiDA6JArchwq/G4NWZyVC+Xq8hEdf7u3a7ycQb0rs3cL 0huBzw5X9Ufag9yLBEM3iS8noXXPgJuWSh/WqX8DTWpOvg1E3Bu8+w55lf/zy8GuUqGF4h1o7W0 qOmxHVECt5X4Ny+VxP5b6kxsezf4wUbVipwfW45ykmdqijK6D2qgrfF2CZMB+/aOZkVnUdavGtJ gjMIYp5Pf/r9uGsCitHgUB0rULcJEippVF59cFhZdGD9ESFbSuuyS/CdaFmO9bmN3mPq/7UpD+i kA8s7BwUumRlLjkhjAnSfC1+sg6vJln4nvp84XpySm80dTf6rRC8D3zfBlk2leVrq+eKr/4r8bF 7x/I6rPiTHgPRHpsiwiVyR9BpzxnmvjQeCjlCHlGxW3Db+O3bbP6xvezxKYnHd6DTWm9ydIlNrU UpONUCnuUvGy/SGhA6la9MlpRTcPlVCywjDAWVXW+U9ninUzNQqctGNSigCb9sgcp/oQEhgdrbG XShEwlMGR1T1Co9HkghLDyQVMIqNGSc7htte0RjHVWqQadeLFyE/O+o2yA98PTrhN/PKR0A8Zj3 DNK0MrBAfS0fTQlkz0RNU2LrYSvNF51+fkpAQexMN5NMDH6zif5WdABJIKysAlQllhnMYh/63wo KmkfVBAKxFOlbzA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Split of the bindings was artificial and not helping - we end up with multiple binding files for very similar devices thus increasing the chances of using different order of reg and clocks entries. Unify DPU bindings of SC7280 and SC8280XP, because they are the same. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) --- .../bindings/display/msm/qcom,sc7280-dpu.yaml | 5 +- .../bindings/display/msm/qcom,sc8280xp-dpu.yaml | 122 --------------------- 2 files changed, 4 insertions(+), 123 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index b0fbe86219d1..fab7a3b9a20e 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -7,13 +7,16 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Display DPU on SC7280 maintainers: + - Bjorn Andersson - Krishna Manikandan $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - const: qcom,sc7280-dpu + enum: + - qcom,sc7280-dpu + - qcom,sc8280xp-dpu reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml deleted file mode 100644 index d19e3bec4600..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml +++ /dev/null @@ -1,122 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SC8280XP Display Processing Unit - -maintainers: - - Bjorn Andersson - -description: - Device tree bindings for SC8280XP Display Processing Unit. - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sc8280xp-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi clock - - description: Display sf axi clock - - description: Display ahb clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include - #include - #include - - display-controller@ae01000 { - compatible = "qcom,sc8280xp-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc0 DISP_CC_MDSS_AHB_CLK>, - <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc0 DISP_CC_MDSS_MDP_CLK>, - <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>, - <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <460000000>, - <19200000>; - - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SC8280XP_MMCX>; - - interrupt-parent = <&mdss0>; - interrupts = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - endpoint { - remote-endpoint = <&mdss0_dp0_in>; - }; - }; - - port@4 { - reg = <4>; - endpoint { - remote-endpoint = <&mdss0_dp1_in>; - }; - }; - - port@5 { - reg = <5>; - endpoint { - remote-endpoint = <&mdss0_dp3_in>; - }; - }; - - port@6 { - reg = <6>; - endpoint { - remote-endpoint = <&mdss0_dp2_in>; - }; - }; - }; - }; -... From patchwork Thu Oct 3 08:14:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13820769 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D71E84FAD for ; Thu, 3 Oct 2024 08:14:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727943277; cv=none; b=OievfJdzNOfj3k5cPNeXVEvrr1dCTfzWLLWxqLZJpuRTf9Qsq6jwEITK7INJ9DaPau+p5GnP3EfBAyWfndS44UkdCki0Va6KZd01wOo0wtPvcipV1fYcAthD9kA5S2Al89ogLywdUhH2oubJZWGydgU2LDiEy1f2IDnO6ugHYY0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727943277; c=relaxed/simple; bh=dH+SVdLskeQZiYIROK71JDfiS/rRfhCzgnVtQVskFbE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XXHLaPlgZT8UYLsqBubQRANgs1jo2PjptcAh0a6vymRhHYUIXXWij1KnCaEvfwxXc85KT2TIwxKnijA7BaHKLY2yNHgv0Rg24ZITUea1rErX63k41AhDaeG64A5uUc2fZz5MHYJOtgcecW4+ZHncfLfLyRVd1/bJiNc4FEKT/1A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=hpzjq4dc; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hpzjq4dc" Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-37cd2cb5615so48898f8f.2 for ; Thu, 03 Oct 2024 01:14:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727943274; x=1728548074; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=eXlZz7rmb9UIZ/1Ho16Xy2pZAX3UIBne7+DPquCei2E=; b=hpzjq4dchmGRnmYdG/oBveNlKJCGnsvCd2Q4B5fn1N+0nd6bEm+/QKbmQjPCHL6Ybr 7L8SRE01YbVOeR3FmNDkXWsYt7i0XXuYvCMqfe2Gt4ApvcGRBsobaOeRH7GCLLa17g+C 84I77gztozBFCLBO7AL3jCMQGGeZyqLX2DT10GUUz1Y7Ko55Et16Zfnm1eYFBvP2HHcA YnA+ZubDzhx513Jo19g7AZ8f82OG36q+2ZXfPMmK5zXj3QffI+0/s/eM7fXoSvoTeucp apVEipA3TBhmoCGCSfk4Nj7QY79OK85RIH2lMbPoKDPVpeZ1AKbn9rR8dmt/B00EaJYX cQ5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727943274; x=1728548074; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eXlZz7rmb9UIZ/1Ho16Xy2pZAX3UIBne7+DPquCei2E=; b=PGucq4RYO0UrJf7RoKPeCa5z3QgFJdzDgJLxUDN3Lh0x7qS1dmdMhxHNaH1zWiko/V IxQ+sfNjPoRzWGMRpixYMUIja7LY+aRZFPcBk2+SF2hfvO6gGPGXm34pkRbvgwoMw3xi bdtjI4vP8+oID6o/cAaXGMWQF88D9s+iaSoZBHBiktbajxdXqxhVWHez7RHZJkr03PT7 Mjjr4Ag00yF7BSup2lJCx3X9JNmXs81YSNDXSkr3cZhueb5e0zz1FYXtvHAfSqtZbja3 xcWv0j+T8uphpqN8snP8cCeHP2585A3EOafPbRGi4rtfbqI65C36nC24qyIFm6YXHpKr s8Ig== X-Gm-Message-State: AOJu0YyCRB/WFo+oYiNi5Hi8eBd3FHAqWO0T8ReuVWiIfNjrpJ6QuZob wlCGnZH6cQ9rWpHR7dAglWcLf8Ptz4jZe7I3nOZKkN3tkeCrTCW9c/GSc7RlPmRi3WeZqrfWZdb J X-Google-Smtp-Source: AGHT+IHORvrlXJ4uwjpyybGVAb6MaxVx88Mqx74c5eN9Gw4NoGknhvyMYnh6Ke8vQdMc9xQqHr1VSg== X-Received: by 2002:a5d:59a8:0:b0:375:bb30:6518 with SMTP id ffacd0b85a97d-37cfb8b6238mr1902193f8f.1.1727943273759; Thu, 03 Oct 2024 01:14:33 -0700 (PDT) Received: from [127.0.1.1] ([178.197.211.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d082d230dsm702027f8f.94.2024.10.03.01.14.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 01:14:33 -0700 (PDT) From: Krzysztof Kozlowski Date: Thu, 03 Oct 2024 10:14:19 +0200 Subject: [PATCH 2/5] dt-bindings: display/msm: merge SM8250 DPU into SM8150 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241003-dt-binding-display-msm-merge-v1-2-91ab08fc76a2@linaro.org> References: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> In-Reply-To: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Neil Armstrong , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4033; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=dH+SVdLskeQZiYIROK71JDfiS/rRfhCzgnVtQVskFbE=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBm/lJg0f/7YyApnEY8pSbuulkztqOe3u+5CTTNw NTupL6zl1uJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZv5SYAAKCRDBN2bmhouD 11hbD/415N1kKo/l9YBKsL0cydlNj3GtPjC2ZZfex3cZjVPKMyQW9dXJJ1WhWI5dIVUToYmeSVp ZTfm3jqW+96yurBGDecwRoJ8/B/Zwim1uWApF4WygfyZKEAOgesBtb8FYMJ1hSbPUaZVNcSZKzJ Iyb482ktA9vGrGkHlyInPWds7pr7vw/JIDUuU/I8xNRd+3KJBl0N+KhcHFN6WxGl/+8FEqkKC7S Qyjee5Py3vzAt7GlaP2MAFz9ut68mmHZpYxkeGnUl0ZiWMESRIOYDZeoqVuuLex/YQkj/UVzgOm ngrcfQMqJEg6Q/zzf9pybylBtVvJuEBWrnC9nJ7vSsDB6v8+L2b0LT2O8X5W+ZSRpdmP9DyUvbw nT9vtIjahfdCxic8tyAuEW7TuoTDM68syCRVwjy2y3RHCCtuQlFQOhKp9bH/BiEe7fFKFnoq5EC yScWAgoh8GRtGDMa7WrsvG6ECThhiRPfdpZR7KwhA0y0KPysZa86F5lFLOqwxkZcje6dCj9yXJW L0JrbOEfSO5oMwrKSNMoUHzt0MZAt0QELr7iK6oNTsbKXNSB8UJa5x6NAfcNqCMpPaoDjKDvgUw HIn1cBl+3Ua37RFoakIXN2ASKUT4/YpkLLV749XHhZIqcU7r/MvlvSIHxvaspMGiqw3JirEbGIv tgLUfaTwPxLZ4hg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Split of the bindings was artificial and not helping - we end up with multiple binding files for very similar devices thus increasing the chances of using different order of reg and clocks entries. Unify DPU bindings of SM8150 and SM8250, because they are the same. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) --- .../bindings/display/msm/qcom,sm8150-dpu.yaml | 4 +- .../bindings/display/msm/qcom,sm8250-dpu.yaml | 99 ---------------------- 2 files changed, 3 insertions(+), 100 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml index 13146b3f053c..a88d22f30a60 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml @@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - const: qcom,sm8150-dpu + enum: + - qcom,sm8150-dpu + - qcom,sm8250-dpu reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml deleted file mode 100644 index ffa5047e901f..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml +++ /dev/null @@ -1,99 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SM8250 Display DPU - -maintainers: - - Dmitry Baryshkov - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sm8250-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display ahb clock - - description: Display hf axi clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: iface - - const: bus - - const: core - - const: vsync - -required: - - compatible - - reg - - reg-names - - clocks - - clock-names - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include - #include - #include - - display-controller@ae01000 { - compatible = "qcom,sm8250-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "iface", "bus", "core", "vsync"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <19200000>; - - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - }; -... From patchwork Thu Oct 3 08:14:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13820770 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69A2A14036E for ; Thu, 3 Oct 2024 08:14:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727943279; cv=none; b=saeukuQyg+aF1VCQRD+mwt0TiNDZIJu3A5qCd4TPlF6Ob/H0uUrZHG1UBXfld4G1Sm7WwI0CWmXwwqa9vbtzs4ssZehYdMMg/tLWA+mCvBOQyIXyqisjNmOfzLEZWbg7qaR1gFY8pQaCq7YPI9Ngw7PiO5Xxlk90TRmlj7gwRuw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727943279; c=relaxed/simple; bh=M70OZAtivNRGOLcaQJi4OpyfB+gup8mxOQUxCSAPC3I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QDYADNvYTW0NOuLqIiiSrOc+vWcygQbQY9GJSSz7MQeiv4+lXaTKY+PF38eyAqgSQ3lKZD/lJV3M2tBw2ycKTihigrnRUbHKl8Qtt+wSYLizBIV3RmRBGruU4fhuVT0p3xIHBCRs1GpdBxQBzu1eXcEL97UW3ZB8CxW6mBoXUsg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Q4/koONN; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Q4/koONN" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-42f7e1fcb8dso1007265e9.2 for ; Thu, 03 Oct 2024 01:14:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727943276; x=1728548076; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=yjGjFpVi6DoXujtHm3muxy156XMe7cgV5oZmQeg5Uh4=; b=Q4/koONNiiCEM9dAiFds4jIOkCQ//cjqQFhBYcahsvN6IObCE5AjTJ6HmM+dSFSisE H8aNFWuNLrB/cB3ykW/tqDM19WfA7XhEbPiFg1du/sN20JpHUBL2vEYCk3tegt5ezN6z 3dh4nfAp7YDdmRP142yMTplD6Q+FZDePgZTUu7jqyOvU7jGmoq1VDUOhoKClwqkQGWCe ZVTINs9K2BT87avZ47mE/4rT3sOHtk1W77t0kk7fXRmLGt4tBjuOPaZ6NkSJVmQPhQNV L/UMqw5CToV8a+4YAxXMdI3AwrRv1QcCvYW8Tb1xweaq/MjvjR8WZcI2rpyr/4Rp40Cq 15eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727943276; x=1728548076; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yjGjFpVi6DoXujtHm3muxy156XMe7cgV5oZmQeg5Uh4=; b=malQ3iD3fqkexMdbVwbsjwk2PA7T2eYOMAFLO0zm9GYIaS9r0t0F0mG95Rbgo0TUy3 lA5fgNQa7w9lxLwmzCLm558hQiZVR0O0GRTZtpClOEb3IlnJ4S92d1P749KW8I6A9Ry9 hHSBKj+i6PFydaNowa0JmPzeAzzXP2LrdJatVGpO5v0QycWivJi3w57nghdd2dLSEIf7 z5d5QWAHihOCKL6d1zXZVZUIO2mpGlYoNoXq0t/7kL0eOouamJILKjJvUvUzT9CTH6so x6ZrWJbGCflTkgR0ze34pUW9BimuJxm3lG+JlO7+HhPgsYgAuSQbJmEyK36IETCF4xZW uEjw== X-Gm-Message-State: AOJu0YzNhwFCO4eLbmPBnM2rt9OVJAWSl3jDcY09TKRoGi16k1LnL6se DWTepRbSPAe3rTNEdKn7+XwO4VT2XtTQKCDJPPS0fimvDuhZpKbKGFMjg+lsQIY= X-Google-Smtp-Source: AGHT+IHNfyTynFWJjVKHkFdbF55NsYmFJ72O5u3SCiEQBvJwWPSRzqEazUj7I33c8ZpWwWaIFNc7vQ== X-Received: by 2002:a05:600c:74a:b0:42c:aeee:e604 with SMTP id 5b1f17b1804b1-42f7795431cmr21343885e9.8.1727943275636; Thu, 03 Oct 2024 01:14:35 -0700 (PDT) Received: from [127.0.1.1] ([178.197.211.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d082d230dsm702027f8f.94.2024.10.03.01.14.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 01:14:35 -0700 (PDT) From: Krzysztof Kozlowski Date: Thu, 03 Oct 2024 10:14:20 +0200 Subject: [PATCH 3/5] dt-bindings: display/msm: merge SM8350 DPU into SC7280 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241003-dt-binding-display-msm-merge-v1-3-91ab08fc76a2@linaro.org> References: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> In-Reply-To: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Neil Armstrong , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4802; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=M70OZAtivNRGOLcaQJi4OpyfB+gup8mxOQUxCSAPC3I=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBm/lJhOPfdZ5V1aYsZIliza2UvaapHm8tgeUCrw olfeMvDH1qJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZv5SYQAKCRDBN2bmhouD 18DeEACG12eR34P9hg1YN3zIF9k5PLLvau56aXFJnH9mm5fk6+FQcDOphwIqZo6K7LJpBGMYCdq /952tDwVpCfoegkyc9mCXLl5K4YNM+MdpdqF430dOaYnmvN2XcCGy+1pxU7EbFB0Q1ke1UofYhV hRYe+1PhZ7kJwKUX99uN+r1NhIIoZ+wwO3KgS+I0fMSsgpCknJ4SI6T9ztvCDd4e1T5CwS4GzdQ Dhw2TjTKvk9pHKMwE0avmYZWIva7YsO7do/bVJvSmbR6F7DEvT53O6rforR0Tuzd7WAGhV095eT v5CgBQegilINyggMwZWWRzL/JTcY/O4fU84k0kywgc/wm2/CkeYOD9ZbqHnFp7/lqgvhjdlRRbu UcUA3FFdlzZd2KkABBwfYeeXotA0cARexYYVOQ0NMYWfkaHR+fnkBp2KWCpzqogzbLIXQetopGX GXdSEHumIM5hVna/wAjh5mV+PH1WzIWGaeODimGNt2d5EJ1cV4KMq1/dKam13yaCHbPwi+76wwo KTUk2bQzqA/xOpXb/lOUiP7nc1Vh6ahSqb+RvmO5ZpfL+cXVmZKnI0YVixDURlStmwh4ThjwprW 8KtdH47jcqHqjosUBR0Cqrw+1ZL/ndaoTW254d3CtefHenxJla9+zt2ivWC9Uu/33V2XPT3aZtI c0VZ2PozLhr9FXw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Split of the bindings was artificial and not helping - we end up with multiple binding files for very similar devices thus increasing the chances of using different order of reg and clocks entries. Unify DPU bindings of SC7280 and SM8350, because they are the same. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) --- .../bindings/display/msm/qcom,sc7280-dpu.yaml | 1 + .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 --------------------- 2 files changed, 1 insertion(+), 120 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index fab7a3b9a20e..3d69a573b450 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -17,6 +17,7 @@ properties: enum: - qcom,sc7280-dpu - qcom,sc8280xp-dpu + - qcom,sm8350-dpu reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml deleted file mode 100644 index 96ef2d9c3512..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml +++ /dev/null @@ -1,120 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SM8350 Display DPU - -maintainers: - - Robert Foss - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sm8350-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi clock - - description: Display sf axi clock - - description: Display ahb clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include - #include - #include - - display-controller@ae01000 { - compatible = "qcom,sm8350-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <19200000>; - - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; - - mdp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-345000000 { - opp-hz = /bits/ 64 <345000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-460000000 { - opp-hz = /bits/ 64 <460000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; -... From patchwork Thu Oct 3 08:14:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13820771 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33B0614601C for ; Thu, 3 Oct 2024 08:14:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727943281; cv=none; b=T/rVMl7Zsmmdl/xHEDbkj32LOnExrcV8u/qULEvK1txLVloA8s+U33K/W3Nh+SnAziOT1rDptoU6Vi6S7ciETkDVCgSt5D95NCCq8mmDLvEEc67WxGOulEcbOZmJs009BT8duZIfLvgfrjsbEJZxsiPFP5PNPxbUwy1NdsD/dhY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727943281; c=relaxed/simple; bh=AKhgP7q0GaIQSUQKoHkiCv6d3dwP2bPLVjVUtecZON0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UhaYwjBIYEx5TNri+0CZeWwUBcIWmtVoSUdzfFI3YPmiwYgrFEOSU2a9jDrCqRKYSNoSctbVtdUWh8FBsF33bQSXX7zRmkWRlpwh4ggxeKAO5bDjegUbeTluXdVV7UmnPNpNho1ABUgzYdNl26F92+cWE+GPrVdpFK4faESIfaQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=d102nr0h; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="d102nr0h" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-42cb1866c8fso815785e9.3 for ; Thu, 03 Oct 2024 01:14:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727943277; x=1728548077; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ArBelTC9NYknk17YOAC0+lV31yeITIe1wOVojgMQpJ4=; b=d102nr0hk8HMMrfif43TAV7maBp1Z8Wd1Tvgu6by5XAkRZeYR1EDAJ/SW8KYNtYSxb i/8Dwxul6Quk9yZqFeuOIrH7u5ocOLVTs1zDZqALcy41miLGd1bjAwSlEutoUvz9vecr 2ajmVb4v+twQkH6lQzhJzRQLGOnLabji+OOxyGKpy+AEpVE7WATlGGG8o3nW/7WWE3d7 gk8eC5mldzNlyY6U3KzF4AWyOMIu51ecxq2juqDHBwTnJSuODPDDDQBNgGlTQES3bP4g kTe1Ya95ALqTS98arkXm0t3qsVmKEVIbxzF4PtCstucOAi+97HkJlt0Nl+PpgL9Ildl2 mnTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727943277; x=1728548077; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ArBelTC9NYknk17YOAC0+lV31yeITIe1wOVojgMQpJ4=; b=qWcnpr7mDZuwJmmxPJk30NM7ZzMpc3OlEbFrw2ArYMzzT3Yx1/GFaijNoYYQ97nKhb QwRB4FylDV70+/9xVXWLR2ToV3Fu6vB5SyjpcCcIUxql5XgAZy/V5lMNW4Tt2Xdo2yRm fE+tzycwQK+sVe7ccTJ/zhkMMx5hVj4s4XfIl/Tvsu39EnFbm+Qb0RQgY3mI85QdiaAN B1SwJbzoqvLgxSS0zOP9HFKxD9waDQe1xfrHxExk4gYjZ67+eNwbiLtgrUZVqzNtp3j6 i86Bh4LppLRnMF2uoPpfhjmR6x/Or2IikIYawe2bpdGC/OCE1SBf1CkB9vO8xMTqlcL5 bqYw== X-Gm-Message-State: AOJu0YwXPKqyHG7bBEHrMH/0MeDw6xczk5l9w6EBnCnX4FScpf13jhO8 jfzEacHdguCjttxZx2cx/IBUG24SGlq6oqPwR7MxLuFfGaBQwEP4d2XzOAaQMzI= X-Google-Smtp-Source: AGHT+IEZZ9yqPRpUkj59+2e4tzhm/Y9ZxH9ngz6j0TXb/L0/Y1YM9lMtfkVQV3nVzkU4l8hHAEAmAg== X-Received: by 2002:a05:600c:1393:b0:42c:ba61:d20b with SMTP id 5b1f17b1804b1-42f790970b6mr19964015e9.3.1727943277392; Thu, 03 Oct 2024 01:14:37 -0700 (PDT) Received: from [127.0.1.1] ([178.197.211.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d082d230dsm702027f8f.94.2024.10.03.01.14.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 01:14:36 -0700 (PDT) From: Krzysztof Kozlowski Date: Thu, 03 Oct 2024 10:14:21 +0200 Subject: [PATCH 4/5] dt-bindings: display/msm: merge SM8450 DPU into SC7280 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241003-dt-binding-display-msm-merge-v1-4-91ab08fc76a2@linaro.org> References: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> In-Reply-To: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Neil Armstrong , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=5495; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=AKhgP7q0GaIQSUQKoHkiCv6d3dwP2bPLVjVUtecZON0=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBm/lJi9PKnUZKPp3bxs4fScDOr+KitJedC3+vAz 0o9qOFFaG2JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZv5SYgAKCRDBN2bmhouD 11upEACJ0BVnq8qjv3Ph2jKpGDLXGePbTEmqdtBS4tTB4aqUTYWkLBhapJkGGUSa04rNy3eDHdx 2Chu4qCpVLpNcHjHfnPQxkeUZYK0fH1ZJvMfTzbNQsq5OeIkWn8ARRPBO3wISAyh/U276apikcf 6Pd8hSW0YCJNbyygS807LXfA0RD25MVv8/azvytxtmnLKqvaJpWPdXSI8Fn/7osOh9PcvKs5r19 rhbTxv6AoRIgeoXHUtKh1/r/tco3c31H9fXHTQsz0J73B6DyoQFjzs7OXXmjDMvwxA/CmDFRlra pWEVEAQOC5W2vMFWRp+98Mnj+LlRaeqs+0dCZESTeZg4rlSsknaFiqb9qtqA5yUU+pDBSdIkvL/ yha2Clkxx243AZ+6wHZd7gVEEBXzFtpkPgOvami5bVTkIW0IDDgE7o1+VRi0z5SrvFiM5JwKUMV 2cD7ZFojH7Ivko0G5OQvE5bIftcK1Jhx9lvvSGHRE6dwe3l8YN3lyE9s+O8uY0fxjpdCEXoflpX XCHXoAg0Fz0AN1onmNQIruiCEav5AmsJm0L5nlBu7tOnNr93ugJlG4LRtHKtyPdHUcqexzaEuN7 QVkk0g8ddnRWELvo/slmntpKjvyn5X/SxkkMvYAZWo3JjpbrxEf14mX+MJd9J5U6YjX+4yDUX9f akLeIow5PLj1HHQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Split of the bindings was artificial and not helping - we end up with multiple binding files for very similar devices thus increasing the chances of using different order of reg and clocks entries. Unify DPU bindings of SC7280 and SM8450, because they are the same. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) --- .../bindings/display/msm/qcom,sc7280-dpu.yaml | 2 + .../bindings/display/msm/qcom,sm8450-dpu.yaml | 139 --------------------- 2 files changed, 2 insertions(+), 139 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index 3d69a573b450..750230839fc9 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -8,6 +8,7 @@ title: Qualcomm Display DPU on SC7280 maintainers: - Bjorn Andersson + - Dmitry Baryshkov - Krishna Manikandan $ref: /schemas/display/msm/dpu-common.yaml# @@ -18,6 +19,7 @@ properties: - qcom,sc7280-dpu - qcom,sc8280xp-dpu - qcom,sm8350-dpu + - qcom,sm8450-dpu reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml deleted file mode 100644 index 2a5d3daed0e1..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml +++ /dev/null @@ -1,139 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SM8450 Display DPU - -maintainers: - - Dmitry Baryshkov - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sm8450-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi - - description: Display sf axi - - description: Display ahb - - description: Display lut - - description: Display core - - description: Display vsync - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - -required: - - compatible - - reg - - reg-names - - clocks - - clock-names - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include - #include - #include - - display-controller@ae01000 { - compatible = "qcom,sm8450-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <19200000>; - - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - - mdp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-172000000{ - opp-hz = /bits/ 64 <172000000>; - required-opps = <&rpmhpd_opp_low_svs_d1>; - }; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-325000000 { - opp-hz = /bits/ 64 <325000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-375000000 { - opp-hz = /bits/ 64 <375000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; -... From patchwork Thu Oct 3 08:14:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13820772 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C51961482E8 for ; Thu, 3 Oct 2024 08:14:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727943283; cv=none; b=mapjLfC5OV0PaARi4Lt2hefsFMpnCAtuj63LXi9jQUkM+kB/bqMODLOY15EstveXUWC7kix6My1E3pgPJANfDnMqxcS0rVj4yFOifcmYbldwBXCRrtFM5YNb6Ttd5oKmSVttwXKWMWl66Xtw6sdqDlRKJKh6SS59KSO4yBoA5uc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727943283; c=relaxed/simple; bh=519873eizrz1N27nvT3FmdiGwc5SoCwK9tJ1LGTJkmw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=g37zDNKVv6ORcAdHkQpn72JJImVPUE81/LtQzaIojUJ0lK3OU8eVNolmAJ72kBp86LoAvVq43NOlMk/qG5OOK2qeNgAMEtQtfyGdVeJoe48xJh9TEiOrkVPvD/ZK/27jLEuwAWL9zJaJLwfa9rN0xZg+cJ04vngvAkHVUHd3Uh8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=LiEQ4yku; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LiEQ4yku" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-42cb3c6c353so1113335e9.3 for ; Thu, 03 Oct 2024 01:14:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1727943279; x=1728548079; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1rwyEFJ4idpDb4iBRYg6Jk2ZQkdCcSf0YAokuJ1SzVA=; b=LiEQ4ykuQNx2cZVv573Lu5sf9QbKUZ9BwUkMMgBNzAJmbS+nFUgEBL1nrWNKIq5YvK 5zyjiitEhXSj396yD1Rzf95g1UIMhF1Wk9hrtrpPNUsxTpMqpgHRmbDoNSM5Kimj+hC6 M5JfQNBsL+kePcuFqFSVCBKEYnnyrCKxbuMwYuTM3f40E28lSD4JVfD/gYYPtLEMU0w3 OpX/vG/eyajtxypSHaY7mpvU9fkdHTbs8XPq4F6OuSPTSN68lHYCita7QDRZRC15l6o5 RvZ//Nohc+uBZLmUP4l9ZMNl7WAqv3niVMqAH4dklPBSSGkicfgA/MhysDKTbWlxtukO WSfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727943279; x=1728548079; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1rwyEFJ4idpDb4iBRYg6Jk2ZQkdCcSf0YAokuJ1SzVA=; b=ThD3VBL9SGgqBKdkQg0vqyDE5Rzj7ZvkRQ5wKm5+0485TiTn6LSnpM98TuJ6w+wDO2 6WsW7sMll/7Wkf/T0Wz82w59/nYJ4ou7NNonNXiC49hylml/Or+MyAsbLCLyNQucU6fO DhUL8jF7kBaz9WYT1jxZ+uEJjoot3eBNmbmPRIeq3o+ySaVJJrOuo4iDSug2nqrWByc2 nNBGuQr3B5KfeL1V8colng8MbHFNyMmlY/gmTsD+Bi/ECklc2zJjGPUybkljmv9IwSt1 OGjlTDrsb4CwW44wGVneyRO4cPKWgY4XSMgKQTzPAKucIBuDW3jkvQjOpjYXn7a6dDKx b0hQ== X-Gm-Message-State: AOJu0Yy8vjDQwyLPdSj7ODRpgrkwzEFWC00fbMEsIkRJBjQphg4/71k6 VN7PCkm/Io7ZfohYu1knL1SP6FG5v8Qd6acnk1b7ngALEm8WI/4OZejyds8icIU= X-Google-Smtp-Source: AGHT+IGM0q7njLtYkyHsjlENSHcXM/bNjMhqikyJ3G8Gq5rle1uFsdl97+lU80Xh3CPM0h4uTp3hpA== X-Received: by 2002:a05:600c:1897:b0:42c:aeee:da86 with SMTP id 5b1f17b1804b1-42f77d30905mr19803775e9.8.1727943279187; Thu, 03 Oct 2024 01:14:39 -0700 (PDT) Received: from [127.0.1.1] ([178.197.211.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d082d230dsm702027f8f.94.2024.10.03.01.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 01:14:38 -0700 (PDT) From: Krzysztof Kozlowski Date: Thu, 03 Oct 2024 10:14:22 +0200 Subject: [PATCH 5/5] dt-bindings: display/msm: merge SM8550 DPU into SC7280 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241003-dt-binding-display-msm-merge-v1-5-91ab08fc76a2@linaro.org> References: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> In-Reply-To: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Neil Armstrong , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=5278; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=519873eizrz1N27nvT3FmdiGwc5SoCwK9tJ1LGTJkmw=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBm/lJjJVqi58VnNZDpSmxF/yPjCq9ttq1x7JffO wwQ5dtGGliJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZv5SYwAKCRDBN2bmhouD 176aD/4oATjZ3tdEJbCuEHszRygOjNaFfffil0utMA5XmiPMerjNs/BIIOcOH66nbj4ddfmYdUA 0E4vrdl3vSqyfS5V9JU14ebXyzspUgYv7Oo99XyI8vOFm+uOzlYvKBBjLOiRFykamVpRrAcP/rg j+FitluwEgTVQOFoG0HsrDnFtqWy+WuvUeVq0MttvA+2hZUMWCKQbBMpRKUg01Pbv6TGQv3EBSu qQStf0fz3iuwvjCEh0FXTS65QEp0csClhCfeGXLzz1KVjvLT+6szIwzFcURy/ZOUJRlHa36MYvm mR0xjRSYkt/SZWLyFCKEH0No4KEZNi7Hto1t1T44/pk0xAIRRTs5kv3fRxZUXumzs88SpchJBJp 08UVEAmS4hj2tcR2HZUlQNDFcxD3+neEoEPHs4wPqdpGq//uUtFbmRFaeMBBPrS7uKko/M6odnd IStITPXnIEPR3fL8rxiT2loTBwUL8eI4PiZRAVCFSGkyMI1bkHKV9xATWxeMc+ehzHqoXa2ONz9 oizmEDr8zkm20TWXT4f5v7RU5wm5SATYTOvZUv2lILuIg/QiK1O88JCfcQDVg35HCxtGjUQjCtX lFbeQKiFqjWfoDDI4rNSOBB05D7+COA7Je1v0lnY332TmB3UVCEAG7exTZ1ApvZdgcOzF5JQ5MU G6kFNAERUhheIbw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Split of the bindings was artificial and not helping - we end up with multiple binding files for very similar devices thus increasing the chances of using different order of reg and clocks entries. Unify DPU bindings of SC7280 and SM8550, because they are the same. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) --- .../bindings/display/msm/qcom,sc7280-dpu.yaml | 2 + .../bindings/display/msm/qcom,sm8550-dpu.yaml | 133 --------------------- 2 files changed, 2 insertions(+), 133 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index 750230839fc9..6902795b4e2c 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -8,6 +8,7 @@ title: Qualcomm Display DPU on SC7280 maintainers: - Bjorn Andersson + - Neil Armstrong - Dmitry Baryshkov - Krishna Manikandan @@ -20,6 +21,7 @@ properties: - qcom,sc8280xp-dpu - qcom,sm8350-dpu - qcom,sm8450-dpu + - qcom,sm8550-dpu reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml deleted file mode 100644 index 16a541fca66f..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml +++ /dev/null @@ -1,133 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SM8550 Display DPU - -maintainers: - - Neil Armstrong - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sm8550-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display AHB - - description: Display hf axi - - description: Display MDSS ahb - - description: Display lut - - description: Display core - - description: Display vsync - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - -required: - - compatible - - reg - - reg-names - - clocks - - clock-names - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include - #include - - display-controller@ae01000 { - compatible = "qcom,sm8550-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <19200000>; - - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; - }; - - mdp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-325000000 { - opp-hz = /bits/ 64 <325000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-375000000 { - opp-hz = /bits/ 64 <375000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-514000000 { - opp-hz = /bits/ 64 <514000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; -...