From patchwork Fri Oct 4 14:07:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Miclaus, Antoniu" X-Patchwork-Id: 13822450 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A78E1215F44; Fri, 4 Oct 2024 14:11:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728051104; cv=none; b=kn0uk4jAuQZ+e/3uICvKEUijblfpVWu5hU1OIHZbE0I0ZrSPSfYg9M1QkHa6CAru5hiNtMhPjZPgDcGg4bcW4tGfxZXsOkPc7+aJO1XKMlN4pTBAMxg5mZ/Djs7wbNB5rpFqpoEHOTUmHhysjD6JwSTKz2QiidnX4UVgUe70YL4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728051104; c=relaxed/simple; bh=QwUCQelik+i6A1CNkuyr3H1FyUX/TmP+s+Jg2M0467w=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=ea3m0R9OK2TiyABdiXZpfKpoijf0fT8eBZGhzqpC5rOBWobBeBmBn5mU+kh6bEQnpjHz+pvJmys6h54Oe1DIf3RDhRVLMX0gnpJw3ByicqEssyWohBo52cuxGJjF4WZ0Mpkn35tK6CdJvE5PhD1pwwDThLiqeeCzxq5NoD+Y/5Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=xs5lVp5k; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="xs5lVp5k" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 494CwJTL001362; Fri, 4 Oct 2024 10:11:15 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h= content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=DKIM; bh=//wQT8iUlWPMtMdf7cCIJhY2fqG xs6wkalMGWLlGMso=; b=xs5lVp5krrt1vGiKflxo1qXGR9y4fXUxM+ydFZohIGc t1KhGOCvqTj2Nj1/yU+drIIq8L+IxLGZX0Sj9WmOM88vT479ReudUWSHzkcbwY8n VLoAT9lcmYNogSC6VnEJfdbdUfe0IM0s2MjXEllrGxygY4hRR7iRuw4SNfZNC/7B 2YedSV/CB13abRm7VVRB2TPIUeJOSnzbKXzgI6bke8T2fEW7DR+eans0k5tlzeqr PEREC6NqRw2FcqYNtaj60k+JXJBskATkF/lvu0jtbDgA1JHWnyIUjV5+ot1zptFR d5yt72m/hh928BDvs6o0okhm4f+viAHvDLXvdqiXuyw== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 422043410d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Oct 2024 10:11:15 -0400 (EDT) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 494EBEod002599 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 4 Oct 2024 10:11:14 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 4 Oct 2024 10:11:14 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 4 Oct 2024 10:11:13 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.173]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 494EAps1001773; Fri, 4 Oct 2024 10:10:54 -0400 From: Antoniu Miclaus To: Jonathan Cameron , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nuno Sa , Olivier Moysan , =?utf-8?q?Uwe_Kleine-K=C3=B6ni?= =?utf-8?q?g?= , Andy Shevchenko , David Lechner , Marcelo Schmitt , Mike Looijmans , =?utf-8?q?Jo=C3=A3o_Paulo_Gon?= =?utf-8?q?=C3=A7alves?= , Dumitru Ceclan , AngeloGioacchino Del Regno , Alisa-Dariana Roman , Sergiu Cuciurean , Dragos Bogdan , Antoniu Miclaus , , , , Subject: [PATCH v2 1/7] iio: backend: add API for interface get Date: Fri, 4 Oct 2024 17:07:50 +0300 Message-ID: <20241004140922.233939-1-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.46.2 Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: 9kRTFBQLyZTItF8hinWGCXcJG6G0jQPk X-Proofpoint-GUID: 9kRTFBQLyZTItF8hinWGCXcJG6G0jQPk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 impostorscore=0 mlxscore=0 phishscore=0 adultscore=0 clxscore=1015 mlxlogscore=999 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040099 Add backend support for obtaining the interface type used. Signed-off-by: Antoniu Miclaus --- changes in v2: - add IIO_BACKEND_INTERFACE_COUNT in enum. - add trailing commas where applies. drivers/iio/industrialio-backend.c | 24 ++++++++++++++++++++++++ include/linux/iio/backend.h | 11 +++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/iio/industrialio-backend.c b/drivers/iio/industrialio-backend.c index efe05be284b6..a322b0be7b2c 100644 --- a/drivers/iio/industrialio-backend.c +++ b/drivers/iio/industrialio-backend.c @@ -449,6 +449,30 @@ ssize_t iio_backend_ext_info_set(struct iio_dev *indio_dev, uintptr_t private, } EXPORT_SYMBOL_NS_GPL(iio_backend_ext_info_set, IIO_BACKEND); +/** + * iio_backend_interface_type_get - get the interace type used. + * @back: Backend device + * @type: Interface type + * + * RETURNS: + * 0 on success, negative error number on failure. + */ +int iio_backend_interface_type_get(struct iio_backend *back, + enum iio_backend_interface_type *type) +{ + int ret; + + ret = iio_backend_op_call(back, interface_type_get, type); + if (ret) + return ret; + + if (*type >= IIO_BACKEND_INTERFACE_COUNT) + return -EINVAL; + + return 0; +} +EXPORT_SYMBOL_NS_GPL(iio_backend_interface_type_get, IIO_BACKEND); + /** * iio_backend_extend_chan_spec - Extend an IIO channel * @indio_dev: IIO device diff --git a/include/linux/iio/backend.h b/include/linux/iio/backend.h index 8099759d7242..34fc76c99d8a 100644 --- a/include/linux/iio/backend.h +++ b/include/linux/iio/backend.h @@ -63,6 +63,12 @@ enum iio_backend_sample_trigger { IIO_BACKEND_SAMPLE_TRIGGER_MAX }; +enum iio_backend_interface_type { + IIO_BACKEND_INTERFACE_LVDS, + IIO_BACKEND_INTERFACE_CMOS, + IIO_BACKEND_INTERFACE_COUNT, +}; + /** * struct iio_backend_ops - operations structure for an iio_backend * @enable: Enable backend. @@ -81,6 +87,7 @@ enum iio_backend_sample_trigger { * @extend_chan_spec: Extend an IIO channel. * @ext_info_set: Extended info setter. * @ext_info_get: Extended info getter. + * @interface_type_get: Interface type. **/ struct iio_backend_ops { int (*enable)(struct iio_backend *back); @@ -113,6 +120,8 @@ struct iio_backend_ops { const char *buf, size_t len); int (*ext_info_get)(struct iio_backend *back, uintptr_t private, const struct iio_chan_spec *chan, char *buf); + int (*interface_type_get)(struct iio_backend *back, + enum iio_backend_interface_type *type); }; int iio_backend_chan_enable(struct iio_backend *back, unsigned int chan); @@ -142,6 +151,8 @@ ssize_t iio_backend_ext_info_set(struct iio_dev *indio_dev, uintptr_t private, ssize_t iio_backend_ext_info_get(struct iio_dev *indio_dev, uintptr_t private, const struct iio_chan_spec *chan, char *buf); +int iio_backend_interface_type_get(struct iio_backend *back, + enum iio_backend_interface_type *type); int iio_backend_extend_chan_spec(struct iio_dev *indio_dev, struct iio_backend *back, struct iio_chan_spec *chan); From patchwork Fri Oct 4 14:07:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Miclaus, Antoniu" X-Patchwork-Id: 13822451 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C7292178FB; Fri, 4 Oct 2024 14:11:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728051114; cv=none; b=N9NujHQ0UtCQJfyRlSvEGmK6PdqC2lK4uxf6rnRinEgTSlos3OzAUUZtEnJbcpBubT2pGLqX9OffEzzXoSQz8e+6YMtSfRH46K/Ih9TQaFvilAiKedgoSv+WuCjBoac3F2Rj4/vglIs0WpKSZdbbauC4A860/QZgGRCXHtRQTQs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728051114; c=relaxed/simple; bh=ktM0phdnuSW8WJGf8ylz0VoKC2MN8v+xOS3UftlUHuQ=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EbEclgd9XH6lqLeTRFWObN/CYs8Z88r3bJsrz+zvxjHZs9nP8SyjiBk25gURYJ878B3gVA4K+Qt/2pS5qD/Idvsk6937HFXBLdaG3ubpoVLD2sWbZQV87JTwzN7oR0OiEhsIU3w72qQlGrPDiRsmX8iydIplj5cH6zE93HIA8Fg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=kUEOfEvJ; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="kUEOfEvJ" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 494Bt54o001476; Fri, 4 Oct 2024 10:11:29 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=7bP1m NbTfWLDWnOvnRC1lLrsY2IrvVC6U/wzgyNzdHI=; b=kUEOfEvJdJO7O2ZIptuIw 3xC0AzsxhK/e9l3fvYHGP1/xBryP/20ZyzMmlZ9RDJ73nBzN80fcHzL5sBbjA9Be 8RWB9M1soa5vKTDSdTJVOLFyZQ2HxbTfMmw3ISyFeD921icRx8aRo/1YdmYB3kOY oo5ylabJaMDUHnsXbk6gDUGjwseyQ/1+DrCxGg+1rfK+C6jpWG3t6WM0EPUCNPBM fD+59WWySEo7Qu9kO2Il3Q0IipfemjVRIvA7zSCOLQwuB8ACTzj2DLc3qKRLfTBV QdcMRPfabzPNjmg8KDCF7TxCa/PwO+kvlR9f4fYb8NRm0i6ZNnKaLDHncTiOJz6C A== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4220434119-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Oct 2024 10:11:28 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 494EBRi0002622 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 4 Oct 2024 10:11:27 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 4 Oct 2024 10:11:27 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 4 Oct 2024 10:11:27 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.173]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 494EAps2001773; Fri, 4 Oct 2024 10:11:22 -0400 From: Antoniu Miclaus To: Jonathan Cameron , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nuno Sa , Olivier Moysan , =?utf-8?q?Uwe_Kleine-K=C3=B6ni?= =?utf-8?q?g?= , Andy Shevchenko , David Lechner , Marcelo Schmitt , Dumitru Ceclan , Ivan Mikhaylov , =?utf-8?q?Jo=C3=A3o_Paulo_Gon=C3=A7al?= =?utf-8?q?ves?= , Antoniu Miclaus , Alisa-Dariana Roman , AngeloGioacchino Del Regno , Sergiu Cuciurean , Dragos Bogdan , , , , Subject: [PATCH v2 2/7] iio: backend: add support for data size set Date: Fri, 4 Oct 2024 17:07:51 +0300 Message-ID: <20241004140922.233939-2-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241004140922.233939-1-antoniu.miclaus@analog.com> References: <20241004140922.233939-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: EK3j5HJaKfdu_yTI2tGB9T8kPO5xEmw6 X-Proofpoint-GUID: EK3j5HJaKfdu_yTI2tGB9T8kPO5xEmw6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 impostorscore=0 mlxscore=0 phishscore=0 adultscore=0 clxscore=1015 mlxlogscore=999 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040099 Add backend support for setting the data size used. This setting can be adjusted within the IP cores interfacing devices. Signed-off-by: Antoniu Miclaus --- changes in v2: - use Return: instead of RETURN. - use size_t instead of ssize_t - improve commit message. drivers/iio/industrialio-backend.c | 21 +++++++++++++++++++++ include/linux/iio/backend.h | 3 +++ 2 files changed, 24 insertions(+) diff --git a/drivers/iio/industrialio-backend.c b/drivers/iio/industrialio-backend.c index a322b0be7b2c..9aaa90ed1274 100644 --- a/drivers/iio/industrialio-backend.c +++ b/drivers/iio/industrialio-backend.c @@ -473,6 +473,27 @@ int iio_backend_interface_type_get(struct iio_backend *back, } EXPORT_SYMBOL_NS_GPL(iio_backend_interface_type_get, IIO_BACKEND); +/** + * iio_backend_data_size_set - set the data width/size in the data bus. + * @back: Backend device + * @size: Size in bits + * + * Some frontend devices can dynamically control the word/data size on the + * interface/data bus. Hence, the backend device needs to be aware of it so + * data can be correctly transferred. + * + * Return: + * 0 on success, negative error number on failure. + */ +size_t iio_backend_data_size_set(struct iio_backend *back, size_t size) +{ + if (!size) + return -EINVAL; + + return iio_backend_op_call(back, data_size_set, size); +} +EXPORT_SYMBOL_NS_GPL(iio_backend_data_size_set, IIO_BACKEND); + /** * iio_backend_extend_chan_spec - Extend an IIO channel * @indio_dev: IIO device diff --git a/include/linux/iio/backend.h b/include/linux/iio/backend.h index 34fc76c99d8a..18e571a24251 100644 --- a/include/linux/iio/backend.h +++ b/include/linux/iio/backend.h @@ -88,6 +88,7 @@ enum iio_backend_interface_type { * @ext_info_set: Extended info setter. * @ext_info_get: Extended info getter. * @interface_type_get: Interface type. + * @data_size_set: Data size. **/ struct iio_backend_ops { int (*enable)(struct iio_backend *back); @@ -122,6 +123,7 @@ struct iio_backend_ops { const struct iio_chan_spec *chan, char *buf); int (*interface_type_get)(struct iio_backend *back, enum iio_backend_interface_type *type); + int (*data_size_set)(struct iio_backend *back, ssize_t size); }; int iio_backend_chan_enable(struct iio_backend *back, unsigned int chan); @@ -153,6 +155,7 @@ ssize_t iio_backend_ext_info_get(struct iio_dev *indio_dev, uintptr_t private, int iio_backend_interface_type_get(struct iio_backend *back, enum iio_backend_interface_type *type); +size_t iio_backend_data_size_set(struct iio_backend *back, size_t size); int iio_backend_extend_chan_spec(struct iio_dev *indio_dev, struct iio_backend *back, struct iio_chan_spec *chan); From patchwork Fri Oct 4 14:07:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Miclaus, Antoniu" X-Patchwork-Id: 13822452 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1F652178F7; Fri, 4 Oct 2024 14:12:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728051129; cv=none; b=diCptL6lyPD7RblSO/V/UC6xzaKZOFU4hTf9rA80iQIhIuqkEx0FgqM76Cp5VOcDCaRZBAydGERfruo1J/13nyU4mhPe5iUSTye6ZEgbq7LNTJyIhb1o95P0Uy2X4MPOCSZLbcjieNz/N2T3lfDo38rzB9iLOnsU6Gp0D60SZcA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728051129; c=relaxed/simple; bh=40sfDcPyL0Hv1P/AU/av8gnSSCv03Ys03LUEWCmCLxI=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=b5AM9JuSZaptFbVWHcIfqBRMC5P8LaaZq96K0bIr5J68Zaw2YL2MoqAjsroTp95vewm/StLQrVtD/7NdnLMMvyf8QDqc5mCW+wuzh3vYjuPOFKrbXNRWSx09bLOZFmx6IuLDHPV4CRD3XObDsXCha+i3axGJOHzRupKXnpxt9fM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=cnTBkBpr; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="cnTBkBpr" Received: from pps.filterd (m0375855.ppops.net [127.0.0.1]) by mx0b-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 494CvDMP003491; Fri, 4 Oct 2024 10:11:46 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=z1RZ+ tv4zaSK4SQ0s7iKEjYgOMKy6YkwVwz3k9BMgO8=; b=cnTBkBprthQqt4g3OK8De 3aV5K5Ql808p+i46kg9qCOPkk/S3dD+w/EfHFTbghKCMAzMf8EgWW1Tz6whU6QEJ H7m9kEO3vJda4ADgMJBUcEg/Q0l2zBDpzZ2BatKRwyIL2h808G8SbWTKVHtAT158 KAIVBDQiMLc7AiVBCBe6cvvaXywKCQrJdJDVgf/M/MfKiqwVE3f6PM9GeP0BVgVo /k66SUMmhPB2NnkI4Sev9hlehmjJx6ilpXqbDl0i1bxQXzzvDR31H+Gj+0QPD6c7 vcYmWFhjvSaKRL694mpqyb9q9nboTk5zP4T8Act8P4YcvO9wkov8kmY7cMC9lMIA g== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0b-00128a01.pphosted.com (PPS) with ESMTPS id 42206cky01-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Oct 2024 10:11:45 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 494EBieD002647 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 4 Oct 2024 10:11:44 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 4 Oct 2024 10:11:44 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 4 Oct 2024 10:11:43 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.173]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 494EAps3001773; Fri, 4 Oct 2024 10:11:36 -0400 From: Antoniu Miclaus To: Jonathan Cameron , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nuno Sa , Olivier Moysan , =?utf-8?q?Uwe_Kleine-K=C3=B6ni?= =?utf-8?q?g?= , Andy Shevchenko , David Lechner , Marcelo Schmitt , Ivan Mikhaylov , Antoniu Miclaus , Dumitru Ceclan , AngeloGioacchino Del Regno , Alisa-Dariana Roman , Mike Looijmans , Sergiu Cuciurean , Dragos Bogdan , , , , Subject: [PATCH v2 3/7] iio: adc: adi-axi-adc: add interface type Date: Fri, 4 Oct 2024 17:07:52 +0300 Message-ID: <20241004140922.233939-3-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241004140922.233939-1-antoniu.miclaus@analog.com> References: <20241004140922.233939-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: eBGkyJySlFeQ1aFunwULnmRGovPhJVKt X-Proofpoint-GUID: eBGkyJySlFeQ1aFunwULnmRGovPhJVKt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 phishscore=0 mlxscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040099 Add support for getting the interface (CMOS or LVDS) used by the AXI ADC ip. Signed-off-by: Antoniu Miclaus --- no changes in v2. drivers/iio/adc/adi-axi-adc.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index 21ce7564e83d..ff48f26e02a3 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -39,6 +39,9 @@ #define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1) #define ADI_AXI_REG_RSTN_RSTN BIT(0) +#define ADI_AXI_ADC_REG_CONFIG 0x000c +#define ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N BIT(7) + #define ADI_AXI_ADC_REG_CTRL 0x0044 #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) @@ -249,6 +252,25 @@ static int axi_adc_chan_disable(struct iio_backend *back, unsigned int chan) ADI_AXI_REG_CHAN_CTRL_ENABLE); } +static int axi_adc_interface_type_get(struct iio_backend *back, + enum iio_backend_interface_type *type) +{ + struct adi_axi_adc_state *st = iio_backend_get_priv(back); + unsigned int val; + int ret; + + ret = regmap_read(st->regmap, ADI_AXI_ADC_REG_CONFIG, &val); + if (ret) + return ret; + + if (val & ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N) + *type = IIO_BACKEND_INTERFACE_CMOS; + else + *type = IIO_BACKEND_INTERFACE_LVDS; + + return 0; +} + static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back, struct iio_dev *indio_dev) { @@ -285,6 +307,7 @@ static const struct iio_backend_ops adi_axi_adc_generic = { .iodelay_set = axi_adc_iodelays_set, .test_pattern_set = axi_adc_test_pattern_set, .chan_status = axi_adc_chan_status, + .interface_type_get = axi_adc_interface_type_get, }; static int adi_axi_adc_probe(struct platform_device *pdev) From patchwork Fri Oct 4 14:07:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Miclaus, Antoniu" X-Patchwork-Id: 13822453 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13BCE215F48; Fri, 4 Oct 2024 14:12:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728051143; cv=none; b=HV2xJ19Fmh6pWUc4bNPwKzDqavMH5GgRLF0hFKPJLH25b2ApatRISCjUo5wQo+KxA1cuCaoE6L/yWwvWwGs6vhH670bvWWXMFAeMvvgX/zSYDd24WpUma01KvXM8blqtQVODjZSwSueKkC3ObJDg1hAuCBxWbE1wcX8RGC5dujM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728051143; c=relaxed/simple; bh=mi7TDRrmv6UimYFq6NJLsYzBW8sIs6VNVvOfBicGJzk=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eBbhvWFUcXdgTv4sjjyPyPnjasN6VIMOJ4c4Xm0z6rLTfNgH+VE+bPgjpepCoVf1Walb+odF0fI2034cDQJB/5gVoqCmkwERMcxm6lRP+yRu5xOLCmSRqv5dMoPTe7mtdR9mO0QrCJLhfUoJIxOTVBEounaPUaReAh76NKtZr/Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=vlWxzRpt; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="vlWxzRpt" Received: from pps.filterd (m0375855.ppops.net [127.0.0.1]) by mx0b-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 494B7SRU003498; Fri, 4 Oct 2024 10:12:01 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=d/Bue uyoKPZLuShNejgMuaZuCApeutDm2KIOpx6lp6c=; b=vlWxzRpt3R6EFn0u20laV fUakUoGVSzEV+kYlqV4/oXG0i2HHbNrUs8wMyjFywPf6mVY89UKdTegfBfPYp9Zg MNY3a32D0m33BDgCNYAr9sSDa6n8rFzb2Fu2PSUOCVRKQpCCn8IR2JXpEEZOZdjd py7AiuNgThyVBp+9q1DLG678vSeA+UmFvpxvvZE/PrHX/9gR7HBzM3AxfDKFLsCw KJnwG0Ov20BddYTovgczTyi5EVWCbDzTtsck7yt5m+rMA8mv0BgzzwFoHeUpnKO4 MtdM1/57RdLWajXa79AA7rEKh7EMavrAOS4B+Y+DkG7nYomeA4XHUfObAAsbyJHB w== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0b-00128a01.pphosted.com (PPS) with ESMTPS id 42206cky16-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Oct 2024 10:12:00 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 494EBv1t002670 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 4 Oct 2024 10:11:57 -0400 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 4 Oct 2024 10:11:57 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 4 Oct 2024 10:11:57 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 4 Oct 2024 10:11:57 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.173]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 494EAps4001773; Fri, 4 Oct 2024 10:11:49 -0400 From: Antoniu Miclaus To: Jonathan Cameron , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nuno Sa , Olivier Moysan , =?utf-8?q?Uwe_Kleine-K=C3=B6ni?= =?utf-8?q?g?= , Andy Shevchenko , David Lechner , Marcelo Schmitt , Dumitru Ceclan , Antoniu Miclaus , =?utf-8?q?Jo=C3=A3o_Paulo_Gon?= =?utf-8?q?=C3=A7alves?= , AngeloGioacchino Del Regno , Alisa-Dariana Roman , Marius Cristea , Sergiu Cuciurean , Dragos Bogdan , , , , Subject: [PATCH v2 4/7] iio: adc: adi-axi-adc: set data format Date: Fri, 4 Oct 2024 17:07:53 +0300 Message-ID: <20241004140922.233939-4-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241004140922.233939-1-antoniu.miclaus@analog.com> References: <20241004140922.233939-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: b3Hc6qwoA3NXOU9dhKjFj-dauySk7erb X-Proofpoint-GUID: b3Hc6qwoA3NXOU9dhKjFj-dauySk7erb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 phishscore=0 mlxscore=0 malwarescore=0 clxscore=1011 priorityscore=1501 lowpriorityscore=0 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040099 Add support for selecting the data format within the AXI ADC ip. Signed-off-by: Antoniu Miclaus --- changes in v2: - add ADI_AXI_ADC_CNTRL_3_CUSTOM_CONTROL_MSK and use regmap_update_bits drivers/iio/adc/adi-axi-adc.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index ff48f26e02a3..363cc29b4c18 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -45,6 +45,9 @@ #define ADI_AXI_ADC_REG_CTRL 0x0044 #define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1) +#define ADI_AXI_ADC_REG_CNTRL_3 0x004c +#define ADI_AXI_ADC_CNTRL_3_CUSTOM_CONTROL_MSK GENMASK(7, 0) + #define ADI_AXI_ADC_REG_DRP_STATUS 0x0074 #define ADI_AXI_ADC_DRP_LOCKED BIT(17) @@ -271,6 +274,25 @@ static int axi_adc_interface_type_get(struct iio_backend *back, return 0; } +static int axi_adc_data_size_set(struct iio_backend *back, + ssize_t size) +{ + struct adi_axi_adc_state *st = iio_backend_get_priv(back); + unsigned int val; + + if (size <= 20) + val = 0; + else if (size <= 24) + val = 1; + else if (size <= 32) + val = 3; + else + return -EINVAL; + + return regmap_update_bits(st->regmap, ADI_AXI_ADC_REG_CNTRL_3, + ADI_AXI_ADC_CNTRL_3_CUSTOM_CONTROL_MSK, val); +} + static struct iio_buffer *axi_adc_request_buffer(struct iio_backend *back, struct iio_dev *indio_dev) { @@ -308,6 +330,7 @@ static const struct iio_backend_ops adi_axi_adc_generic = { .test_pattern_set = axi_adc_test_pattern_set, .chan_status = axi_adc_chan_status, .interface_type_get = axi_adc_interface_type_get, + .data_size_set = axi_adc_data_size_set, }; static int adi_axi_adc_probe(struct platform_device *pdev) From patchwork Fri Oct 4 14:07:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Miclaus, Antoniu" X-Patchwork-Id: 13822454 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 257D52101B0; Fri, 4 Oct 2024 14:12:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728051168; cv=none; b=pAe25xmfM2FQ1w1faHhrpuSnAWXMecdRmsF9BZ8jQeBm82Hpdpv3lhoR+AeT5V6poO+XfXu+xT40vrQqEAvQVo125ymKGAddeWS/4JWcuJUXVnMjXllIGGTi5gr+E5WPyFnBGBU9K+6zTwBA+DeIvjcITsZFuHu5rQRPHHIMEbQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728051168; c=relaxed/simple; bh=5lW8oMEFmW7p6x8FGFF04WMN74g9Dt3tlSQpUik1Vfg=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jTb6gROs26ep7RVUcXEzaKiAil7PBjxiBc1+ra3ashXAob/DP4aq82h6Wk5EFsog1QPm60kai8cFDzlec9/bl4tFfdZCcOIoG7BOmGJJ+Hrb3CGsyVSKPsbFrMDrWHe95bsAiUF1El6BBzmSAscC8izgGjZF6TsHP3JfcHyE4Kw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=DkKbqE39; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="DkKbqE39" Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 494CXItR001474; Fri, 4 Oct 2024 10:12:17 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=bkUpO 7u7CuSY6YV6dzInnLhdyATuUaRS3aliQkkJWlg=; b=DkKbqE39l10MnuruFpSHz BI0TDGeBvaCwMRwzceEeqQjsE+YiRJr8Wxx2TQLt5r0y7mUshdA9L/y8aKAWE5EP WozruF6WQExKlqyu0Xtbc13sNxGdk0VO2QTTXFB7FlFI4Cy30JxwKLlKyhZMSlXs IBVlCZO94WvJzIK3lrUbM+ykkCnGdN9QWQF3dJE0D/3nVsPYbr4UF3Fk1JxhCkpN KoeyglpTo0+ST88C1VF/+MevdPddwWPE1PNn1TlQxImjAx5HIk6BDPcqhOoMQoEG B491LOC6p9AGYBGo9637lSegS3DneK3o0xF//T3nbcMBG+RhErf86ZmQbs2/30FX g== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 4220434147-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Oct 2024 10:12:17 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 494ECGBu002697 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 4 Oct 2024 10:12:16 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 4 Oct 2024 10:12:16 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 4 Oct 2024 10:12:15 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.173]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 494EAps5001773; Fri, 4 Oct 2024 10:12:05 -0400 From: Antoniu Miclaus To: Jonathan Cameron , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nuno Sa , Olivier Moysan , =?utf-8?q?Uwe_Kleine-K=C3=B6ni?= =?utf-8?q?g?= , Andy Shevchenko , David Lechner , Marcelo Schmitt , =?utf-8?q?Jo=C3=A3o_Paulo_Gon?= =?utf-8?q?=C3=A7alves?= , Ivan Mikhaylov , Dumitru Ceclan , Antoniu Miclaus , Alisa-Dariana Roman , Marius Cristea , AngeloGioacchino Del Regno , Mike Looijmans , Sergiu Cuciurean , Dragos Bogdan , , , , Subject: [PATCH v2 5/7] dt-bindings: iio: adc: add ad485x Date: Fri, 4 Oct 2024 17:07:54 +0300 Message-ID: <20241004140922.233939-5-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241004140922.233939-1-antoniu.miclaus@analog.com> References: <20241004140922.233939-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: b7O_c4W7JqEN338smsj8fMtmW1WcZOM5 X-Proofpoint-GUID: b7O_c4W7JqEN338smsj8fMtmW1WcZOM5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 impostorscore=0 mlxscore=0 phishscore=0 adultscore=0 clxscore=1015 mlxlogscore=999 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040099 Add devicetree bindings for ad485x family. Signed-off-by: Antoniu Miclaus Reviewed-by: Conor Dooley --- changes in v2: - link all public parts in the description - add $ref: /schemas/spi/spi-peripheral-props.yaml# - add vee-supply - add vddl-supply - add description for pwms - add pd-gpios - update spi-max-frequency value - make vddh-supply optional, not required. - update example based on new properties added. - fix typos in commit message/title. - update year to 2024 - drop "DAS" and "device driver" from bindings description. .../bindings/iio/adc/adi,ad485x.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad485x.yaml +... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad485x.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad485x.yaml new file mode 100644 index 000000000000..899a65504f12 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad485x.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad485x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD485X family + +maintainers: + - Sergiu Cuciurean + - Dragos Bogdan + - Antoniu Miclaus + +description: | + Analog Devices AD485X family + + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4858.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4857.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4856.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4855.pdf + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad4858 + - adi,ad4857 + - adi,ad4856 + - adi,ad4855 + - adi,ad4854 + - adi,ad4853 + - adi,ad4852 + - adi,ad4851 + - adi,ad4858i + + reg: + maxItems: 1 + + vcc-supply: true + + vee-supply: true + + vdd-supply: true + + vddh-supply: true + + vddl-supply: true + + vio-supply: true + + pwms: + description: PWM connected to the CNV pin. + maxItems: 1 + + io-backends: + maxItems: 1 + + pd-gpios: + maxItems: 1 + + spi-max-frequency: + maximum: 25000000 + +required: + - compatible + - reg + - vcc-supply + - vee-supply + - vdd-supply + - vio-supply + - pwms + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0{ + compatible = "adi,ad4858"; + reg = <0>; + spi-max-frequency = <10000000>; + vcc-supply = <&vcc>; + vdd-supply = <&vdd>; + vee-supply = <&vee>; + vddh-supply = <&vddh>; + vddl-supply = <&vddh>; + vio-supply = <&vio>; + pwms = <&pwm_gen 0 0>; + io-backends = <&iio_backend>; + }; + }; From patchwork Fri Oct 4 14:07:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Miclaus, Antoniu" X-Patchwork-Id: 13822455 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 000B121948A; Fri, 4 Oct 2024 14:12:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728051178; cv=none; b=k8oyFZQAGDbiTQYzMgtrgEqmP8yC/3h62Y1gOh05GpBoj6cHeVXv0BXf4qikB+RhqCSGHkUtOYu+zYd1ESAUzFwGhJUELxgsDFR2FhWsOeP8lCHbdjrZQktIfc9qLqUFpd63FbMm2xonoy924XUMVt8Wyb3wcJeRtHRHbhOzVTU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728051178; c=relaxed/simple; bh=pzW7iuyzRD2K759N01E5Jaz26IcNvpUm4uAbf2rWQLw=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AHb2wBQZaU80sIeWhA0kOsAPOAscmBWJNCVnFv08q1MX02nqNzSJX5Uvf3tDJNefmA3eW/W7dPlDwBzxH7PEmdIw2IWuT7NMGDwR2L9FnUzyULlnYoYIE6gurE+ydA/A6ia7wjwVHaUoJAzSMUcvIgCWOVAPxVom066nWrEikOA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=EqEO9+iM; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="EqEO9+iM" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 494CRWL0018542; Fri, 4 Oct 2024 10:12:33 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=hDxri lQhpy2H1zj6HuSbX6K/M4nBLm9dU04rOyXlAyM=; b=EqEO9+iMmQ2GBJyyxxNuS cphRf+gBMmDX20GnMTosQ3tZp7kiJYVhcbCSTvVxqzM/LUJ/5PlbEkUPUmnY8kZT BQC62/37uY3NUniuoNsNtrlpcAD0fOesWJ+gAqfE3lNtooOP770FR18RqMkNO8Dq lIZ59gGXJesgE9xhnsboTZzXy7mTWOpnNh/XcqV0qAYGinKbsuS/QHdAJo4UCt4U eO0R3z79aJThFXj++6qqBMpcBBtXoct7be75sdXVxRtxpIVO3Y1cK+m889as0lQs b3Rwm3ad+zd4c7IQN/7Qs44w5+/hqQIDKPMq1egUXSjbISaO7wYzIwy21y6K+yb1 g== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 422043kx44-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Oct 2024 10:12:33 -0400 (EDT) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 494ECVnd002721 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 4 Oct 2024 10:12:31 -0400 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 4 Oct 2024 10:12:31 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 4 Oct 2024 10:12:31 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 4 Oct 2024 10:12:31 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.173]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 494EAps6001773; Fri, 4 Oct 2024 10:12:21 -0400 From: Antoniu Miclaus To: Jonathan Cameron , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nuno Sa , Olivier Moysan , =?utf-8?q?Uwe_Kleine-K=C3=B6ni?= =?utf-8?q?g?= , Andy Shevchenko , David Lechner , Marcelo Schmitt , "Mike Looijmans" , Marius Cristea , Dumitru Ceclan , Antoniu Miclaus , AngeloGioacchino Del Regno , Alisa-Dariana Roman , Ivan Mikhaylov , "Sergiu Cuciurean" , Dragos Bogdan , , , , Subject: [PATCH v2 6/7] iio: adc: ad485x: add ad485x driver Date: Fri, 4 Oct 2024 17:07:55 +0300 Message-ID: <20241004140922.233939-6-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241004140922.233939-1-antoniu.miclaus@analog.com> References: <20241004140922.233939-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: 8x-ZYWrZfhZ0ipt9tH6ssrRdXEGtxgf4 X-Proofpoint-GUID: 8x-ZYWrZfhZ0ipt9tH6ssrRdXEGtxgf4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 suspectscore=0 mlxlogscore=999 mlxscore=0 bulkscore=0 impostorscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040099 Add support for the AD485X DAS familiy. Signed-off-by: Antoniu Miclaus --- changes in v2: - update headers and include the missing ones, order them alphabetically. - use clamp() - use units macros where applies - convert int to unsigned variables where applies. - add trailing commas where applies. - return FIELD_GET directly. - shrink function header to one line where it fits. - update scale table values arrangement - pow-of-two per line - rename j to have a proper meaning. - invert if (st->offsets[chan->channel] != val) and drop next lines indentation. - drop whitespace from * val = ... (altough checkpatch complains about it) - drop comma in the terminator lines for ext_info. - fix inconsistency between chip_info structures. - use devm_mutex_init - return -ENOENT on max_cnt check. - check both val and val2 for negative before converting to unsigned. - remove val2 where not used. - use dev_info() instead of dev_warn() - add spaces after { and before } in ad485x_scale_table drivers/iio/adc/Kconfig | 12 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad485x.c | 1094 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 1107 insertions(+) create mode 100644 drivers/iio/adc/ad485x.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index f60fe85a30d5..83f55229d731 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -36,6 +36,18 @@ config AD4130 To compile this driver as a module, choose M here: the module will be called ad4130. +config AD485X + tristate "Analog Device AD485x DAS Driver" + depends on SPI + select REGMAP_SPI + select IIO_BACKEND + help + Say yes here to build support for Analog Devices AD485x high speed + data acquisition system (DAS). + + To compile this driver as a module, choose M here: the module will be + called ad485x. + config AD7091R tristate diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index d370e066544e..26c1670c8913 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_AB8500_GPADC) += ab8500-gpadc.o obj-$(CONFIG_AD_SIGMA_DELTA) += ad_sigma_delta.o obj-$(CONFIG_AD4130) += ad4130.o +obj-$(CONFIG_AD485X) += ad485x.o obj-$(CONFIG_AD7091R) += ad7091r-base.o obj-$(CONFIG_AD7091R5) += ad7091r5.o obj-$(CONFIG_AD7091R8) += ad7091r8.o diff --git a/drivers/iio/adc/ad485x.c b/drivers/iio/adc/ad485x.c new file mode 100644 index 000000000000..faa10d56a791 --- /dev/null +++ b/drivers/iio/adc/ad485x.c @@ -0,0 +1,1094 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Analog Devices AD485x DAS driver + * + * Copyright 2024 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#define AD485X_REG_INTERFACE_CONFIG_A 0x00 +#define AD485X_REG_INTERFACE_CONFIG_B 0x01 +#define AD485X_REG_PRODUCT_ID_L 0x04 +#define AD485X_REG_PRODUCT_ID_H 0x05 +#define AD485X_REG_DEVICE_CTRL 0x25 +#define AD485X_REG_PACKET 0x26 + +#define AD485X_REG_CH_CONFIG_BASE 0x2A +#define AD485X_REG_CHX_SOFTSPAN(ch) ((0x12 * (ch)) + AD485X_REG_CH_CONFIG_BASE) +#define AD485X_REG_CHX_OFFSET(ch) (AD485X_REG_CHX_SOFTSPAN(ch) + 0x01) +#define AD485X_REG_CHX_OFFSET_LSB(ch) AD485X_REG_CHX_OFFSET(ch) +#define AD485X_REG_CHX_OFFSET_MID(ch) (AD485X_REG_CHX_OFFSET_LSB(ch) + 0x01) +#define AD485X_REG_CHX_OFFSET_MSB(ch) (AD485X_REG_CHX_OFFSET_MID(ch) + 0x01) +#define AD485X_REG_CHX_GAIN(ch) (AD485X_REG_CHX_OFFSET(ch) + 0x03) +#define AD485X_REG_CHX_GAIN_LSB(ch) AD485X_REG_CHX_GAIN(ch) +#define AD485X_REG_CHX_GAIN_MSB(ch) (AD485X_REG_CHX_GAIN(ch) + 0x01) +#define AD485X_REG_CHX_PHASE(ch) (AD485X_REG_CHX_GAIN(ch) + 0x02) +#define AD485X_REG_CHX_PHASE_LSB(ch) AD485X_REG_CHX_PHASE(ch) +#define AD485X_REG_CHX_PHASE_MSB(ch) (AD485X_REG_CHX_PHASE_LSB(ch) + 0x01) + +#define AD485X_REG_TESTPAT_0(c) (0x38 + (c) * 0x12) +#define AD485X_REG_TESTPAT_1(c) (0x39 + (c) * 0x12) +#define AD485X_REG_TESTPAT_2(c) (0x3A + (c) * 0x12) +#define AD485X_REG_TESTPAT_3(c) (0x3B + (c) * 0x12) + +#define AD485X_SW_RESET (BIT(7) | BIT(0)) +#define AD485X_SDO_ENABLE BIT(4) +#define AD485X_SINGLE_INSTRUCTION BIT(7) +#define AD485X_ECHO_CLOCK_MODE BIT(0) + +#define AD485X_PACKET_FORMAT_0 0 +#define AD485X_PACKET_FORMAT_1 1 +#define AD485X_PACKET_FORMAT_MASK GENMASK(1, 0) +#define AD485X_OS_EN BIT(7) + +#define AD485X_TEST_PAT BIT(2) + +#define AD4858_PACKET_SIZE_20 0 +#define AD4858_PACKET_SIZE_24 1 +#define AD4858_PACKET_SIZE_32 2 + +#define AD4857_PACKET_SIZE_16 0 +#define AD4857_PACKET_SIZE_24 1 + +#define AD485X_TESTPAT_0_DEFAULT 0x2A +#define AD485X_TESTPAT_1_DEFAULT 0x3C +#define AD485X_TESTPAT_2_DEFAULT 0xCE +#define AD485X_TESTPAT_3_DEFAULT(c) (0x0A + (0x10 * (c))) + +#define AD485X_SOFTSPAN_0V_2V5 0 +#define AD485X_SOFTSPAN_N2V5_2V5 1 +#define AD485X_SOFTSPAN_0V_5V 2 +#define AD485X_SOFTSPAN_N5V_5V 3 +#define AD485X_SOFTSPAN_0V_6V25 4 +#define AD485X_SOFTSPAN_N6V25_6V25 5 +#define AD485X_SOFTSPAN_0V_10V 6 +#define AD485X_SOFTSPAN_N10V_10V 7 +#define AD485X_SOFTSPAN_0V_12V5 8 +#define AD485X_SOFTSPAN_N12V5_12V5 9 +#define AD485X_SOFTSPAN_0V_20V 10 +#define AD485X_SOFTSPAN_N20V_20V 11 +#define AD485X_SOFTSPAN_0V_25V 12 +#define AD485X_SOFTSPAN_N25V_25V 13 +#define AD485X_SOFTSPAN_0V_40V 14 +#define AD485X_SOFTSPAN_N40V_40V 15 + +#define AD485X_MAX_LANES 8 +#define AD485X_MAX_IODELAY 32 + +#define AD485X_T_CNVH_NS 40 + +#define AD4858_PROD_ID 0x60 +#define AD4857_PROD_ID 0x61 +#define AD4856_PROD_ID 0x62 +#define AD4855_PROD_ID 0x63 +#define AD4854_PROD_ID 0x64 +#define AD4853_PROD_ID 0x65 +#define AD4852_PROD_ID 0x66 +#define AD4851_PROD_ID 0x67 +#define AD4858I_PROD_ID 0x6F + +struct ad485x_chip_info { + const char *name; + unsigned int product_id; + const unsigned int (*scale_table)[2]; + int num_scales; + const int *offset_table; + int num_offset; + const struct iio_chan_spec *channels; + unsigned int num_channels; + unsigned long throughput; + unsigned int resolution; +}; + +struct ad485x_state { + struct spi_device *spi; + struct pwm_device *cnv; + struct iio_backend *back; + /* + * Synchronize access to members the of driver state, and ensure + * atomicity of consecutive regmap operations. + */ + struct mutex lock; + struct regmap *regmap; + const struct ad485x_chip_info *info; + struct gpio_desc *pd_gpio; + unsigned long sampling_freq; + unsigned int (*scales)[2]; + int *offsets; +}; + +static int ad485x_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int writeval, + unsigned int *readval) +{ + struct ad485x_state *st = iio_priv(indio_dev); + + if (readval) + return regmap_read(st->regmap, reg, readval); + + return regmap_write(st->regmap, reg, writeval); +} + +static int ad485x_set_sampling_freq(struct ad485x_state *st, unsigned int freq) +{ + struct pwm_state cnv_state = { + .duty_cycle = AD485X_T_CNVH_NS, + .enabled = true, + }; + int ret; + + freq = clamp(freq, 0, st->info->throughput); + + cnv_state.period = DIV_ROUND_CLOSEST_ULL(GIGA, freq); + + ret = pwm_apply_might_sleep(st->cnv, &cnv_state); + if (ret) + return ret; + + st->sampling_freq = freq; + + return 0; +} + +static int ad485x_setup(struct ad485x_state *st) +{ + unsigned int product_id; + int ret; + + ret = ad485x_set_sampling_freq(st, HZ_PER_MHZ); + if (ret) + return ret; + + ret = regmap_write(st->regmap, AD485X_REG_INTERFACE_CONFIG_A, + AD485X_SW_RESET); + if (ret) + return ret; + + ret = regmap_write(st->regmap, AD485X_REG_INTERFACE_CONFIG_B, + AD485X_SINGLE_INSTRUCTION); + if (ret) + return ret; + + ret = regmap_write(st->regmap, AD485X_REG_INTERFACE_CONFIG_A, + AD485X_SDO_ENABLE); + if (ret) + return ret; + + ret = regmap_read(st->regmap, AD485X_REG_PRODUCT_ID_L, &product_id); + if (ret) + return ret; + + if (product_id != st->info->product_id) + dev_info(&st->spi->dev, "Unknown product ID: 0x%02X\n", + product_id); + + ret = regmap_write(st->regmap, AD485X_REG_DEVICE_CTRL, + AD485X_ECHO_CLOCK_MODE); + if (ret) + return ret; + + return regmap_write(st->regmap, AD485X_REG_PACKET, 0); +} + +static int ad485x_find_opt(bool *field, u32 size, u32 *ret_start) +{ + unsigned int i, cnt = 0, max_cnt = 0, max_start = 0; + int start; + + for (i = 0, start = -1; i < size; i++) { + if (field[i] == 0) { + if (start == -1) + start = i; + cnt++; + } else { + if (cnt > max_cnt) { + max_cnt = cnt; + max_start = start; + } + start = -1; + cnt = 0; + } + } + + if (cnt > max_cnt) { + max_cnt = cnt; + max_start = start; + } + + if (!max_cnt) + return -ENOENT; + + *ret_start = max_start; + + return max_cnt; +} + +static int ad485x_calibrate(struct ad485x_state *st) +{ + unsigned int opt_delay, lane_num, delay, i, s, c; + enum iio_backend_interface_type interface_type; + bool pn_status[AD485X_MAX_LANES][AD485X_MAX_IODELAY]; + int ret; + + ret = iio_backend_interface_type_get(st->back, &interface_type); + if (ret) + return ret; + + if (interface_type == IIO_BACKEND_INTERFACE_CMOS) + lane_num = st->info->num_channels; + else + lane_num = 1; + + if (st->info->resolution == 16) { + ret = iio_backend_data_size_set(st->back, 24); + if (ret) + return ret; + + ret = regmap_write(st->regmap, AD485X_REG_PACKET, + AD485X_TEST_PAT | AD4857_PACKET_SIZE_24); + if (ret) + return ret; + } else { + ret = iio_backend_data_size_set(st->back, 32); + if (ret) + return ret; + + ret = regmap_write(st->regmap, AD485X_REG_PACKET, + AD485X_TEST_PAT | AD4858_PACKET_SIZE_32); + if (ret) + return ret; + } + + for (i = 0; i < st->info->num_channels; i++) { + ret = regmap_write(st->regmap, AD485X_REG_TESTPAT_0(i), + AD485X_TESTPAT_0_DEFAULT); + if (ret) + return ret; + + ret = regmap_write(st->regmap, AD485X_REG_TESTPAT_1(i), + AD485X_TESTPAT_1_DEFAULT); + if (ret) + return ret; + + ret = regmap_write(st->regmap, AD485X_REG_TESTPAT_2(i), + AD485X_TESTPAT_2_DEFAULT); + if (ret) + return ret; + + ret = regmap_write(st->regmap, AD485X_REG_TESTPAT_3(i), + AD485X_TESTPAT_3_DEFAULT(i)); + if (ret) + return ret; + + ret = iio_backend_chan_enable(st->back, i); + if (ret) + return ret; + } + + for (i = 0; i < lane_num; i++) { + for (delay = 0; delay < AD485X_MAX_IODELAY; delay++) { + ret = iio_backend_iodelay_set(st->back, i, delay); + if (ret) + return ret; + ret = iio_backend_chan_status(st->back, i, + &pn_status[i][delay]); + if (ret) + return ret; + } + } + + for (i = 0; i < lane_num; i++) { + c = ad485x_find_opt(&pn_status[i][0], AD485X_MAX_IODELAY, &s); + if (c < 0) + return c; + + opt_delay = s + c / 2; + ret = iio_backend_iodelay_set(st->back, i, opt_delay); + if (ret) + return ret; + } + + for (i = 0; i < st->info->num_channels; i++) { + ret = iio_backend_chan_disable(st->back, i); + if (ret) + return ret; + } + + ret = iio_backend_data_size_set(st->back, 20); + if (ret) + return ret; + + return regmap_write(st->regmap, AD485X_REG_PACKET, 0); +} + +static const char *const ad4858_packet_fmts[] = { + "20-bit", "24-bit", "32-bit", +}; + +static const char *const ad4857_packet_fmts[] = { + "16-bit", "24-bit", +}; + +static int ad485x_set_packet_format(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int format) +{ + struct ad485x_state *st = iio_priv(indio_dev); + unsigned int val; + int ret; + + if (chan->scan_type.realbits == 20) + switch (format) { + case 0: + val = 20; + break; + case 1: + val = 24; + break; + case 2: + val = 32; + break; + default: + return -EINVAL; + } + else if (chan->scan_type.realbits == 16) + switch (format) { + case 0: + val = 16; + break; + case 1: + val = 24; + break; + default: + return -EINVAL; + } + else + return -EINVAL; + + ret = iio_backend_data_size_set(st->back, val); + if (ret) + return ret; + + return regmap_update_bits(st->regmap, AD485X_REG_PACKET, + AD485X_PACKET_FORMAT_MASK, format); +} + +static int ad485x_get_packet_format(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad485x_state *st = iio_priv(indio_dev); + unsigned int format; + int ret; + + ret = regmap_read(st->regmap, AD485X_REG_PACKET, &format); + if (ret) + return ret; + + return FIELD_GET(AD485X_PACKET_FORMAT_MASK, format); +} + +static const struct iio_enum ad4858_packet_fmt = { + .items = ad4858_packet_fmts, + .num_items = ARRAY_SIZE(ad4858_packet_fmts), + .set = ad485x_set_packet_format, + .get = ad485x_get_packet_format, +}; + +static const struct iio_enum ad4857_packet_fmt = { + .items = ad4857_packet_fmts, + .num_items = ARRAY_SIZE(ad4857_packet_fmts), + .set = ad485x_set_packet_format, + .get = ad485x_get_packet_format, +}; + +static int ad485x_get_calibscale(struct ad485x_state *st, int ch, int *val, int *val2) +{ + unsigned int reg_val; + int gain; + int ret; + + guard(mutex)(&st->lock); + + ret = regmap_read(st->regmap, AD485X_REG_CHX_GAIN_MSB(ch), + ®_val); + if (ret) + return ret; + + gain = (reg_val & 0xFF) << 8; + + ret = regmap_read(st->regmap, AD485X_REG_CHX_GAIN_LSB(ch), + ®_val); + if (ret) + return ret; + + gain |= reg_val & 0xFF; + + *val = gain; + *val2 = 32768; + + return IIO_VAL_FRACTIONAL; +} + +static int ad485x_set_calibscale(struct ad485x_state *st, int ch, int val, + int val2) +{ + unsigned long long gain; + unsigned int reg_val; + int ret; + + if (val < 0 || val2 < 0) + return -EINVAL; + + gain = val * MICRO + val2; + gain = DIV_U64_ROUND_CLOSEST(gain * 32768, MICRO); + + reg_val = gain; + + guard(mutex)(&st->lock); + + ret = regmap_write(st->regmap, AD485X_REG_CHX_GAIN_MSB(ch), + reg_val >> 8); + if (ret) + return ret; + + return regmap_write(st->regmap, AD485X_REG_CHX_GAIN_LSB(ch), + reg_val & 0xFF); +} + +static int ad485x_get_calibbias(struct ad485x_state *st, int ch, int *val) +{ + unsigned int lsb, mid, msb; + int ret; + + guard(mutex)(&st->lock); + + ret = regmap_read(st->regmap, AD485X_REG_CHX_OFFSET_MSB(ch), + &msb); + if (ret) + return ret; + + ret = regmap_read(st->regmap, AD485X_REG_CHX_OFFSET_MID(ch), + &mid); + if (ret) + return ret; + + ret = regmap_read(st->regmap, AD485X_REG_CHX_OFFSET_LSB(ch), + &lsb); + if (ret) + return ret; + + if (st->info->resolution == 16) { + *val = msb << 8; + *val |= mid; + *val = sign_extend32(*val, 15); + } else { + *val = msb << 12; + *val |= mid << 4; + *val |= lsb >> 4; + *val = sign_extend32(*val, 19); + } + + return IIO_VAL_INT; +} + +static int ad485x_set_calibbias(struct ad485x_state *st, int ch, int val) +{ + u8 buf[3] = { 0 }; + int ret; + + if (val < 0) + return -EINVAL; + + if (st->info->resolution == 16) + put_unaligned_be16(val, buf); + else + put_unaligned_be24(val << 4, buf); + + guard(mutex)(&st->lock); + + ret = regmap_write(st->regmap, AD485X_REG_CHX_OFFSET_LSB(ch), buf[2]); + if (ret) + return ret; + + ret = regmap_write(st->regmap, AD485X_REG_CHX_OFFSET_MID(ch), buf[1]); + if (ret) + return ret; + + return regmap_write(st->regmap, AD485X_REG_CHX_OFFSET_MSB(ch), buf[0]); +} + +static const unsigned int ad485x_scale_table[][2] = { + { 2500, 0x0 }, + { 5000, 0x1 }, + { 5000, 0x2 }, + { 10000, 0x3 }, + { 6250, 0x04 }, + { 12500, 0x5 }, + { 10000, 0x6 }, + { 20000, 0x7 }, + { 12500, 0x8 }, + { 25000, 0x9 }, + { 20000, 0xA }, + { 40000, 0xB }, + { 25000, 0xC }, + { 50000, 0xD }, + { 40000, 0xE }, + { 80000, 0xF }, +}; + +static const int ad4857_offset_table[] = { + 0, -32768, +}; + +static const int ad4858_offset_table[] = { + 0, -524288, +}; + +static const unsigned int ad485x_scale_avail[] = { + 2500, 5000, 10000, 6250, 12500, 20000, 25000, 40000, 50000, 80000, +}; + +static void __ad485x_get_scale(struct ad485x_state *st, int scale_tbl, + unsigned int *val, unsigned int *val2) +{ + const struct ad485x_chip_info *info = st->info; + const struct iio_chan_spec *chan = &info->channels[0]; + unsigned int tmp; + + tmp = (scale_tbl * 1000000ULL) >> chan->scan_type.realbits; + *val = tmp / 1000000; + *val2 = tmp % 1000000; +} + +static int ad485x_set_scale(struct ad485x_state *st, + const struct iio_chan_spec *chan, int val, int val2) +{ + const struct ad485x_chip_info *info = st->info; + unsigned int scale_val[2]; + unsigned int i; + bool single_ended = false; + + for (i = 0; i < info->num_scales; i++) { + __ad485x_get_scale(st, info->scale_table[i][0], + &scale_val[0], &scale_val[1]); + if (scale_val[0] != val || scale_val[1] != val2) + continue; + + /* + * Adjust the softspan value (differential or single ended) + * based on the scale value selected and current offset of + * the channel. + * + * If the offset is 0 then continue iterations until finding + * the next matching scale value which always corresponds to + * the single ended mode. + */ + if (!st->offsets[chan->channel] && !single_ended) { + single_ended = true; + continue; + } + + return regmap_write(st->regmap, + AD485X_REG_CHX_SOFTSPAN(chan->channel), + info->scale_table[i][1]); + } + + return -EINVAL; +} + +static int ad485x_get_scale(struct ad485x_state *st, + const struct iio_chan_spec *chan, int *val, + int *val2) +{ + const struct ad485x_chip_info *info = st->info; + unsigned int i, softspan_val; + int ret; + + ret = regmap_read(st->regmap, AD485X_REG_CHX_SOFTSPAN(chan->channel), + &softspan_val); + if (ret) + return ret; + + for (i = 0; i < info->num_scales; i++) { + if (softspan_val == info->scale_table[i][1]) + break; + } + + if (i == info->num_scales) + return -EIO; + + __ad485x_get_scale(st, info->scale_table[i][0], val, val2); + + return IIO_VAL_INT_PLUS_MICRO; +} + +static int ad485x_set_offset(struct ad485x_state *st, + const struct iio_chan_spec *chan, int val) +{ + guard(mutex)(&st->lock); + + if (val != st->offsets[chan->channel]) + return 0; + + st->offsets[chan->channel] = val; + /* Restore to the default range if offset changes */ + if (st->offsets[chan->channel]) + return regmap_write(st->regmap, + AD485X_REG_CHX_SOFTSPAN(chan->channel), + AD485X_SOFTSPAN_N40V_40V); + return regmap_write(st->regmap, + AD485X_REG_CHX_SOFTSPAN(chan->channel), + AD485X_SOFTSPAN_0V_40V); +} + +static int ad485x_scale_offset_fill(struct ad485x_state *st) +{ + unsigned int i, val1, val2; + + st->offsets = devm_kcalloc(&st->spi->dev, st->info->num_channels, + sizeof(*st->offsets), GFP_KERNEL); + if (!st->offsets) + return -ENOMEM; + + st->scales = devm_kmalloc_array(&st->spi->dev, ARRAY_SIZE(ad485x_scale_avail), + sizeof(*st->scales), GFP_KERNEL); + if (!st->scales) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(ad485x_scale_avail); i++) { + __ad485x_get_scale(st, ad485x_scale_avail[i], &val1, &val2); + st->scales[i][0] = val1; + st->scales[i][1] = val2; + } + + return 0; +} + +static int ad485x_read_raw(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + int *val, int *val2, long info) +{ + struct ad485x_state *st = iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: + *val = st->sampling_freq; + return IIO_VAL_INT; + case IIO_CHAN_INFO_CALIBSCALE: + return ad485x_get_calibscale(st, chan->channel, val, val2); + case IIO_CHAN_INFO_SCALE: + return ad485x_get_scale(st, chan, val, val2); + case IIO_CHAN_INFO_CALIBBIAS: + return ad485x_get_calibbias(st, chan->channel, val); + case IIO_CHAN_INFO_OFFSET: + scoped_guard(mutex, &st->lock) + *val = st->offsets[chan->channel]; + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int ad485x_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) +{ + struct ad485x_state *st = iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: + return ad485x_set_sampling_freq(st, val); + case IIO_CHAN_INFO_SCALE: + return ad485x_set_scale(st, chan, val, val2); + case IIO_CHAN_INFO_CALIBSCALE: + return ad485x_set_calibscale(st, chan->channel, val, val2); + case IIO_CHAN_INFO_CALIBBIAS: + return ad485x_set_calibbias(st, chan->channel, val); + case IIO_CHAN_INFO_OFFSET: + return ad485x_set_offset(st, chan, val); + default: + return -EINVAL; + } +} + +static int ad485x_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + struct ad485x_state *st = iio_priv(indio_dev); + unsigned int c; + int ret; + + for (c = 0; c < st->info->num_channels; c++) { + if (test_bit(c, scan_mask)) + ret = iio_backend_chan_enable(st->back, c); + else + ret = iio_backend_chan_disable(st->back, c); + if (ret) + return ret; + } + + return 0; +} + +static int ad485x_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) +{ + struct ad485x_state *st = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_SCALE: + *vals = (const int *)st->scales; + *type = IIO_VAL_INT_PLUS_MICRO; + /* Values are stored in a 2D matrix */ + *length = ARRAY_SIZE(ad485x_scale_avail) * 2; + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_OFFSET: + *vals = st->info->offset_table; + *type = IIO_VAL_INT; + *length = st->info->num_offset; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + +#define AD485X_IIO_CHANNEL(index, real, storage, info) \ +{ \ + .type = IIO_VOLTAGE, \ + .ext_info = info, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) | \ + BIT(IIO_CHAN_INFO_CALIBBIAS) | \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_OFFSET), \ + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_shared_by_type_available = \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_OFFSET), \ + .indexed = 1, \ + .channel = index, \ + .scan_index = index, \ + .scan_type = { \ + .sign = 's', \ + .realbits = real, \ + .storagebits = storage, \ + }, \ +} + +static struct iio_chan_spec_ext_info ad4858_ext_info[] = { + IIO_ENUM("packet_format", IIO_SHARED_BY_ALL, &ad4858_packet_fmt), + IIO_ENUM_AVAILABLE("packet_format", + IIO_SHARED_BY_ALL, &ad4858_packet_fmt), + {} +}; + +static struct iio_chan_spec_ext_info ad4857_ext_info[] = { + IIO_ENUM("packet_format", IIO_SHARED_BY_ALL, &ad4857_packet_fmt), + IIO_ENUM_AVAILABLE("packet_format", + IIO_SHARED_BY_ALL, &ad4857_packet_fmt), + {} +}; + +static const struct iio_chan_spec ad4858_channels[] = { + AD485X_IIO_CHANNEL(0, 20, 32, ad4858_ext_info), + AD485X_IIO_CHANNEL(1, 20, 32, ad4858_ext_info), + AD485X_IIO_CHANNEL(2, 20, 32, ad4858_ext_info), + AD485X_IIO_CHANNEL(3, 20, 32, ad4858_ext_info), + AD485X_IIO_CHANNEL(4, 20, 32, ad4858_ext_info), + AD485X_IIO_CHANNEL(5, 20, 32, ad4858_ext_info), + AD485X_IIO_CHANNEL(6, 20, 32, ad4858_ext_info), + AD485X_IIO_CHANNEL(7, 20, 32, ad4858_ext_info), +}; + +static const struct iio_chan_spec ad4857_channels[] = { + AD485X_IIO_CHANNEL(0, 16, 16, ad4857_ext_info), + AD485X_IIO_CHANNEL(1, 16, 16, ad4857_ext_info), + AD485X_IIO_CHANNEL(2, 16, 16, ad4857_ext_info), + AD485X_IIO_CHANNEL(3, 16, 16, ad4857_ext_info), + AD485X_IIO_CHANNEL(4, 16, 16, ad4857_ext_info), + AD485X_IIO_CHANNEL(5, 16, 16, ad4857_ext_info), + AD485X_IIO_CHANNEL(6, 16, 16, ad4857_ext_info), + AD485X_IIO_CHANNEL(7, 16, 16, ad4857_ext_info), +}; + +static const struct ad485x_chip_info ad4858_info = { + .name = "ad4858", + .product_id = AD4858_PROD_ID, + .scale_table = ad485x_scale_table, + .num_scales = ARRAY_SIZE(ad485x_scale_table), + .offset_table = ad4858_offset_table, + .num_offset = ARRAY_SIZE(ad4858_offset_table), + .channels = ad4858_channels, + .num_channels = ARRAY_SIZE(ad4858_channels), + .throughput = 1 * MEGA, + .resolution = 20, +}; + +static const struct ad485x_chip_info ad4857_info = { + .name = "ad4857", + .product_id = AD4857_PROD_ID, + .scale_table = ad485x_scale_table, + .num_scales = ARRAY_SIZE(ad485x_scale_table), + .offset_table = ad4857_offset_table, + .num_offset = ARRAY_SIZE(ad4857_offset_table), + .channels = ad4857_channels, + .num_channels = ARRAY_SIZE(ad4857_channels), + .throughput = 1 * MEGA, + .resolution = 16, +}; + +static const struct ad485x_chip_info ad4856_info = { + .name = "ad4856", + .product_id = AD4856_PROD_ID, + .scale_table = ad485x_scale_table, + .num_scales = ARRAY_SIZE(ad485x_scale_table), + .offset_table = ad4858_offset_table, + .num_offset = ARRAY_SIZE(ad4858_offset_table), + .channels = ad4858_channels, + .num_channels = ARRAY_SIZE(ad4858_channels), + .throughput = 250 * KILO, + .resolution = 20, +}; + +static const struct ad485x_chip_info ad4855_info = { + .name = "ad4855", + .product_id = AD4855_PROD_ID, + .scale_table = ad485x_scale_table, + .num_scales = ARRAY_SIZE(ad485x_scale_table), + .offset_table = ad4857_offset_table, + .num_offset = ARRAY_SIZE(ad4857_offset_table), + .channels = ad4857_channels, + .num_channels = ARRAY_SIZE(ad4857_channels), + .throughput = 250 * KILO, + .resolution = 16, +}; + +static const struct ad485x_chip_info ad4854_info = { + .name = "ad4854", + .product_id = AD4854_PROD_ID, + .scale_table = ad485x_scale_table, + .num_scales = ARRAY_SIZE(ad485x_scale_table), + .offset_table = ad4858_offset_table, + .num_offset = ARRAY_SIZE(ad4858_offset_table), + .channels = ad4858_channels, + .num_channels = ARRAY_SIZE(ad4858_channels), + .throughput = 1 * MEGA, + .resolution = 20, +}; + +static const struct ad485x_chip_info ad4853_info = { + .name = "ad4853", + .product_id = AD4853_PROD_ID, + .scale_table = ad485x_scale_table, + .num_scales = ARRAY_SIZE(ad485x_scale_table), + .offset_table = ad4857_offset_table, + .num_offset = ARRAY_SIZE(ad4857_offset_table), + .channels = ad4857_channels, + .num_channels = ARRAY_SIZE(ad4857_channels), + .throughput = 1 * MEGA, + .resolution = 16, +}; + +static const struct ad485x_chip_info ad4852_info = { + .name = "ad4852", + .product_id = AD4852_PROD_ID, + .scale_table = ad485x_scale_table, + .num_scales = ARRAY_SIZE(ad485x_scale_table), + .offset_table = ad4858_offset_table, + .num_offset = ARRAY_SIZE(ad4858_offset_table), + .channels = ad4858_channels, + .num_channels = ARRAY_SIZE(ad4858_channels), + .throughput = 250 * KILO, + .resolution = 20, +}; + +static const struct ad485x_chip_info ad4851_info = { + .name = "ad4851", + .product_id = AD4851_PROD_ID, + .scale_table = ad485x_scale_table, + .num_scales = ARRAY_SIZE(ad485x_scale_table), + .offset_table = ad4857_offset_table, + .num_offset = ARRAY_SIZE(ad4857_offset_table), + .channels = ad4857_channels, + .num_channels = ARRAY_SIZE(ad4857_channels), + .throughput = 250 * KILO, + .resolution = 16, +}; + +static const struct ad485x_chip_info ad4858i_info = { + .name = "ad4858i", + .product_id = AD4858I_PROD_ID, + .scale_table = ad485x_scale_table, + .num_scales = ARRAY_SIZE(ad485x_scale_table), + .offset_table = ad4858_offset_table, + .num_offset = ARRAY_SIZE(ad4858_offset_table), + .channels = ad4858_channels, + .num_channels = ARRAY_SIZE(ad4858_channels), + .throughput = 1 * MEGA, + .resolution = 20, +}; + +static const struct iio_info ad485x_info = { + .debugfs_reg_access = ad485x_reg_access, + .read_raw = ad485x_read_raw, + .write_raw = ad485x_write_raw, + .update_scan_mode = ad485x_update_scan_mode, + .read_avail = ad485x_read_avail, +}; + +static const struct regmap_config regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .read_flag_mask = BIT(7), +}; + +static const char * const ad485x_power_supplies[] = { + "vcc", "vdd", "vee", "vio", +}; + +static int ad485x_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct ad485x_state *st; + int ret; + + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st = iio_priv(indio_dev); + st->spi = spi; + + ret = devm_mutex_init(&spi->dev, &st->lock); + if (ret) + return ret; + + ret = devm_regulator_bulk_get_enable(&spi->dev, + ARRAY_SIZE(ad485x_power_supplies), + ad485x_power_supplies); + if (ret) + return dev_err_probe(&spi->dev, ret, + "failed to get and enable supplies\n"); + + ret = devm_regulator_get_enable_optional(&spi->dev, "vddh"); + if (ret < 0 && ret != -ENODEV) + return dev_err_probe(&spi->dev, ret, "failed to get vddh voltage\n"); + + ret = devm_regulator_get_enable_optional(&spi->dev, "vddl"); + if (ret < 0 && ret != -ENODEV) + return dev_err_probe(&spi->dev, ret, "failed to get vddl voltage\n"); + + st->pd_gpio = devm_gpiod_get_optional(&spi->dev, "pd", GPIOD_OUT_LOW); + if (IS_ERR(st->pd_gpio)) + return dev_err_probe(&spi->dev, PTR_ERR(st->pd_gpio), + "Error on requesting pd GPIO\n"); + + st->cnv = devm_pwm_get(&spi->dev, NULL); + if (IS_ERR(st->cnv)) + return PTR_ERR(st->cnv); + + st->info = spi_get_device_match_data(spi); + if (!st->info) + return -ENODEV; + + st->regmap = devm_regmap_init_spi(spi, ®map_config); + if (IS_ERR(st->regmap)) + return PTR_ERR(st->regmap); + + ret = ad485x_scale_offset_fill(st); + if (ret) + return ret; + + ret = ad485x_setup(st); + if (ret) + return ret; + + indio_dev->name = st->info->name; + indio_dev->channels = st->info->channels; + indio_dev->num_channels = st->info->num_channels; + indio_dev->info = &ad485x_info; + + st->back = devm_iio_backend_get(&spi->dev, NULL); + if (IS_ERR(st->back)) + return PTR_ERR(st->back); + + ret = devm_iio_backend_request_buffer(&spi->dev, st->back, indio_dev); + if (ret) + return ret; + + ret = devm_iio_backend_enable(&spi->dev, st->back); + if (ret) + return ret; + + ret = ad485x_calibrate(st); + if (ret) + return ret; + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static const struct of_device_id ad485x_of_match[] = { + { .compatible = "adi,ad4858", .data = &ad4858_info, }, + { .compatible = "adi,ad4857", .data = &ad4857_info, }, + { .compatible = "adi,ad4856", .data = &ad4856_info, }, + { .compatible = "adi,ad4855", .data = &ad4855_info, }, + { .compatible = "adi,ad4854", .data = &ad4854_info, }, + { .compatible = "adi,ad4853", .data = &ad4853_info, }, + { .compatible = "adi,ad4852", .data = &ad4852_info, }, + { .compatible = "adi,ad4851", .data = &ad4851_info, }, + { .compatible = "adi,ad4858i", .data = &ad4858i_info, }, + {} +}; + +static const struct spi_device_id ad485x_spi_id[] = { + { "ad4858", (kernel_ulong_t)&ad4858_info }, + { "ad4857", (kernel_ulong_t)&ad4857_info }, + { "ad4856", (kernel_ulong_t)&ad4856_info }, + { "ad4855", (kernel_ulong_t)&ad4855_info }, + { "ad4854", (kernel_ulong_t)&ad4854_info }, + { "ad4853", (kernel_ulong_t)&ad4853_info }, + { "ad4852", (kernel_ulong_t)&ad4852_info }, + { "ad4851", (kernel_ulong_t)&ad4851_info }, + { "ad4858i", (kernel_ulong_t)&ad4858i_info }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad485x_spi_id); + +static struct spi_driver ad485x_driver = { + .probe = ad485x_probe, + .driver = { + .name = "ad485x", + .of_match_table = ad485x_of_match, + }, + .id_table = ad485x_spi_id, +}; +module_spi_driver(ad485x_driver); + +MODULE_AUTHOR("Sergiu Cuciurean "); +MODULE_AUTHOR("Dragos Bogdan "); +MODULE_AUTHOR("Antoniu Miclaus "); +MODULE_DESCRIPTION("Analog Devices AD485x DAS driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(IIO_BACKEND); From patchwork Fri Oct 4 14:07:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Miclaus, Antoniu" X-Patchwork-Id: 13822456 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABB8B217304; Fri, 4 Oct 2024 14:13:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728051194; cv=none; b=bMFxi8yVcD0AUYlzv7PoFMsvcfNwlCZ5vCe66YzNoQq2eth7aDP5I1Bto28B/wHg/4NG1wLgBCTJixBweLu0ROTQ5hNgCLKpLZYrDUALneSnTSf3lL8/qgzcbjXIxHLujom8sqGo2FmfA69Nwlx/88ClrZ2Eg1YYvCUoyUfRk+8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728051194; c=relaxed/simple; bh=uAq7LOKTJTM0nxXXvyUdoiwg8irtm++qAYb+DvlExws=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=U0Eg7D2fE1+tyDt3gWiJU9tPGNWGeo7IureK6zNIVBd99AnzHYLhXKBGAiiZiwyXTvEnh2wuvtlm9ao/LHT+EOLYdOmw4nf2n1G8Z9Z02qdZjA3CCTFyuk2HCZowwMZAhdKpOjzK7MC9S7uG6pLeq+0X4JSeUMyNh2WUVbx1ljw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=feWtulwa; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="feWtulwa" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 494C48Ad018577; Fri, 4 Oct 2024 10:12:47 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=0Ns6c KpXekNU/LVxVd6eQphUEDq2bnU24uk5tmxzSMQ=; b=feWtulwaqA4FLlp7H5gQQ HneJ3ZeDnfXhFN2ra+Xw8Dxrzm1g1IZ+WRrGWxDh/a0sj40BISpIem/YTlyTNRO/ 6/r9lpcMmPkvHTRMwV3+DETlZqs7Cs68euRd14OV3+nFdhhJQ2Agtq+md50X8vWo s/Q0StOBYbnoQuwclNNY1SV/Loc5j540ck6YQ7HIq0G5yx8/6m5T2ob/1M4n89C6 bm58apYgEzdC8GuHsrWrNHOtJX9Sxq7iOD8H9VFhn3xc1YGyKs28EK0SV0w+OaM7 D1A7AM5TiYXDcl5jAswl0FtD3yyKqHWLEdcuat6yLKolfA0/CxdPu1VdkKYK8cir w== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 422043kx57-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Oct 2024 10:12:46 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 494ECj6P002749 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 4 Oct 2024 10:12:45 -0400 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 4 Oct 2024 10:12:45 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Fri, 4 Oct 2024 10:12:45 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Fri, 4 Oct 2024 10:12:45 -0400 Received: from amiclaus-VirtualBox.ad.analog.com (AMICLAUS-L02.ad.analog.com [10.48.65.173]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 494EAps7001773; Fri, 4 Oct 2024 10:12:37 -0400 From: Antoniu Miclaus To: Jonathan Cameron , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nuno Sa , Olivier Moysan , =?utf-8?q?Uwe_Kleine-K=C3=B6ni?= =?utf-8?q?g?= , Andy Shevchenko , David Lechner , Marcelo Schmitt , AngeloGioacchino Del Regno , "Mike Looijmans" , Dumitru Ceclan , =?utf-8?q?Jo=C3=A3o_Paulo_Gon?= =?utf-8?q?=C3=A7alves?= , Antoniu Miclaus , Alisa-Dariana Roman , Sergiu Cuciurean , Dragos Bogdan , , , , Subject: [PATCH v2 7/7] Documentation: ABI: testing: ad485x: add ABI docs Date: Fri, 4 Oct 2024 17:07:56 +0300 Message-ID: <20241004140922.233939-7-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241004140922.233939-1-antoniu.miclaus@analog.com> References: <20241004140922.233939-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: W_s_ac2Gz9o3ctJLcwc1ZsfxpmcR588x X-Proofpoint-GUID: W_s_ac2Gz9o3ctJLcwc1ZsfxpmcR588x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 suspectscore=0 mlxlogscore=999 mlxscore=0 bulkscore=0 impostorscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040099 Add documentation for the packet size. Signed-off-by: Antoniu Miclaus --- changes in v2: - improve description for packet_format - add kernel version .../ABI/testing/sysfs-bus-iio-adc-ad485x | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-adc-ad485x diff --git a/Documentation/ABI/testing/sysfs-bus-iio-adc-ad485x b/Documentation/ABI/testing/sysfs-bus-iio-adc-ad485x new file mode 100644 index 000000000000..5d69a8d30383 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-adc-ad485x @@ -0,0 +1,16 @@ +What: /sys/bus/iio/devices/iio:deviceX/packet_format_available +KernelVersion: 6.13 +Contact: linux-iio@vger.kernel.org +Description: + Packet sizes on the CMOS or LVDS conversion data output bus. + Reading this returns the valid values that can be written to the + packet_format. + +What: /sys/bus/iio/devices/iio:deviceX/packet_format +KernelVersion: 6.13 +Contact: linux-iio@vger.kernel.org +Description: + This attribute configures the frame size on conversion data + output bus. See packet_format_available for available sizes + based on the device used. + Reading returns the actual size used.