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List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add peric1, misc and hsi0/1 clock definitions. - CMU_PERIC1 for USI, IC2 and I3C - CMU_MISC for MISC, GIC and OTP - HSI0 for PCIE - HSI1 for USB and MMC Signed-off-by: Sunyeal Hong --- .../clock/samsung,exynosautov920.h | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h index c720f344b6bf..0c681f2ba3d0 100644 --- a/include/dt-bindings/clock/samsung,exynosautov920.h +++ b/include/dt-bindings/clock/samsung,exynosautov920.h @@ -160,6 +160,7 @@ #define DOUT_CLKCMU_SNW_NOC 144 #define DOUT_CLKCMU_SSP_NOC 145 #define DOUT_CLKCMU_TAA_NOC 146 +#define DOUT_TCXO_DIV2 147 /* CMU_PERIC0 */ #define CLK_MOUT_PERIC0_IP_USER 1 @@ -188,4 +189,50 @@ #define CLK_DOUT_PERIC0_USI_I2C 23 #define CLK_DOUT_PERIC0_I3C 24 +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_IP_USER 1 +#define CLK_MOUT_PERIC1_NOC_USER 2 +#define CLK_MOUT_PERIC1_USI09_USI 3 +#define CLK_MOUT_PERIC1_USI10_USI 4 +#define CLK_MOUT_PERIC1_USI11_USI 5 +#define CLK_MOUT_PERIC1_USI12_USI 6 +#define CLK_MOUT_PERIC1_USI13_USI 7 +#define CLK_MOUT_PERIC1_USI14_USI 8 +#define CLK_MOUT_PERIC1_USI15_USI 9 +#define CLK_MOUT_PERIC1_USI16_USI 10 +#define CLK_MOUT_PERIC1_USI17_USI 11 +#define CLK_MOUT_PERIC1_USI_I2C 12 +#define CLK_MOUT_PERIC1_I3C 13 + +#define CLK_DOUT_PERIC1_USI09_USI 14 +#define CLK_DOUT_PERIC1_USI10_USI 15 +#define CLK_DOUT_PERIC1_USI11_USI 16 +#define CLK_DOUT_PERIC1_USI12_USI 17 +#define CLK_DOUT_PERIC1_USI13_USI 18 +#define CLK_DOUT_PERIC1_USI14_USI 19 +#define CLK_DOUT_PERIC1_USI15_USI 20 +#define CLK_DOUT_PERIC1_USI16_USI 21 +#define CLK_DOUT_PERIC1_USI17_USI 22 +#define CLK_DOUT_PERIC1_USI_I2C 23 +#define CLK_DOUT_PERIC1_I3C 24 + +/* CMU_MISC */ +#define CLK_MOUT_MISC_NOC_USER 1 +#define CLK_MOUT_MISC_GIC 2 + +#define CLK_DOUT_MISC_OTP 3 +#define CLK_DOUT_MISC_NOCP 4 +#define CLK_DOUT_MISC_OSC_DIV2 5 + +/* CMU_HSI0 */ +#define CLK_MOUT_HSI0_NOC_USER 1 + +#define CLK_DOUT_HSI0_PCIE_APB 2 + +/* CMU_HSI1 */ +#define CLK_MOUT_HSI1_MMC_CARD_USER 1 +#define CLK_MOUT_HSI1_NOC_USER 2 +#define CLK_MOUT_HSI1_USBDRD_USER 3 +#define CLK_MOUT_HSI1_USBDRD 4 + #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */ From patchwork Mon Oct 7 07:13:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunyeal Hong X-Patchwork-Id: 13824271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9061ACFB440 for ; Mon, 7 Oct 2024 07:44:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; 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sfid-20241007_081351_129421_2848B1BC X-CRM114-Status: GOOD ( 16.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Register compatible and cmu_info data to support clocks. CMU_PERIC1, this provides clocks for USI09 ~ USI17, USI_I2C and USI_I3C. CMU_MISC, this provides clocks for MISC, GIC and OTP. CMU_HSI0, this provides clocks for PCIE. CMU_HSI1, this provides clocks for USB and MMC. Signed-off-by: Sunyeal Hong --- drivers/clk/samsung/clk-exynosautov920.c | 290 +++++++++++++++++++++++ 1 file changed, 290 insertions(+) diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c index f60f0a0c598d..f96998b0a864 100644 --- a/drivers/clk/samsung/clk-exynosautov920.c +++ b/drivers/clk/samsung/clk-exynosautov920.c @@ -19,6 +19,10 @@ /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1) #define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1) +#define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1) +#define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1) +#define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1) +#define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1) /* ---- CMU_TOP ------------------------------------------------------------ */ @@ -974,6 +978,8 @@ static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initcon "mout_shared5_pll", 1, 3, 0), FFACTOR(DOUT_SHARED5_DIV4, "dout_shared5_div4", "mout_shared5_pll", 1, 4, 0), + FFACTOR(DOUT_TCXO_DIV2, "dout_tcxo_div2", + "oscclk", 1, 2, 0), }; static const struct samsung_cmu_info top_cmu_info __initconst = { @@ -1139,6 +1145,277 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = { .clk_name = "noc", }; +/* ---- CMU_PERIC1 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIC1 (0x10C00000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x600 +#define PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER 0x610 +#define CLK_CON_MUX_MUX_CLK_PERIC1_I3C 0x1000 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x1004 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1008 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x100c +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI 0x1010 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI 0x1014 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI 0x1018 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI 0x101c +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI 0x1020 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI 0x1024 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1028 +#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI 0x1818 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI 0x181c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1828 + +static const unsigned long peric1_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, + CLK_CON_MUX_MUX_CLK_PERIC1_I3C, + CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, + CLK_CON_DIV_DIV_CLK_PERIC1_I3C, + CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, +}; + +/* List of parent clocks for Muxes in CMU_PERIC1 */ +PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" }; +PNAME(mout_peric1_noc_user_p) = { "oscclk", "dout_clkcmu_peric1_noc" }; +PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" }; + +static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user", + mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_NOC_USER, "mout_peric1_noc_user", + mout_peric1_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 4, 1), + /* USI09 ~ USI17 */ + MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI12_USI, "mout_peric1_usi12_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI13_USI, "mout_peric1_usi13_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI14_USI, "mout_peric1_usi14_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI15_USI, "mout_peric1_usi15_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI16_USI, "mout_peric1_usi16_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI17_USI, "mout_peric1_usi17_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, 0, 1), + /* USI_I2C */ + MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1), + /* USI_I3C */ + MUX(CLK_MOUT_PERIC1_I3C, "mout_peric1_i3c", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_I3C, 0, 1), +}; + +static const struct samsung_div_clock peric1_div_clks[] __initconst = { + /* USI09 ~ USI17 */ + DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi", + "mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi", + "mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi", + "mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi", + "mout_peric1_usi12_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI13_USI, "dout_peric1_usi13_usi", + "mout_peric1_usi13_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI14_USI, "dout_peric1_usi14_usi", + "mout_peric1_usi14_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI15_USI, "dout_peric1_usi15_usi", + "mout_peric1_usi15_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi", + "mout_peric1_usi16_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi", + "mout_peric1_usi17_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI, + 0, 4), + /* USI_I2C */ + DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c", + "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4), + /* USI_I3C */ + DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", + "mout_peric1_i3c", CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4), +}; + +static const struct samsung_cmu_info peric1_cmu_info __initconst = { + .mux_clks = peric1_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), + .div_clks = peric1_div_clks, + .nr_div_clks = ARRAY_SIZE(peric1_div_clks), + .nr_clk_ids = CLKS_NR_PERIC1, + .clk_regs = peric1_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), + .clk_name = "noc", +}; + +/* ---- CMU_MISC --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_MISC (0x10020000) */ +#define PLL_CON0_MUX_CLKCMU_MISC_NOC_USER 0x600 +#define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000 +#define CLK_CON_DIV_CLKCMU_OTP 0x1800 +#define CLK_CON_DIV_DIV_CLK_MISC_NOCP 0x1804 +#define CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2 0x1808 + +static const unsigned long misc_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, + CLK_CON_MUX_MUX_CLK_MISC_GIC, + CLK_CON_DIV_CLKCMU_OTP, + CLK_CON_DIV_DIV_CLK_MISC_NOCP, + CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2, +}; + +/* List of parent clocks for Muxes in CMU_MISC */ +PNAME(mout_misc_noc_user_p) = { "oscclk", "dout_clkcmu_misc_noc" }; +PNAME(mout_misc_gic_p) = { "dout_misc_nocp", "oscclk" }; + +static const struct samsung_mux_clock misc_mux_clks[] __initconst = { + MUX(CLK_MOUT_MISC_NOC_USER, "mout_misc_noc_user", + mout_misc_noc_user_p, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, 4, 1), + MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic", + mout_misc_gic_p, CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 1), +}; + +static const struct samsung_div_clock misc_div_clks[] __initconst = { + DIV(CLK_DOUT_MISC_NOCP, "dout_misc_nocp", + "mout_misc_noc_user", CLK_CON_DIV_DIV_CLK_MISC_NOCP, + 0, 3), +}; + +static const struct samsung_fixed_factor_clock misc_fixed_factor_clks[] __initconst = { + FFACTOR(CLK_DOUT_MISC_OTP, "dout_misc_otp", + "oscclk", 1, 10, 0), + FFACTOR(CLK_DOUT_MISC_OSC_DIV2, "dout_misc_osc_div2", + "oscclk", 1, 2, 0), +}; + +static const struct samsung_cmu_info misc_cmu_info __initconst = { + .mux_clks = misc_mux_clks, + .nr_mux_clks = ARRAY_SIZE(misc_mux_clks), + .div_clks = misc_div_clks, + .nr_div_clks = ARRAY_SIZE(misc_div_clks), + .fixed_factor_clks = misc_fixed_factor_clks, + .nr_fixed_factor_clks = ARRAY_SIZE(misc_fixed_factor_clks), + .nr_clk_ids = CLKS_NR_MISC, + .clk_regs = misc_clk_regs, + .nr_clk_regs = ARRAY_SIZE(misc_clk_regs), + .clk_name = "noc", +}; + +/* ---- CMU_HSI0 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_HSI0 (0x16000000) */ +#define PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER 0x600 +#define CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB 0x1800 + +static const unsigned long hsi0_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, + CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB, +}; + +/* List of parent clocks for Muxes in CMU_HSI0 */ +PNAME(mout_hsi0_noc_user_p) = { "oscclk", "dout_clkcmu_hsi0_noc" }; + +static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = { + MUX(CLK_MOUT_HSI0_NOC_USER, "mout_hsi0_noc_user", + mout_hsi0_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, 4, 1), +}; + +static const struct samsung_div_clock hsi0_div_clks[] __initconst = { + DIV(CLK_DOUT_HSI0_PCIE_APB, "dout_hsi0_pcie_apb", + "mout_hsi0_noc_user", CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB, + 0, 4), +}; + +static const struct samsung_cmu_info hsi0_cmu_info __initconst = { + .mux_clks = hsi0_mux_clks, + .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks), + .div_clks = hsi0_div_clks, + .nr_div_clks = ARRAY_SIZE(hsi0_div_clks), + .nr_clk_ids = CLKS_NR_HSI0, + .clk_regs = hsi0_clk_regs, + .nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs), + .clk_name = "noc", +}; + +/* ---- CMU_HSI1 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_HSI1 (0x16400000) */ +#define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER 0x600 +#define PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER 0x610 +#define PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER 0x620 +#define CLK_CON_MUX_MUX_CLK_HSI1_USBDRD 0x1000 + +static const unsigned long hsi1_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, + PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, + PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER, + CLK_CON_MUX_MUX_CLK_HSI1_USBDRD, +}; + +/* List of parent clocks for Muxes in CMU_HSI1 */ +PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"}; +PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" }; +PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "mout_clkcmu_hsi1_usbdrd" }; +PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" }; + +static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = { + MUX(CLK_MOUT_HSI1_MMC_CARD_USER, "mout_hsi1_mmc_card_user", + mout_hsi1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, 4, 1), + MUX(CLK_MOUT_HSI1_NOC_USER, "mout_hsi1_noc_user", + mout_hsi1_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, 4, 1), + MUX(CLK_MOUT_HSI1_USBDRD_USER, "mout_hsi1_usbdrd_user", + mout_hsi1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER, 4, 1), + MUX(CLK_MOUT_HSI1_USBDRD, "mout_hsi1_usbdrd", + mout_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLK_HSI1_USBDRD, 4, 1), +}; + +static const struct samsung_cmu_info hsi1_cmu_info __initconst = { + .mux_clks = hsi1_mux_clks, + .nr_mux_clks = ARRAY_SIZE(hsi1_mux_clks), + .nr_clk_ids = CLKS_NR_HSI1, + .clk_regs = hsi1_clk_regs, + .nr_clk_regs = ARRAY_SIZE(hsi1_clk_regs), + .clk_name = "noc", +}; + static int __init exynosautov920_cmu_probe(struct platform_device *pdev) { const struct samsung_cmu_info *info; @@ -1154,6 +1431,19 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = { { .compatible = "samsung,exynosautov920-cmu-peric0", .data = &peric0_cmu_info, + }, { + .compatible = "samsung,exynosautov920-cmu-peric1", + .data = &peric1_cmu_info, + }, { + .compatible = "samsung,exynosautov920-cmu-misc", + .data = &misc_cmu_info, + }, { + .compatible = "samsung,exynosautov920-cmu-hsi0", + .data = &hsi0_cmu_info, + }, { + .compatible = "samsung,exynosautov920-cmu-hsi1", + .data = &hsi1_cmu_info, + }, { }, { } }; From patchwork Mon Oct 7 07:13:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunyeal Hong X-Patchwork-Id: 13824282 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D171ECFB43F for ; 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Mon, 7 Oct 2024 07:13:38 +0000 (GMT) From: Sunyeal Hong To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sunyeal Hong Subject: [PATCH v1 3/3] arm64: dts: exynosautov920: add peric1, misc and hsi0/1 clock DT nodes Date: Mon, 7 Oct 2024 16:13:33 +0900 Message-ID: <20241007071333.3011125-4-sunyeal.hong@samsung.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241007071333.3011125-1-sunyeal.hong@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrHJsWRmVeSWpSXmKPExsWy7bCmqa5yF3O6wanXTBYP5m1js1iz9xyT xfUvz1kt5h85x2px/vwGdotNj6+xWnzsucdqcXnXHDaLGef3MVlcPOVq8X/PDnaLw2/aWS3+ XdvIYtG0bD2TA5/H+xut7B6bVnWyeWxeUu/Rt2UVo8fnTXIBrFHZNhmpiSmpRQqpecn5KZl5 6bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlAdyoplCXmlAKFAhKLi5X07WyK8ktL UhUy8otLbJVSC1JyCswL9IoTc4tL89L18lJLrAwNDIxMgQoTsjOmfHzOWHBWtGLOoTssDYyv BLoYOTkkBEwk5k2/x9LFyMUhJLCDUWLXp342COcTo8StS/ehMt8YJT7cOMYO0/K3fwUTRGIv o8SWI72sEM5HRonjPx4ydjFycLAJ6Er8+ecAEhcR2MMkseX8ErAOZoGzjBJ35ywAGyUskCBx 4/UqVhCbRUBVYmffaRYQm1fAXmLjiUlQ6+Qlrj8+ygRicwo4SDw7B7IApEZQ4uTMJ2D1zEA1 zVtnM4MskBCYyyFxor2DHeQKCQEXiVk75SDmCEu8Or4FaqaUxOd3e9kg7HyJydffMkH0NjBK XPvXzQyRsJdYdOYn2BxmAU2J9bv0IUYqSxy5BbWWT6Lj8F+oTbwSHW1CEI1qEp+uXIYaIiNx 7MQzKNtDYsqlPmjATWaUOH2uiWkCo8IsJN/MQvLNLITFCxiZVzGKpRYU56anFhsVmMCjODk/ dxMjOOFqeexgnP32g94hRiYOxkOMEhzMSiK8EWsY04V4UxIrq1KL8uOLSnNSiw8xmgLDeiKz lGhyPjDl55XEG5pYGpiYmRmaG5kamCuJ895rnZsiJJCeWJKanZpakFoE08fEwSnVwOSdKKp1 SjeEXyJZ9b/IR8/2GRuvb3yhW2pdtiggXD9mjb3nqaYmpmnrX/mHW2pf8nlfF6V9Tu3iU/Y3 YpVOZaWtnYdUb24JDpw43WDrZ728w/7vvvnLPs9+HLTtn9fyN1EzlbO15Kfte3k1x3/Hx63t TXPUts5kmxNx+uKWWaHsm+sCpn8o2JT4T+qS6/Kfb9MYE3+dn7L41SavBdq9vdq90R1TpklZ t22JvvKaw29Ny48DP1mFoqR2uRS9STh4/mf7iY7/6T6LKjdnTSt2WHS+1zX32zKP6/NrTRon p/OLZN6477BXbXXClaisP93MZnaTRedWP/lqNSW3b/+HfrOIyHf/le8mKE9Z9aL06AYlluKM REMt5qLiRAAgD1D4QQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOLMWRmVeSWpSXmKPExsWy7bCSvK5SF3O6weZlchYP5m1js1iz9xyT xfUvz1kt5h85x2px/vwGdotNj6+xWnzsucdqcXnXHDaLGef3MVlcPOVq8X/PDnaLw2/aWS3+ XdvIYtG0bD2TA5/H+xut7B6bVnWyeWxeUu/Rt2UVo8fnTXIBrFFcNimpOZllqUX6dglcGVM+ PmcsOCtaMefQHZYGxlcCXYycHBICJhJ/+1cwgdhCArsZJX5/VYKIy0hsbPjPDmELS9xvOcLa xcgFVPOeUeLl/odADRwcbAK6En/+OYDERQQOMUlM/PyUBcRhFrjMKHHs7mRmkG5hgTiJplcz WEBsFgFViZ19p8FsXgF7iY0nJkFtkJe4/vgo2BWcAg4Sz849ZARZIARUc/NDAkS5oMTJmU/A WpmBypu3zmaewCgwC0lqFpLUAkamVYySqQXFuem5xYYFRnmp5XrFibnFpXnpesn5uZsYwXGh pbWDcc+qD3qHGJk4GA8xSnAwK4nwRqxhTBfiTUmsrEotyo8vKs1JLT7EKM3BoiTO++11b4qQ QHpiSWp2ampBahFMlomDU6qBKW7Cw919s9+UKkwU7jx2dj1jU/IapX+1fw7wvdDsT9t/eYPP ldDZvvE/GQu/hVm/WPVaWvzQrC27xOU0eJYvKFqo0/Z9ZfhdpUX5V0PdwuM9r22ap8Ox5B3L 2TPCtny7n37z23zKl8tDbf+Z16Y5B56+Mah6t4Z9AuvTuVsy5u1p+75kt9Sswncv//c+Drv7 aMoLpxkHd7KszX1aXrNHoEtQ4nWs33d35r7555lab795XXGVU3mT9LzLazf5y3vlXs/0+M4Q 8dLKxdvggNzDo77F2kJXj09RXBQ9f8d/T5ZbyT9/ctRYHb7fNt18l3iM7U6r8APlM89brjkQ 8cZJ/GfaybVTbU9aFz5viGdPZxFSYinOSDTUYi4qTgQAIAa3IfoCAAA= X-CMS-MailID: 20241007071338epcas2p4361cff07030753a9c7c3e1589209a20d X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20241007071338epcas2p4361cff07030753a9c7c3e1589209a20d References: <20241007071333.3011125-1-sunyeal.hong@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241007_081351_150861_B1C43163 X-CRM114-Status: GOOD ( 14.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add cmu_peric1 for USI, I2C and I3C clocks respectively. Add cmu_misc for MISC, GIC and OTP clocks respectively. Add cmu_hsi0 for PCIE clocks respectively. Add cmu_hsi1 for USB and MMC clocks respectively. Signed-off-by: Sunyeal Hong --- .../arm64/boot/dts/exynos/exynosautov920.dtsi | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index 91882b37fdb3..c759134c909e 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -172,6 +172,17 @@ chipid@10000000 { reg = <0x10000000 0x24>; }; + cmu_misc: clock-controller@10020000 { + compatible = "samsung,exynosautov920-cmu-misc"; + reg = <0x10020000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_MISC_NOC>; + clock-names = "oscclk", + "noc"; + }; + gic: interrupt-controller@10400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -247,6 +258,19 @@ pwm: pwm@109b0000 { status = "disabled"; }; + cmu_peric1: clock-controller@10c00000 { + compatible = "samsung,exynosautov920-cmu-peric1"; + reg = <0x10c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_PERIC1_NOC>, + <&cmu_top DOUT_CLKCMU_PERIC1_IP>; + clock-names = "oscclk", + "noc", + "ip"; + }; + syscon_peric1: syscon@10c20000 { compatible = "samsung,exynosautov920-peric1-sysreg", "syscon"; @@ -283,12 +307,38 @@ pmu_system_controller: system-controller@11860000 { reg = <0x11860000 0x10000>; }; + cmu_hsi0: clock-controller@16000000 { + compatible = "samsung,exynosautov920-cmu-hsi0"; + reg = <0x16000000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_HSI0_NOC>; + clock-names = "oscclk", + "noc"; + }; + pinctrl_hsi0: pinctrl@16040000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x16040000 0x10000>; interrupts = ; }; + cmu_hsi1: clock-controller@16400000 { + compatible = "samsung,exynosautov920-cmu-hsi1"; + reg = <0x16400000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_HSI1_NOC>, + <&cmu_top DOUT_CLKCMU_HSI1_USBDRD>, + <&cmu_top DOUT_CLKCMU_HSI1_MMC_CARD>; + clock-names = "oscclk", + "noc", + "usbdrd", + "mmc_card"; + }; + pinctrl_hsi1: pinctrl@16450000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x16450000 0x10000>;