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Mon, 7 Oct 2024 13:44:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 193.8.40.94) smtp.mailfrom=leica-geosystems.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=leica-geosystems.com; Received-SPF: Pass (protection.outlook.com: domain of leica-geosystems.com designates 193.8.40.94 as permitted sender) receiver=protection.outlook.com; client-ip=193.8.40.94; helo=hexagon.com; pr=C Received: from hexagon.com (193.8.40.94) by DB5PEPF00014B8F.mail.protection.outlook.com (10.167.8.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Mon, 7 Oct 2024 13:44:28 +0000 Received: from aherlnxbspsrv01.lgs-net.com ([10.60.34.116]) by hexagon.com with Microsoft SMTPSVC(10.0.17763.1697); Mon, 7 Oct 2024 15:44:28 +0200 From: Catalin Popescu To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, m.felsch@pengutronix.de, bsp-development.geo@leica-geosystems.com, Catalin Popescu Subject: [PATCH] arm64: dts: imx8mp: add cpuidle state "cpu-pd-wait" Date: Mon, 7 Oct 2024 15:44:24 +0200 Message-Id: <20241007134424.859467-1-catalin.popescu@leica-geosystems.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginalArrivalTime: 07 Oct 2024 13:44:28.0399 (UTC) FILETIME=[07AA67F0:01DB18BF] X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB5PEPF00014B8F:EE_|AM8PR06MB7363:EE_ X-MS-Office365-Filtering-Correlation-Id: aa6c3ac0-bdff-423a-da0d-08dce6d62a52 X-SET-LOWER-SCL-SCANNER: YES X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; 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X-OriginatorOrg: leica-geosystems.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2024 13:44:28.6605 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aa6c3ac0-bdff-423a-da0d-08dce6d62a52 X-MS-Exchange-CrossTenant-Id: 1b16ab3e-b8f6-4fe3-9f3e-2db7fe549f6a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=1b16ab3e-b8f6-4fe3-9f3e-2db7fe549f6a;Ip=[193.8.40.94];Helo=[hexagon.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B8F.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR06MB7363 So far, only WFI is supported on i.MX8mp platform. Add support for deeper cpuidle state "cpu-pd-wait" that would allow for better power usage during runtime. This is a port from NXP downstream kernel. Signed-off-by: Catalin Popescu --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) base-commit: 58ca61c1a866bfdaa5e19fb19a2416764f847d75 prerequisite-patch-id: 0000000000000000000000000000000000000000 diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index f3531cfb0d79..8b1e0ca248d1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -47,6 +47,20 @@ cpus { #address-cells = <1>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; @@ -65,6 +79,7 @@ A53_0: cpu@0 { nvmem-cell-names = "speed_grade"; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_1: cpu@1 { @@ -83,6 +98,7 @@ A53_1: cpu@1 { next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_2: cpu@2 { @@ -101,6 +117,7 @@ A53_2: cpu@2 { next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_3: cpu@3 { @@ -119,6 +136,7 @@ A53_3: cpu@3 { next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_L2: l2-cache0 {