From patchwork Tue Oct 8 22:37:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Atwood X-Patchwork-Id: 13827140 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 867B6CF042C for ; Tue, 8 Oct 2024 22:37:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5303C10E5FF; Tue, 8 Oct 2024 22:37:47 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="XChdVHWe"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0BBC110E260; Tue, 8 Oct 2024 22:37:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728427066; x=1759963066; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PuMuOZHGpetAAR0hpYL9i17GXiT1WxUXVgVYHF17tmQ=; b=XChdVHWeh2v3MjgMyT0LUZnMTKYf//Sk+PF58RZvQF1P2KJDvUt8HWj1 94YomkqPstZryC84yoAH/T8IL6L83oCpAxGpyLL2R/T2Vu4pHoZDiw+p8 mmVI0XmYVWxyTd4bpcEHNPetxfO+TIWdFsiIoTI+lxxCy49tvQlmTE7wM Sarx1wvTbnryvpSI+Kada4JC5GtQr9NgkqbM97Tu6QLWr7hRfwVQ/ILzS rSIwtM0nFglcPeL6hjiXXoN6c7AX1gctZoBhdoAawdNb1KlVi5aqxpI+e BUutYa5It6Vh/1ZWmZ0mqVVV/1D8roj3sG/bASGWgH6pxwH2UFf23VfL5 A==; X-CSE-ConnectionGUID: 5d+umG1tSDm5z0Onpr7qGw== X-CSE-MsgGUID: DDPHIvDMQQm0TX7HAk54aw== X-IronPort-AV: E=McAfee;i="6700,10204,11219"; a="39037281" X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="39037281" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:46 -0700 X-CSE-ConnectionGUID: Hc7mFkpWTC+USoidqP/GHw== X-CSE-MsgGUID: PMl9ZEkQTf2N0VjJIhTAoA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="80811828" Received: from msatwood-mobl.jf.intel.com ([10.24.12.132]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:45 -0700 From: Matt Atwood To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Clint Taylor , Matt Atwood Subject: [PATCH 01/10] drm/i915/xe3lpd: reuse xe2lpd definition Date: Tue, 8 Oct 2024 15:37:32 -0700 Message-ID: <20241008223741.82790-2-matthew.s.atwood@intel.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241008223741.82790-1-matthew.s.atwood@intel.com> References: <20241008223741.82790-1-matthew.s.atwood@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Clint Taylor xe3_lpd display is functionally identical to xe2_lpd for now so reuse the device description. A separate xe3 definition will be added in the future if/when new feature flags are required. Signed-off-by: Clint Taylor Signed-off-by: Matt Atwood Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display_device.c | 6 ++++++ drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++ include/drm/intel/i915_pciids.h | 12 ++++++++++++ 3 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index f33062322c66..aa22189e3853 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -1252,6 +1252,10 @@ static const struct platform_desc bmg_desc = { PLATFORM(BATTLEMAGE), }; +static const struct platform_desc ptl_desc = { + PLATFORM(PANTHERLAKE), +}; + __diag_pop(); /* @@ -1322,6 +1326,7 @@ static const struct { INTEL_MTL_IDS(INTEL_DISPLAY_DEVICE, &mtl_desc), INTEL_LNL_IDS(INTEL_DISPLAY_DEVICE, &lnl_desc), INTEL_BMG_IDS(INTEL_DISPLAY_DEVICE, &bmg_desc), + INTEL_PTL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc), }; static const struct { @@ -1332,6 +1337,7 @@ static const struct { { 14, 0, &xe_lpdp_display }, { 14, 1, &xe2_hpd_display }, { 20, 0, &xe2_lpd_display }, + { 30, 0, &xe2_lpd_display }, }; static const struct intel_display_device_info * diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 3ef537fa551a..071a36b51f79 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -70,6 +70,8 @@ enum intel_display_platform { INTEL_DISPLAY_LUNARLAKE, /* Display ver 14.1 (based on GMD ID) */ INTEL_DISPLAY_BATTLEMAGE, + /* Display ver 30 (based on GMD ID) */ + INTEL_DISPLAY_PANTHERLAKE, }; enum intel_display_subplatform { diff --git a/include/drm/intel/i915_pciids.h b/include/drm/intel/i915_pciids.h index 02156c6f79b6..6b92f8c3731b 100644 --- a/include/drm/intel/i915_pciids.h +++ b/include/drm/intel/i915_pciids.h @@ -794,4 +794,16 @@ MACRO__(0xE20D, ## __VA_ARGS__), \ MACRO__(0xE212, ## __VA_ARGS__) +/* PTL */ +#define INTEL_PTL_IDS(MACRO__, ...) \ + MACRO__(0xB080, ## __VA_ARGS__), \ + MACRO__(0xB081, ## __VA_ARGS__), \ + MACRO__(0xB082, ## __VA_ARGS__), \ + MACRO__(0xB090, ## __VA_ARGS__), \ + MACRO__(0xB091, ## __VA_ARGS__), \ + MACRO__(0xB092, ## __VA_ARGS__), \ + MACRO__(0xB0A0, ## __VA_ARGS__), \ + MACRO__(0xB0A1, ## __VA_ARGS__), \ + MACRO__(0xB0A2, ## __VA_ARGS__) + #endif /* _I915_PCIIDS_H */ From patchwork Tue Oct 8 22:37:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Atwood X-Patchwork-Id: 13827142 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B9C3CF042D for ; Tue, 8 Oct 2024 22:37:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CD69C10E605; Tue, 8 Oct 2024 22:37:48 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WRg9fa2x"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id BBA0310E287; Tue, 8 Oct 2024 22:37:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728427067; x=1759963067; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=X4yFoYG09nBDCVGDiZa3j9lk+3PKGtYPHU6d9kBAYt8=; b=WRg9fa2xQBc8P74jkVoeJbKTOYS5fJQkVgw01aI7CXaFMFJJkjsWbqlU 6SG5xsr+18G5oy3trPwZUdEn9Ssfl/ocjV3lMfdvHmFWPI8flpgelOOCo sp6Z+jQntCzCKFgiyBw6Ahj9CGORZcRa+M+PUDJhGE3luOGKmsavOK0k8 ZQG4+9VBWvcpkAjSatwftL2xR6P0XwT2zWFp/0WD0CV+VYnPNp6GpDGD/ 2PD0fvYZOvO6PLHW4w/6LzXFhH7ZeZoy6aYwY6VXcBpwjNljzKlX2DsHF WazAToh2099RDvBDf6+FmTMwosoFsRG1EJBTd5JuAmBQRDEirNwZng3ji w==; X-CSE-ConnectionGUID: UwQvN7+jRUGhUf61Z3EJrg== X-CSE-MsgGUID: qX2/x22KTPq+bisS3bNoUA== X-IronPort-AV: E=McAfee;i="6700,10204,11219"; a="39037282" X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="39037282" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:46 -0700 X-CSE-ConnectionGUID: 0+8QxvPDS66j3AlNm/7ksg== X-CSE-MsgGUID: waNaBbhjSpCpS9rp8s7Lqg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="80811832" Received: from msatwood-mobl.jf.intel.com ([10.24.12.132]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:46 -0700 From: Matt Atwood To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Matt Roper , Matt Atwood Subject: [PATCH 02/10] drm/i915/xe3lpd: Adjust watermark calculations Date: Tue, 8 Oct 2024 15:37:33 -0700 Message-ID: <20241008223741.82790-3-matthew.s.atwood@intel.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241008223741.82790-1-matthew.s.atwood@intel.com> References: <20241008223741.82790-1-matthew.s.atwood@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper Xe3 makes a couple minor tweaks to the watermark algorithm's block count calculations. Bspec: 68985 Signed-off-by: Matt Roper Signed-off-by: Matt Atwood Reviewed-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/skl_watermark.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 6e1f04d5ef47..31de33e868df 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -718,7 +718,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state, int width, const struct drm_format_info *format, u64 modifier, unsigned int rotation, u32 plane_pixel_rate, struct skl_wm_params *wp, - int color_plane); + int color_plane, unsigned int pan_x); static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, struct intel_plane *plane, @@ -765,7 +765,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state, drm_format_info(DRM_FORMAT_ARGB8888), DRM_FORMAT_MOD_LINEAR, DRM_MODE_ROTATE_0, - crtc_state->pixel_rate, &wp, 0); + crtc_state->pixel_rate, &wp, 0, 0); drm_WARN_ON(&i915->drm, ret); for (level = 0; level < i915->display.wm.num_levels; level++) { @@ -1742,7 +1742,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state, int width, const struct drm_format_info *format, u64 modifier, unsigned int rotation, u32 plane_pixel_rate, struct skl_wm_params *wp, - int color_plane) + int color_plane, unsigned int pan_x) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); @@ -1803,7 +1803,9 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state, wp->y_min_scanlines, wp->dbuf_block_size); - if (DISPLAY_VER(i915) >= 10) + if (DISPLAY_VER(i915) >= 30) + interm_pbpl += (pan_x != 0); + else if (DISPLAY_VER(i915) >= 10) interm_pbpl++; wp->plane_blocks_per_line = div_fixed16(interm_pbpl, @@ -1845,7 +1847,8 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state, fb->format, fb->modifier, plane_state->hw.rotation, intel_plane_pixel_rate(crtc_state, plane_state), - wp, color_plane); + wp, color_plane, + plane_state->uapi.src.x1); } static bool skl_wm_has_lines(struct drm_i915_private *i915, int level) @@ -1909,7 +1912,10 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, } } - blocks = fixed16_to_u32_round_up(selected_result) + 1; + blocks = fixed16_to_u32_round_up(selected_result); + if (DISPLAY_VER(i915) < 30) + blocks++; + /* * Lets have blocks at minimum equivalent to plane_blocks_per_line * as there will be at minimum one line for lines configuration. This From patchwork Tue Oct 8 22:37:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Atwood X-Patchwork-Id: 13827141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 96A28CF042A for ; Tue, 8 Oct 2024 22:37:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7BE7D10E601; Tue, 8 Oct 2024 22:37:48 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FyFXzW82"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5B66510E601; Tue, 8 Oct 2024 22:37:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728427067; x=1759963067; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9Ny8T6M3fzprq95+5lbmeUT/hXI8v2YRCwkTVK9nQHI=; b=FyFXzW825dAOuYTscj1YOAxtV1NE7AvHlXdBWNX7YE7IKdO2eRy2kjsE uwfdqLNhtIOEkG08V68D4Pzv8l1Ryy/N2pVPdeghpRYYyIW8ovOKRWG1M iwBBNFfbSM1KJDQVVWx8kDe6AdfiucqpFev2VzBRB2DiJAyqnNtZFLwMK MoVxGPk6IqCId17ewXzbTCZbgXGicVnuA7RPudU376eNH4pf6B7/m8c9v OSkQ1Y5KEoDHr2rCzSNeEnl3fyx+HSbTT7H5wIHrCs7uG39xJ2y4Ik65F Cz29hYgqu7fMYYpX12CHxdsOwquUQA+r7B1kTmjf7fDRPFrFeS7sYbQG9 w==; X-CSE-ConnectionGUID: dUTb8hxDTNOozrCR5WLA4g== X-CSE-MsgGUID: 5aZq0ljoQ0uVEeTqU/q2gQ== X-IronPort-AV: E=McAfee;i="6700,10204,11219"; a="39037284" X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="39037284" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:47 -0700 X-CSE-ConnectionGUID: EgvNcDvFSBSZx3XhDsSkEw== X-CSE-MsgGUID: 7RaJKkmzTCiWTRzijiN61A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="80811836" Received: from msatwood-mobl.jf.intel.com ([10.24.12.132]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:47 -0700 From: Matt Atwood To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Matt Roper , Matt Atwood Subject: [PATCH 03/10] drm/i915/xe3lpd: Add new display power wells Date: Tue, 8 Oct 2024 15:37:34 -0700 Message-ID: <20241008223741.82790-4-matthew.s.atwood@intel.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241008223741.82790-1-matthew.s.atwood@intel.com> References: <20241008223741.82790-1-matthew.s.atwood@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper Xe3's power well handling is similar to previous platforms, but there are a few changes that need to be handled to ensure optimal power management: - PGB now only depends on PG1, not PG2 - Transcoder B is now in PG1 (was previously in PGB) - Transcoders C & D are now in PG2 (were previously in PGC/PGD) - DC states now require PG2 to be off (whereas on Xe2 it could remain on as a dependency of PGB, although the features inside of it could not be used). Bspec: 72519, 68851 Signed-off-by: Matt Roper Signed-off-by: Matt Atwood Reviewed-by: Luca Coelho --- .../i915/display/intel_display_power_map.c | 135 +++++++++++++++++- 1 file changed, 134 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c index 10948b3964ee..255b2c09607c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c @@ -1586,6 +1586,137 @@ static const struct i915_power_well_desc_list xe2lpd_power_wells[] = { I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica), }; +/* + * Xe3 changes the power well hierarchy slightly from Xe_LPD+; PGB now + * depends on PG1 instead of PG2: + * + * PG0 + * | + * --PG1-- + * / | \ + * PGA PGB PG2 + * / \ + * PGC PGD + */ + +#define XE3LPD_PW_C_POWER_DOMAINS \ + POWER_DOMAIN_PIPE_C, \ + POWER_DOMAIN_PIPE_PANEL_FITTER_C + +#define XE3LPD_PW_D_POWER_DOMAINS \ + POWER_DOMAIN_PIPE_D, \ + POWER_DOMAIN_PIPE_PANEL_FITTER_D + +#define XE3LPD_PW_2_POWER_DOMAINS \ + XE3LPD_PW_C_POWER_DOMAINS, \ + XE3LPD_PW_D_POWER_DOMAINS, \ + POWER_DOMAIN_TRANSCODER_C, \ + POWER_DOMAIN_TRANSCODER_D, \ + POWER_DOMAIN_VGA, \ + POWER_DOMAIN_PORT_DDI_LANES_TC1, \ + POWER_DOMAIN_PORT_DDI_LANES_TC2, \ + POWER_DOMAIN_PORT_DDI_LANES_TC3, \ + POWER_DOMAIN_PORT_DDI_LANES_TC4 + +I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_2, + XE3LPD_PW_2_POWER_DOMAINS, + POWER_DOMAIN_INIT); + +I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_b, + POWER_DOMAIN_PIPE_B, + POWER_DOMAIN_PIPE_PANEL_FITTER_B, + POWER_DOMAIN_INIT); + +I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_c, + XE3LPD_PW_C_POWER_DOMAINS, + POWER_DOMAIN_INIT); + +I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_d, + XE3LPD_PW_D_POWER_DOMAINS, + POWER_DOMAIN_INIT); + +static const struct i915_power_well_desc xe3lpd_power_wells_main[] = { + { + .instances = &I915_PW_INSTANCES( + I915_PW("PW_2", &xe3lpd_pwdoms_pw_2, + .hsw.idx = ICL_PW_CTL_IDX_PW_2, + .id = SKL_DISP_PW_2), + ), + .ops = &hsw_power_well_ops, + .has_vga = true, + .has_fuses = true, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("PW_A", &xelpd_pwdoms_pw_a, + .hsw.idx = XELPD_PW_CTL_IDX_PW_A), + ), + .ops = &hsw_power_well_ops, + .irq_pipe_mask = BIT(PIPE_A), + .has_fuses = true, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("PW_B", &xe3lpd_pwdoms_pw_b, + .hsw.idx = XELPD_PW_CTL_IDX_PW_B), + ), + .ops = &hsw_power_well_ops, + .irq_pipe_mask = BIT(PIPE_B), + .has_fuses = true, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("PW_C", &xe3lpd_pwdoms_pw_c, + .hsw.idx = XELPD_PW_CTL_IDX_PW_C), + ), + .ops = &hsw_power_well_ops, + .irq_pipe_mask = BIT(PIPE_C), + .has_fuses = true, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("PW_D", &xe3lpd_pwdoms_pw_d, + .hsw.idx = XELPD_PW_CTL_IDX_PW_D), + ), + .ops = &hsw_power_well_ops, + .irq_pipe_mask = BIT(PIPE_D), + .has_fuses = true, + }, { + .instances = &I915_PW_INSTANCES( + I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A), + I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B), + I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1), + I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2), + I915_PW("AUX_TC3", &xelpdp_pwdoms_aux_tc3, .xelpdp.aux_ch = AUX_CH_USBC3), + I915_PW("AUX_TC4", &xelpdp_pwdoms_aux_tc4, .xelpdp.aux_ch = AUX_CH_USBC4), + ), + .ops = &xelpdp_aux_power_well_ops, + }, +}; + +I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_dc_off, + POWER_DOMAIN_DC_OFF, + XE3LPD_PW_2_POWER_DOMAINS, + XE3LPD_PW_C_POWER_DOMAINS, + XE3LPD_PW_D_POWER_DOMAINS, + POWER_DOMAIN_AUDIO_MMIO, + POWER_DOMAIN_INIT); + +static const struct i915_power_well_desc xe3lpd_power_wells_dcoff[] = { + { + .instances = &I915_PW_INSTANCES( + I915_PW("DC_off", &xe3lpd_pwdoms_dc_off, + .id = SKL_DISP_DC_OFF), + ), + .ops = &gen9_dc_off_power_well_ops, + }, +}; + + +static const struct i915_power_well_desc_list xe3lpd_power_wells[] = { + I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), + I915_PW_DESCRIPTORS(icl_power_wells_pw_1), + I915_PW_DESCRIPTORS(xe3lpd_power_wells_dcoff), + I915_PW_DESCRIPTORS(xe3lpd_power_wells_main), + I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica), +}; + static void init_power_well_domains(const struct i915_power_well_instance *inst, struct i915_power_well *power_well) { @@ -1693,7 +1824,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains) return 0; } - if (DISPLAY_VER(i915) >= 20) + if (DISPLAY_VER(i915) >= 30) + return set_power_wells(power_domains, xe3lpd_power_wells); + else if (DISPLAY_VER(i915) >= 20) return set_power_wells(power_domains, xe2lpd_power_wells); else if (DISPLAY_VER(i915) >= 14) return set_power_wells(power_domains, xelpdp_power_wells); From patchwork Tue Oct 8 22:37:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Atwood X-Patchwork-Id: 13827147 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0726CF0436 for ; Tue, 8 Oct 2024 22:37:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D22A610E610; Tue, 8 Oct 2024 22:37:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kT8xwyQB"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 08F0D10E601; Tue, 8 Oct 2024 22:37:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728427068; x=1759963068; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=46WTSoKQHstpXH4th6GymTB5Rl6Jrj00kx01X7UnEBE=; b=kT8xwyQBAigAJyYoJp375ExNgnL8zobKgXHnGZn7aCNyC82jEQTQ7ytm R42168S6pZ3XP3pz3S86OcHZ3c3Xv3yuD9ACUW6EpPTYQXuuMfFgOmTnT y6y0WZsQYQXswjB31KTsaathUfD9A2abrU2C2EBttVZZFTccqa4xM9la6 FSFTQwisqQAe84k5ZfYZTVVA7Vw0LmU3gwiHM8YSDdRGzN+IEpEIoIVVh 0ETs5iWGEfx3eZ+YHzOVtStiDzMuzlGCrkcGiBy4AdPUGoRzBjq0vTs/b f59rN8AsW+OwkQIqOSDkRHcvGMqP8y9VBJ6qS9Z2sy6oZ+s9D+GqX7tMc g==; X-CSE-ConnectionGUID: hnZtRldhRgqEf8t/xW7ofQ== X-CSE-MsgGUID: Drp9tvUuR1CzCy2qoLKKgw== X-IronPort-AV: E=McAfee;i="6700,10204,11219"; a="39037285" X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="39037285" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:48 -0700 X-CSE-ConnectionGUID: m8a07vA+Rf+s81qXoHltVQ== X-CSE-MsgGUID: U2m2WBmGQnq0uhexOp1vMA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="80811839" Received: from msatwood-mobl.jf.intel.com ([10.24.12.132]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:47 -0700 From: Matt Atwood To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Matt Roper , Matt Atwood Subject: [PATCH 04/10] drm/i915/xe3lpd: Update pmdemand programming Date: Tue, 8 Oct 2024 15:37:35 -0700 Message-ID: <20241008223741.82790-5-matthew.s.atwood@intel.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241008223741.82790-1-matthew.s.atwood@intel.com> References: <20241008223741.82790-1-matthew.s.atwood@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper There are some minor changes to pmdemand handling on Xe3: - Active scalers are no longer tracked. We can simply skip the readout and programming of this field. - Active dbuf slices are no longer tracked. We should skip the readout and programming of this field and also make sure that it stays 0 in our software bookkeeping so that we won't erroneously return true from intel_pmdemand_needs_update() due to mismatches. - Even though there aren't enough pipes to utilize them, the size of the 'active pipes' field has expanded to four bits, taking over the register bits previously used for dbuf slices. Since the lower bits of the mask have moved, we need to update our reads/writes to handle this properly. Bspec: 68883, 69125 Signed-off-by: Matt Roper Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/display/intel_pmdemand.c | 61 +++++++++++++------ drivers/gpu/drm/i915/display/intel_pmdemand.h | 4 +- drivers/gpu/drm/i915/i915_reg.h | 1 + 3 files changed, 45 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c index ceaf9e3147da..9af2f83d3a75 100644 --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c @@ -258,6 +258,7 @@ intel_pmdemand_connector_needs_update(struct intel_atomic_state *state) static bool intel_pmdemand_needs_update(struct intel_atomic_state *state) { + struct drm_i915_private *i915 = to_i915(state->base.dev); const struct intel_bw_state *new_bw_state, *old_bw_state; const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state; const struct intel_crtc_state *new_crtc_state, *old_crtc_state; @@ -274,12 +275,16 @@ static bool intel_pmdemand_needs_update(struct intel_atomic_state *state) new_dbuf_state = intel_atomic_get_new_dbuf_state(state); old_dbuf_state = intel_atomic_get_old_dbuf_state(state); if (new_dbuf_state && - (new_dbuf_state->active_pipes != - old_dbuf_state->active_pipes || - new_dbuf_state->enabled_slices != - old_dbuf_state->enabled_slices)) + new_dbuf_state->active_pipes != old_dbuf_state->active_pipes) return true; + if (DISPLAY_VER(i915) < 30) { + if (new_dbuf_state && + new_dbuf_state->enabled_slices != + old_dbuf_state->enabled_slices) + return true; + } + new_cdclk_state = intel_atomic_get_new_cdclk_state(state); old_cdclk_state = intel_atomic_get_old_cdclk_state(state); if (new_cdclk_state && @@ -329,8 +334,10 @@ int intel_pmdemand_atomic_check(struct intel_atomic_state *state) new_pmdemand_state->params.active_pipes = min_t(u8, hweight8(new_dbuf_state->active_pipes), 3); - new_pmdemand_state->params.active_dbufs = - min_t(u8, hweight8(new_dbuf_state->enabled_slices), 3); + + if (DISPLAY_VER(i915) < 30) + new_pmdemand_state->params.active_dbufs = + min_t(u8, hweight8(new_dbuf_state->enabled_slices), 3); new_cdclk_state = intel_atomic_get_cdclk_state(state); if (IS_ERR(new_cdclk_state)) @@ -395,27 +402,32 @@ intel_pmdemand_init_pmdemand_params(struct drm_i915_private *i915, reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)); - /* Set 1*/ pmdemand_state->params.qclk_gv_bw = REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, reg1); pmdemand_state->params.voltage_index = REG_FIELD_GET(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, reg1); pmdemand_state->params.qclk_gv_index = REG_FIELD_GET(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, reg1); - pmdemand_state->params.active_pipes = - REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1); - pmdemand_state->params.active_dbufs = - REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1); pmdemand_state->params.active_phys = REG_FIELD_GET(XELPDP_PMDEMAND_PHYS_MASK, reg1); - /* Set 2*/ pmdemand_state->params.cdclk_freq_mhz = REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, reg2); pmdemand_state->params.ddiclk_max = REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, reg2); - pmdemand_state->params.scalers = - REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2); + + if (DISPLAY_VER(i915) >= 30) { + pmdemand_state->params.active_pipes = + REG_FIELD_GET(XE3_PMDEMAND_PIPES_MASK, reg1); + } else { + pmdemand_state->params.active_pipes = + REG_FIELD_GET(XELPDP_PMDEMAND_PIPES_MASK, reg1); + pmdemand_state->params.active_dbufs = + REG_FIELD_GET(XELPDP_PMDEMAND_DBUFS_MASK, reg1); + + pmdemand_state->params.scalers = + REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2); + } unlock: mutex_unlock(&i915->display.pmdemand.lock); @@ -442,6 +454,10 @@ void intel_pmdemand_program_dbuf(struct drm_i915_private *i915, { u32 dbufs = min_t(u32, hweight8(dbuf_slices), 3); + /* PM Demand only tracks active dbufs on pre-Xe3 platforms */ + if (DISPLAY_VER(i915) >= 30) + return; + mutex_lock(&i915->display.pmdemand.lock); if (drm_WARN_ON(&i915->drm, !intel_pmdemand_check_prev_transaction(i915))) @@ -460,7 +476,8 @@ void intel_pmdemand_program_dbuf(struct drm_i915_private *i915, } static void -intel_pmdemand_update_params(const struct intel_pmdemand_state *new, +intel_pmdemand_update_params(struct drm_i915_private *i915, + const struct intel_pmdemand_state *new, const struct intel_pmdemand_state *old, u32 *reg1, u32 *reg2, bool serialized) { @@ -495,16 +512,22 @@ intel_pmdemand_update_params(const struct intel_pmdemand_state *new, update_reg(reg1, qclk_gv_bw, XELPDP_PMDEMAND_QCLK_GV_BW_MASK); update_reg(reg1, voltage_index, XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK); update_reg(reg1, qclk_gv_index, XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK); - update_reg(reg1, active_pipes, XELPDP_PMDEMAND_PIPES_MASK); - update_reg(reg1, active_dbufs, XELPDP_PMDEMAND_DBUFS_MASK); update_reg(reg1, active_phys, XELPDP_PMDEMAND_PHYS_MASK); /* Set 2*/ update_reg(reg2, cdclk_freq_mhz, XELPDP_PMDEMAND_CDCLK_FREQ_MASK); update_reg(reg2, ddiclk_max, XELPDP_PMDEMAND_DDICLK_FREQ_MASK); - update_reg(reg2, scalers, XELPDP_PMDEMAND_SCALERS_MASK); update_reg(reg2, plls, XELPDP_PMDEMAND_PLLS_MASK); + if (DISPLAY_VER(i915) >= 30) { + update_reg(reg1, active_pipes, XE3_PMDEMAND_PIPES_MASK); + } else { + update_reg(reg1, active_pipes, XELPDP_PMDEMAND_PIPES_MASK); + update_reg(reg1, active_dbufs, XELPDP_PMDEMAND_DBUFS_MASK); + + update_reg(reg2, scalers, XELPDP_PMDEMAND_SCALERS_MASK); + } + #undef update_reg } @@ -529,7 +552,7 @@ intel_pmdemand_program_params(struct drm_i915_private *i915, reg2 = intel_de_read(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1)); mod_reg2 = reg2; - intel_pmdemand_update_params(new, old, &mod_reg1, &mod_reg2, + intel_pmdemand_update_params(i915, new, old, &mod_reg1, &mod_reg2, serialized); if (reg1 != mod_reg1) { diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.h b/drivers/gpu/drm/i915/display/intel_pmdemand.h index 128fd61f8f14..a1c49efdc493 100644 --- a/drivers/gpu/drm/i915/display/intel_pmdemand.h +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.h @@ -20,14 +20,14 @@ struct pmdemand_params { u8 voltage_index; u8 qclk_gv_index; u8 active_pipes; - u8 active_dbufs; + u8 active_dbufs; /* pre-Xe3 only */ /* Total number of non type C active phys from active_phys_mask */ u8 active_phys; u8 plls; u16 cdclk_freq_mhz; /* max from ddi_clocks[] */ u16 ddiclk_max; - u8 scalers; + u8 scalers; /* pre-Xe3 only */ }; struct intel_pmdemand_state { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 818142f5a10c..d30459f8d1cb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2705,6 +2705,7 @@ #define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16) #define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12) #define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8) +#define XE3_PMDEMAND_PIPES_MASK REG_GENMASK(7, 4) #define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6) #define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4) #define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0) From patchwork Tue Oct 8 22:37:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Atwood X-Patchwork-Id: 13827143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5066FCF042C for ; Tue, 8 Oct 2024 22:37:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E8CB10E603; Tue, 8 Oct 2024 22:37:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="N0usWddA"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8F8E310E603; Tue, 8 Oct 2024 22:37:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728427069; x=1759963069; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lVEu8PXqU/hx6B5niOi9zHYApMRmg9lo5UOPf0rdyFY=; b=N0usWddAi2B+05sTCCh5ODhfpOfMqvDd7EbSqYz9R+hr6MqXBhN9nHRM TGKpyRmo8jSC8UvncoTdn0Up8/iM7SlAJoEjM4dyVbRbOqVUGLvLrN4z6 9xY+t6mrqI2IvheyIVY/Otx2M7hFLeglpTvwi2CzYFn2+Y31wjCnZ4YsQ uVGEtQlGNXtNJOWqKq8xrPOaYf/LNxvWm08nO5qn/rnnrIDwlSuMYlp9W TfY3Zh3RkwO30kSVem+mtUjdZrXb14EMPHlAAU3r4tj/eVekFSO8f34DQ lOWENZJOobQtLF7ZzcoasXfS+yZmk08b4sHMGaFF4QXYozIt59cw36OEV g==; X-CSE-ConnectionGUID: +p+5x41JRZCxSiUDGHYnlQ== X-CSE-MsgGUID: 4IBF9sqtTlWPHt1ZQUfiHQ== X-IronPort-AV: E=McAfee;i="6700,10204,11219"; a="39037294" X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="39037294" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:48 -0700 X-CSE-ConnectionGUID: Le0+tN6vQRSX/0fljF7n3w== X-CSE-MsgGUID: OTKGOF2lR7Caqp8D5mISKA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="80811842" Received: from msatwood-mobl.jf.intel.com ([10.24.12.132]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:48 -0700 From: Matt Atwood To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Radhakrishna Sripada , Gustavo Sousa , Matt Atwood Subject: [PATCH 05/10] drm/i915/xe3lpd: Add cdclk changes Date: Tue, 8 Oct 2024 15:37:36 -0700 Message-ID: <20241008223741.82790-6-matthew.s.atwood@intel.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241008223741.82790-1-matthew.s.atwood@intel.com> References: <20241008223741.82790-1-matthew.s.atwood@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Radhakrishna Sripada Xe3_LPD has new max cdclk of 691200 which requires reusing the lnl table and modify/add higher frequencies. Updating the max cdclk supported by the platform and voltage_level determination is also updated. There are minor changes in cdclk programming sequence compared to lnl, where programming cd2x divider needs to be skipped. This is already handled by the calculations in existing code. Bspec: 68861, 68863, 68864 Cc: Gustavo Sousa Signed-off-by: Radhakrishna Sripada Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/display/intel_cdclk.c | 56 +++++++++++++++++++++- 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index fa1c2012b10c..6ac7bd6afc36 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1468,6 +1468,32 @@ static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { {} }; +static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = { + { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, + { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, + { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, + { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, + { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, + { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, + { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 }, + { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee }, + { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de }, + { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe }, + { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe }, + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, + { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe }, + { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe }, + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, + { .refclk = 38400, .cdclk = 561600, .ratio = 36, .waveform = 0xf7de }, + { .refclk = 38400, .cdclk = 604800, .ratio = 36, .waveform = 0xfefe }, + { .refclk = 38400, .cdclk = 648000, .ratio = 36, .waveform = 0xfffe }, + { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, + {} +}; + static const int cdclk_squash_len = 16; static int cdclk_squash_divider(u16 waveform) @@ -1594,6 +1620,20 @@ static u8 rplu_calc_voltage_level(int cdclk) rplu_voltage_level_max_cdclk); } +static u8 xe3lpd_calc_voltage_level(int cdclk) +{ + static const int xe3lpd_voltage_level_max_cdclk[] = { + [0] = 307200, + [1] = 480000, + [2] = 556800, + [3] = 691200, + }; + + return calc_voltage_level(cdclk, + ARRAY_SIZE(xe3lpd_voltage_level_max_cdclk), + xe3lpd_voltage_level_max_cdclk); +} + static void icl_readout_refclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { @@ -3437,7 +3477,9 @@ void intel_update_max_cdclk(struct intel_display *display) { struct drm_i915_private *dev_priv = to_i915(display->drm); - if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { + if (DISPLAY_VER(display) >= 30) { + display->cdclk.max_cdclk_freq = 691200; + } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { if (display->cdclk.hw.ref == 24000) display->cdclk.max_cdclk_freq = 552000; else @@ -3650,6 +3692,13 @@ void intel_cdclk_debugfs_register(struct intel_display *display) display, &i915_cdclk_info_fops); } +static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = { + .get_cdclk = bxt_get_cdclk, + .set_cdclk = bxt_set_cdclk, + .modeset_calc_cdclk = bxt_modeset_calc_cdclk, + .calc_voltage_level = xe3lpd_calc_voltage_level, +}; + static const struct intel_cdclk_funcs rplu_cdclk_funcs = { .get_cdclk = bxt_get_cdclk, .set_cdclk = bxt_set_cdclk, @@ -3794,7 +3843,10 @@ void intel_init_cdclk_hooks(struct intel_display *display) { struct drm_i915_private *dev_priv = to_i915(display->drm); - if (DISPLAY_VER(display) >= 20) { + if (DISPLAY_VER(display) >= 30) { + display->funcs.cdclk = &xe3lpd_cdclk_funcs; + display->cdclk.table = xe3lpd_cdclk_table; + } else if (DISPLAY_VER(display) >= 20) { display->funcs.cdclk = &rplu_cdclk_funcs; display->cdclk.table = xe2lpd_cdclk_table; } else if (DISPLAY_VER_FULL(display) >= IP_VER(14, 1)) { From patchwork Tue Oct 8 22:37:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Atwood X-Patchwork-Id: 13827144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5103ACF0433 for ; Tue, 8 Oct 2024 22:37:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7460710E60C; Tue, 8 Oct 2024 22:37:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="JRBtYYqU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 06BF210E603; Tue, 8 Oct 2024 22:37:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728427069; x=1759963069; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ezuk9ZVixS0Bdwk+/pYM8vQ6lsIZj7vxUNdV2OyKVBU=; b=JRBtYYqUjOjrvTpTOZGwl8AYImkK/zLGcZw99hKZzRYAZngqEBAzJh7x 9MhrRyol9aGD9GKYc+rSQ+aFTpwkBtY6ixyiMa7iVD9AG9xgr66APFEyH vgKzR/3r/IFymPimml9HsSl1nQ/iLXNpV1+z/SMdhkEZlHceDxfjYpK5r GV/o3xfLnDDnLzapaF3Y66xZ8Q+lK4aIFgjSd8Hwz/xaY3Ja6e3aOWXTw YpwASMD9+WYRGpfrjvcifiqFjkcTrosF4qfY47m1j1YTaojH+mLp2vjl3 siDHhwSUCbr8WgANrYKnMshecPi9P7fQZVyDm36NpaU1+YUmEKZUEyQ/d Q==; X-CSE-ConnectionGUID: 2A71NvSLQqKf+oAK7ScVJA== X-CSE-MsgGUID: bOlRj3FSQYegh7rb/S/wfA== X-IronPort-AV: E=McAfee;i="6700,10204,11219"; a="39037295" X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="39037295" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:49 -0700 X-CSE-ConnectionGUID: TJMXs95XTXqacxZOtDjrfw== X-CSE-MsgGUID: p62INz4bRYW52m4quLdxaw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="80811846" Received: from msatwood-mobl.jf.intel.com ([10.24.12.132]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:48 -0700 From: Matt Atwood To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Suraj Kandpal , Matt Atwood Subject: [PATCH 06/10] drm/i915/xe3lpd: Add macro to choose HDCP_LINE_REKEY bit Date: Tue, 8 Oct 2024 15:37:37 -0700 Message-ID: <20241008223741.82790-7-matthew.s.atwood@intel.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241008223741.82790-1-matthew.s.atwood@intel.com> References: <20241008223741.82790-1-matthew.s.atwood@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Suraj Kandpal DISPLAY_VER() >= 30 has the HDCP_LINE_REKEY bit redefined from bit 12 to bit 14. Create a macro to choose the correct bit based on DISPLAY_VER(). Signed-off-by: Suraj Kandpal Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/display/intel_hdcp.c | 5 +++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index ed6aa87403e2..e9b0414590ce 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -47,10 +47,11 @@ intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder, intel_de_rmw(display, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder), 0, HDCP_LINE_REKEY_DISABLE); else if (IS_DISPLAY_VER_STEP(display, IP_VER(14, 1), STEP_B0, STEP_FOREVER) || - IS_DISPLAY_VER_STEP(display, IP_VER(20, 0), STEP_B0, STEP_FOREVER)) + IS_DISPLAY_VER_STEP(display, IP_VER(20, 0), STEP_B0, STEP_FOREVER) || + DISPLAY_VER(display) >= 30) intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder), - 0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE); + 0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE(display)); } } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d30459f8d1cb..da65500cd0c8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3832,7 +3832,7 @@ enum skl_power_gate { #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) -#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12) +#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE(display) (DISPLAY_VER(display) >= 30 ? REG_BIT(15) : REG_BIT(12)) #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) From patchwork Tue Oct 8 22:37:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Atwood X-Patchwork-Id: 13827148 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8EB0CCF0439 for ; Tue, 8 Oct 2024 22:37:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DA85710E612; Tue, 8 Oct 2024 22:37:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="br2Jl+Pa"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 852DD10E608; Tue, 8 Oct 2024 22:37:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728427070; x=1759963070; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1Dcjbfg/KTffaljo/Exf5s9G5KuehLL0msqMILUED9Q=; b=br2Jl+PaWHPUJuVHQpB4bGofDF09Ld7rL/nHBe8Hhgr3CzRZThzsYWrg OFlRTSangGLsqKJg4qTjBpATzNVBxM/Ph3vzUBRxb8ijfCSY7a6ftuSvi 81OiXMC6kf+uKnduUWAMiAr2gDGRItVHen/k9LIn6mnwmXyOsjVS7xsqo 1yQFRVrahXzZp1eNJ9p3XliZV6EaXuzVMR/M1v7cS6xtuAwSmFT+EsHDR qlH1cdo6sgOiL+iXA4n7rrUltwr1lC7zb26Ac5rVkddt2bjgNd9TeUsRN ZvrCW9DrDEn+lZCghBl4Cn1d+fUnBOMIurK3gaBZMaVx+Q0Ntesp3Kh/h g==; X-CSE-ConnectionGUID: yA2wIjnFRPipCOkbi4bMEg== X-CSE-MsgGUID: 9/NMSl1/Tm6qkWtjeUVC1w== X-IronPort-AV: E=McAfee;i="6700,10204,11219"; a="39037297" X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="39037297" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:49 -0700 X-CSE-ConnectionGUID: EvNl8cMtRDOSzfXtiEPJOA== X-CSE-MsgGUID: 7vUFMgb/SrWUa5zpWhnOaQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="80811850" Received: from msatwood-mobl.jf.intel.com ([10.24.12.132]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:49 -0700 From: Matt Atwood To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Suraj Kandpal , Matt Atwood Subject: [PATCH 07/10] drm/i915/xe3lpd: Add C20 Phy consolidated programming table Date: Tue, 8 Oct 2024 15:37:38 -0700 Message-ID: <20241008223741.82790-8-matthew.s.atwood@intel.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241008223741.82790-1-matthew.s.atwood@intel.com> References: <20241008223741.82790-1-matthew.s.atwood@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Suraj Kandpal From DISPLAY_VER() >= 30 C20 PHY consolidated programming table of DP and eDP been merged and now use the same rates and values. eDP over TypeC has also been introduced. Moreover it allows more granular and higher rates. Add new table to represent this change. Bspec: 68961 Signed-off-by: Suraj Kandpal Signed-off-by: Matt Atwood Reviewed-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 24 ++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 4a6c3040ca15..0d6f75ae35f5 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -1122,6 +1122,22 @@ static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = { NULL, }; +static const struct intel_c20pll_state * const xe3lpd_c20_dp_edp_tables[] = { + &mtl_c20_dp_rbr, + &xe2hpd_c20_edp_r216, + &xe2hpd_c20_edp_r243, + &mtl_c20_dp_hbr1, + &xe2hpd_c20_edp_r324, + &xe2hpd_c20_edp_r432, + &mtl_c20_dp_hbr2, + &xe2hpd_c20_edp_r675, + &mtl_c20_dp_hbr3, + &mtl_c20_dp_uhbr10, + &xe2hpd_c20_dp_uhbr13_5, + &mtl_c20_dp_uhbr20, + NULL, +}; + /* * HDMI link rates with 38.4 MHz reference clock. */ @@ -2242,11 +2258,15 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, struct drm_i915_private *i915 = to_i915(encoder->base.dev); if (intel_crtc_has_dp_encoder(crtc_state)) { - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - return xe2hpd_c20_edp_tables; + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { + if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) + return xe2hpd_c20_edp_tables; + } if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) return xe2hpd_c20_dp_tables; + else if (DISPLAY_VER(i915) >= 30) + return xe3lpd_c20_dp_edp_tables; else return mtl_c20_dp_tables; From patchwork Tue Oct 8 22:37:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Atwood X-Patchwork-Id: 13827145 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C34A6CF042A for ; Tue, 8 Oct 2024 22:37:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A8ED610E602; Tue, 8 Oct 2024 22:37:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="eqPMItKv"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1985D10E608; Tue, 8 Oct 2024 22:37:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728427070; x=1759963070; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=flY6UGWxGmAB6AHvdOEcIlWrpTLqwN0jhUutDadTauQ=; b=eqPMItKvSfrPfG15flIkjj0HBExgRkoJoT7qOTQHYMyMYn89JHRf8yEC eFOmOgK3YfegJWwRhJxBp3r53Cmctud3LOFYBgXPdU0VcvdonE2LmGDoO mprLuEDkxt7yFFQoMyNwjH+BkHP+UwsEAD3i9+++Lyy9mMLDY/0jnikJO 2EWwHB5TIjhtuJeBHYaK8ENprcfmyFmnlTcE7YG6kDwjb5rct7beIHXZb S0u4xEGU6pWIUTU6WpDdE2PPqsqF+S8XsiRhs1/fNFFesOFuO/kXrmAkL gdVKCgKFhJriwAUVNHwdgquNWcmBnBquZasaGw/PiCk8/LDaCnpjD1zNF A==; X-CSE-ConnectionGUID: 6+i0pRq3Thu0Z9kbLZLnZg== X-CSE-MsgGUID: ToamC6ExT82oeGbwv3mtyg== X-IronPort-AV: E=McAfee;i="6700,10204,11219"; a="39037300" X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="39037300" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:50 -0700 X-CSE-ConnectionGUID: 20Yw8cKTT6aWdPNhvvjnoA== X-CSE-MsgGUID: 1g1qGnifTiC2H3VpKlIArA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="80811853" Received: from msatwood-mobl.jf.intel.com ([10.24.12.132]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:49 -0700 From: Matt Atwood To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Suraj Kandpal , Matt Atwood Subject: [PATCH 08/10] drm/i915/xe3lpd: Add new bit range of MAX swing setup Date: Tue, 8 Oct 2024 15:37:39 -0700 Message-ID: <20241008223741.82790-9-matthew.s.atwood@intel.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241008223741.82790-1-matthew.s.atwood@intel.com> References: <20241008223741.82790-1-matthew.s.atwood@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Suraj Kandpal Add new bit range for Max PHY Swing Setup in PORT_ALPM_CTL register for DISPLAY_VER >= 30. Bspec: 70277 Signed-off-by: Suraj Kandpal Signed-off-by: Matt Atwood Reviewed-by: Shekhar Chauhan --- drivers/gpu/drm/i915/display/intel_alpm.c | 2 +- drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 55f3ae1e68c9..100ce776a203 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -334,7 +334,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, intel_de_write(display, PORT_ALPM_CTL(port), PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | - PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | + PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(display, 15) | PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | PORT_ALPM_CTL_SILENCE_PERIOD( intel_dp->alpm_parameters.silence_period_sym_clocks)); diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 0841242543ca..046e400704e8 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -299,7 +299,9 @@ #define PORT_ALPM_CTL(port) _MMIO_PORT(port, _PORT_ALPM_CTL_A, _PORT_ALPM_CTL_B) #define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31) #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20) -#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val) +#define PTL_PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(25, 20) +#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(display, val) (DISPLAY_VER(display) >= 30 ? REG_FIELD_PREP(PTL_PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val) :\ + REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val)) #define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK REG_GENMASK(19, 16) #define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK, val) #define PORT_ALPM_CTL_SILENCE_PERIOD_MASK REG_GENMASK(7, 0) From patchwork Tue Oct 8 22:37:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Atwood X-Patchwork-Id: 13827149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 468D7CF042E for ; Tue, 8 Oct 2024 22:37:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C759810E613; Tue, 8 Oct 2024 22:37:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="BreKkOpD"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id BAE2B10E60F; Tue, 8 Oct 2024 22:37:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728427071; x=1759963071; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4WYcOxeFEHx7fhoQsQjrYNitYn6S0kg+pmhaVq8NAnU=; b=BreKkOpDblOS+tpsgw0xg9N8bgdgLJ/FM22P9OlR0Q5k5PM8G6r3fiwM Gokx7WHfHtfiNG2H8ox2QUhyelWBrnCTOr9aWqLsDDaPUzHTEIy6KaGHz HYflBZnAFCg/r2PlRSs5X/3hgGcwd4/D2ekYCsGq9OojV3HAuBXgvc4Vx n12ZfF2zluvLR1hEh5dupmAJtWsWj1y4lFpIpq5+16fQxNkS/5LaoeeuG 9TRQs/97zxtiiY9Nf3ljVw09Iex0QBp3KlJFIxlz3LtYax49CpJk2IVzi LJowYiaKbGAU0Q7aA/g2//AXx+CwckUjvb0wyuHnDGiYTg9a4mPlP9C3E A==; X-CSE-ConnectionGUID: ml0vXaL9RV+ZqtpmnDQuXA== X-CSE-MsgGUID: S+E36AleTtK3+Ro+S3QK/Q== X-IronPort-AV: E=McAfee;i="6700,10204,11219"; a="39037302" X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="39037302" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:50 -0700 X-CSE-ConnectionGUID: NeBRjr7XQAytROD2nf/xUw== X-CSE-MsgGUID: +uav4hpwSJKgqp8w6rkNRQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="80811856" Received: from msatwood-mobl.jf.intel.com ([10.24.12.132]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:50 -0700 From: Matt Atwood To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Suraj Kandpal , Matt Atwood Subject: [PATCH 09/10] drm/i915/xe3lpd: Add check to see if edp over type c is allowed Date: Tue, 8 Oct 2024 15:37:40 -0700 Message-ID: <20241008223741.82790-10-matthew.s.atwood@intel.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241008223741.82790-1-matthew.s.atwood@intel.com> References: <20241008223741.82790-1-matthew.s.atwood@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Suraj Kandpal Read PICA register to see if edp over type C is possible and then add the appropriate tables for it. Bspec: 68846 Signed-off-by: Suraj Kandpal Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 ++ .../gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 4 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 0d6f75ae35f5..1c8c2a2b05e1 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2261,6 +2261,8 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) return xe2hpd_c20_edp_tables; + if (DISPLAY_VER(i915) >= 30 && encoder->typec_supp) + return xe3lpd_c20_dp_edp_tables; } if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 2bb1fa64da2f..e9dc7707fbcd 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -158,6 +158,7 @@ struct intel_encoder { enum port port; u16 cloneable; u8 pipe_mask; + bool typec_supp; /* Check and recover a bad link state. */ struct delayed_work link_check_work; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index fbb096be02ad..917a503cc43b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5570,6 +5570,20 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd); } +static void +intel_dp_check_edp_typec_supp(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + bool is_tc_port = intel_encoder_is_tc(encoder); + u32 ret = 0; + + if (encoder->type != INTEL_OUTPUT_EDP || !is_tc_port) + return; + + ret = intel_de_read(i915, PICA_PHY_CONFIG_CONTROL); + encoder->typec_supp = ret & EDP_ON_TYPEC; +} + static int intel_dp_detect(struct drm_connector *connector, struct drm_modeset_acquire_ctx *ctx, @@ -5595,6 +5609,8 @@ intel_dp_detect(struct drm_connector *connector, if (!intel_display_driver_check_access(dev_priv)) return connector->status; + intel_dp_check_edp_typec_supp(encoder); + /* Can't disconnect eDP */ if (intel_dp_is_edp(intel_dp)) status = edp_detect(intel_dp); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index da65500cd0c8..5f5a6ade5f8c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4583,4 +4583,7 @@ enum skl_power_gate { #define MTL_MEDIA_GSI_BASE 0x380000 +#define PICA_PHY_CONFIG_CONTROL _MMIO(0x16FE68) +#define EDP_ON_TYPEC REG_BIT(31) + #endif /* _I915_REG_H_ */ From patchwork Tue Oct 8 22:37:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Atwood X-Patchwork-Id: 13827146 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BE86CF0429 for ; Tue, 8 Oct 2024 22:37:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AEA2310E60F; Tue, 8 Oct 2024 22:37:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="EEeeJn0G"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4073610E60F; Tue, 8 Oct 2024 22:37:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728427071; x=1759963071; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=x12u9sZdj9Z+CFEQFhSZUb1EdU1mYtiL5y0WfZwvTuY=; b=EEeeJn0GbAIT1f8gOlTEavYhnPD0wOcUKAlfpBnO/AgnECws8+lbOsJO PCI0mT7Tr6Aa96GU/ikZZ5DqfKRyyB6PGSp6PxdhdwnHqfiKl6ngZKThg lVa3eOeWT7G2sVQrL/09uTI+MeSKVVpoIUYTypX65eX5MJ9qz1WJwxmVu I46H17p1UtQ5UWbzEb/eTfwwxoMuebPbCstWK9ATJVkzqJzD2oGvXOj9X Bu/teRbeK+5tIO6nRpfIUMUERmo1/sKonWwbY3Cor1NltPsd6rgnZg1HN EwjvAqwTKl4IxPQV7Mi6gIotcoJxy693C583WywJxDr8Y727Im/by9W8n A==; X-CSE-ConnectionGUID: zaHMlG7qTsKPI6Dwgv5H9g== X-CSE-MsgGUID: T3uR0f0hQbidwtGz62s4Ug== X-IronPort-AV: E=McAfee;i="6700,10204,11219"; a="39037303" X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="39037303" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:51 -0700 X-CSE-ConnectionGUID: O9CHIl+XR9SkJ6hbt5jbfA== X-CSE-MsgGUID: TGX14IIATPKWVMcrsTxZtA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,188,1725346800"; d="scan'208";a="80811859" Received: from msatwood-mobl.jf.intel.com ([10.24.12.132]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Oct 2024 15:37:51 -0700 From: Matt Atwood To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Suraj Kandpal , Matt Atwood Subject: [PATCH 10/10] drm/i915/xe3lpd: Add powerdown value of eDP over type c Date: Tue, 8 Oct 2024 15:37:41 -0700 Message-ID: <20241008223741.82790-11-matthew.s.atwood@intel.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241008223741.82790-1-matthew.s.atwood@intel.com> References: <20241008223741.82790-1-matthew.s.atwood@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Suraj Kandpal Add condition for P2.PG power down value. Bspec: 74494 Signed-off-by: Suraj Kandpal Signed-off-by: Matt Atwood Reviewed-by: Shekhar Chauhan --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 1c8c2a2b05e1..3d95ee65a9f1 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -3144,7 +3144,8 @@ static u8 cx0_power_control_disable_val(struct intel_encoder *encoder) if (intel_encoder_is_c10phy(encoder)) return CX0_P2PG_STATE_DISABLE; - if (IS_BATTLEMAGE(i915) && encoder->port == PORT_A) + if ((IS_BATTLEMAGE(i915) && encoder->port == PORT_A) || + (DISPLAY_VER(i915) >= 30 && encoder->type == INTEL_OUTPUT_EDP)) return CX0_P2PG_STATE_DISABLE; return CX0_P4PG_STATE_DISABLE;