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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:28:38.1436 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15df0581-d290-47b7-f6e2-08dce87f6dea X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017090.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8584 X-Patchwork-Delegate: kuba@kernel.org From: Abin Joseph Add s_axi_aclk AXI4 clock support. Traditionally this IP was used on microblaze platforms which had fixed clocks enabled all the time. But since its a PL IP, it can also be used on SoC platforms like Zynq UltraScale+ MPSoC which combines processing system (PS) and user programmable logic (PL) into the same device. On these platforms instead of fixed enabled clocks it is mandatory to explicitly enable IP clocks for proper functionality. So make clock a required property and also define max supported clock constraints. Signed-off-by: Abin Joseph Signed-off-by: Radhey Shyam Pandey Acked-by: Conor Dooley --- Changes for v3: - Add Conor acked-by tag. Changes for v2: - Make clocks as required property. --- Documentation/devicetree/bindings/net/xlnx,emaclite.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml b/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml index 92d8ade988f6..e16384aff557 100644 --- a/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml +++ b/Documentation/devicetree/bindings/net/xlnx,emaclite.yaml @@ -29,6 +29,9 @@ properties: interrupts: maxItems: 1 + clocks: + maxItems: 1 + phy-handle: true local-mac-address: true @@ -45,6 +48,7 @@ required: - compatible - reg - interrupts + - clocks - phy-handle additionalProperties: false @@ -56,6 +60,7 @@ examples: reg = <0x40e00000 0x10000>; interrupt-parent = <&axi_intc_1>; interrupts = <1>; + clocks = <&dummy>; local-mac-address = [00 00 00 00 00 00]; phy-handle = <&phy0>; xlnx,rx-ping-pong; From patchwork Wed Oct 9 16:28:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Radhey Shyam Pandey X-Patchwork-Id: 13828768 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2057.outbound.protection.outlook.com [40.107.237.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC53C1E7C10; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:28:42.5796 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4795d60-43c9-46d9-89b8-08dce87f70a0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001708E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7646 X-Patchwork-Delegate: kuba@kernel.org From: Abin Joseph Use device managed ethernet device allocation to simplify the error handling logic. No functional change. Signed-off-by: Abin Joseph Signed-off-by: Radhey Shyam Pandey Reviewed-by: Simon Horman --- Changes for v3: - None Changes for v2: - None --- drivers/net/ethernet/xilinx/xilinx_emaclite.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c index 2eb7f23538a6..418587942527 100644 --- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c +++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c @@ -1097,7 +1097,7 @@ static int xemaclite_of_probe(struct platform_device *ofdev) dev_info(dev, "Device Tree Probing\n"); /* Create an ethernet device instance */ - ndev = alloc_etherdev(sizeof(struct net_local)); + ndev = devm_alloc_etherdev(dev, sizeof(struct net_local)); if (!ndev) return -ENOMEM; @@ -1110,15 +1110,13 @@ static int xemaclite_of_probe(struct platform_device *ofdev) /* Get IRQ for the device */ rc = platform_get_irq(ofdev, 0); if (rc < 0) - goto error; + return rc; ndev->irq = rc; lp->base_addr = devm_platform_get_and_ioremap_resource(ofdev, 0, &res); - if (IS_ERR(lp->base_addr)) { - rc = PTR_ERR(lp->base_addr); - goto error; - } + if (IS_ERR(lp->base_addr)) + return PTR_ERR(lp->base_addr); ndev->mem_start = res->start; ndev->mem_end = res->end; @@ -1167,8 +1165,6 @@ static int xemaclite_of_probe(struct platform_device *ofdev) put_node: of_node_put(lp->phy_node); -error: - free_netdev(ndev); return rc; } @@ -1197,8 +1193,6 @@ static void xemaclite_of_remove(struct platform_device *of_dev) of_node_put(lp->phy_node); lp->phy_node = NULL; - - free_netdev(ndev); } #ifdef CONFIG_NET_POLL_CONTROLLER From patchwork Wed Oct 9 16:28:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Radhey Shyam Pandey X-Patchwork-Id: 13828767 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2071.outbound.protection.outlook.com [40.107.101.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE01F1DEFF4; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:28:47.9147 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0a9199dc-71f7-42c1-1409-08dce87f73c5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017091.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9190 X-Patchwork-Delegate: kuba@kernel.org From: Abin Joseph Adapt to use the clock framework. Add s_axi_aclk clock from the processor bus clock domain and make clk optional to keep DTB backward compatibility. Signed-off-by: Abin Joseph Signed-off-by: Radhey Shyam Pandey Reviewed-by: Simon Horman Reviewed-by: Simon Horman --- Changes for v3: - Remove braces around dev_err_probe(). Changes for v2: - None --- drivers/net/ethernet/xilinx/xilinx_emaclite.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c index 418587942527..ecf47107146d 100644 --- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c +++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c @@ -7,6 +7,7 @@ * Copyright (c) 2007 - 2013 Xilinx, Inc. */ +#include #include #include #include @@ -1091,6 +1092,7 @@ static int xemaclite_of_probe(struct platform_device *ofdev) struct net_device *ndev = NULL; struct net_local *lp = NULL; struct device *dev = &ofdev->dev; + struct clk *clkin; int rc = 0; @@ -1127,6 +1129,11 @@ static int xemaclite_of_probe(struct platform_device *ofdev) lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong"); lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong"); + clkin = devm_clk_get_optional_enabled(&ofdev->dev, NULL); + if (IS_ERR(clkin)) + return dev_err_probe(&ofdev->dev, PTR_ERR(clkin), + "Failed to get and enable clock from Device Tree\n"); + rc = of_get_ethdev_address(ofdev->dev.of_node, ndev); if (rc) { dev_warn(dev, "No MAC address found, using random\n");