From patchwork Wed Oct 9 16:38:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828832 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A9B3CEE332 for ; Wed, 9 Oct 2024 17:08:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=RXa2VJQ8Fls05TpaX244UmA1ctsFhfXZXCj7XwzjBIg=; b=XBvVr6u57Eop1paDnEATb1lTiW ic6Cuy+pqSAgO4KcRcop0iGEW8dwRX1OUap06ITYtxgMYhO0AHye4kRMRil3mendiLFXuQqO7Jgd6 uY4hXey29Gb/hlYsECigUaGHvEXMdsREOlrW63crO6d53ZPmBEgd8ob54g5Oo07dVRCxKOll9ir3N 1vvUi4x0rOrzjE7Zkjh6zZYd2WNcVr9TqdO0mkN6XjeUHxsgTY67CYStxnlUTzbpYA+VI/9RJ7WjO EhW5Fj+NC5nnpOJM1CTrscc5DEBPSsPuJYYBbMbIxKbO8R7G/s79bxQz4ErzhD0iRwNVp0ONgjpsi awBNu0fw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syaAs-0000000A7QA-2Tvz; Wed, 09 Oct 2024 17:08:34 +0000 Received: from mail-bn8nam04on2054.outbound.protection.outlook.com ([40.107.100.54] helo=NAM04-BN8-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZiU-0000000A0WQ-3A7K for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:17 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=rpP6IA1O5rChIeAoYe06F/b77d/Wmg4VHylR7DquPzP/vs+Wv9MKh+Z16Dn5aedKw6AbEAp3F431YA99BtEj6OFqKUODsmXjiGuODL9nLv8/KvUHWejuAQxFqEEIdqQkztt/PSZJ+gljw69jTNBTK2frFsua5z5BsW2DwinZT4CH5eGad2GKKXOgX4bG+IrhR70Bo5evnGQfwE1tOJ+Nbzsl6UoFQdWSebO7b1a6ZF9be9KzUWBFcD2lhLhbjnv73PMZy8a6G4zlXm5N+UjoCuTAs8Q23louj1gKAeMC8tEQSo3YapaKkaa6ObM1hi6RcmDX5gOEqnbUngaX9Y1N5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=RXa2VJQ8Fls05TpaX244UmA1ctsFhfXZXCj7XwzjBIg=; b=UYl5dFZXH3ojNBvOsdzVR5iRH2qwJd5ajdOLyVgh6c31eXgeLm/Pj99Y2Y9pjOvRngudpdeJ9DSqadNct7TF3Sq/1B1XO9YFD7yuE1+N4OscFljKl1YM1u+MryWeS2hzbcNyvXsQx2sPmsPJI5VYzHQcqRO753MRahdNZ+OyrhUV9XVhw1KSitwJSnM+I6vICkIH3Qjkmj7sqrNgjSghFs/zzjFMkQTfhQPYKyCdao7Ntmqln25SK4IH2xTwgOsZdsFs0DW8DdolGHEAcWAuZ0IfCvUPI/n/+ZjFhdtbWkxikvtPU5SrMI13Cv+XEwg50QP3Vjabobt2gxNDJaiIKg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RXa2VJQ8Fls05TpaX244UmA1ctsFhfXZXCj7XwzjBIg=; b=TQs0yl0sc282WuZftAojfHPa5nPQY9j5mCtF0g59zmxbOknhA7hDxxxrSpnvmTRwpgGF2dA3q39brcFxqCb9AP5WieMsYzww6HHJMx+5qwYpuhEC6bWUywwU49JSKOyDRWtCPTqBcNYOxoQL2V3rgOmfYNI2TLUwNzlSV8klktJZA2gTvHLMKIzkpymfxv/Rbv4H1iaB5LNPSAcR56Pn2K3P0kz1fBF5h2+nIZ3FsTA4r42Q73XOn7YL2eC7KUeuoi2jqg5g+uEdeMP5dACB9ugGlgVS5cOKplup56QYAfsDGeADzsZouHoO1LUqlj4WvDMFFQbRS3G9+/Qi5Ht5rQ== Received: from DS7P220CA0010.NAMP220.PROD.OUTLOOK.COM (2603:10b6:8:1ca::8) by MW4PR12MB6900.namprd12.prod.outlook.com (2603:10b6:303:20e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.18; Wed, 9 Oct 2024 16:39:04 +0000 Received: from DS3PEPF000099E2.namprd04.prod.outlook.com (2603:10b6:8:1ca:cafe::d7) by DS7P220CA0010.outlook.office365.com (2603:10b6:8:1ca::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.18 via Frontend Transport; Wed, 9 Oct 2024 16:39:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by DS3PEPF000099E2.mail.protection.outlook.com (10.167.17.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:04 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:38:57 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:38:57 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:38:56 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 01/16] iommufd/viommu: Introduce IOMMUFD_OBJ_VDEVICE and its related struct Date: Wed, 9 Oct 2024 09:38:13 -0700 Message-ID: <556347d2e69e8b236ec946a93132181385344d4f.1728491532.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E2:EE_|MW4PR12MB6900:EE_ X-MS-Office365-Filtering-Correlation-Id: 31dde2ea-0a2b-4962-37b1-08dce880e313 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: Yh/feIL9Pam1eaNXAiTZ/JfzsClKom6cEoIXFqtWEw7jAmLWlLy/WC+s6pexObjAAtIoeNRV+y6ArZ5t9iX3ADguZXosAWV/JQ2S3JDqwtX+KdklsRGZHPOf9/YkHWUaL9CI9psz+eE73n9aeYq3w45eQxxvhJArfQSE9bAyp6n4gX/MbN3t9Xe8zSZmTvL9PNejA7H+xDNX1wa6b+mF9uhuTNzOM5X8x2tmispGnHqMWNXedmy8hyUt9/85qsMkOXwxehljDkpDNmAk/dchpjZV7pFrYRxDdWG7cpmeXo8G5P/zIHDDROVSjjaqsZMJ6FUy8QzyrbOV3WFpqdgfYTnoJJhtPmsZjOoDnQRHezhe6nGRpZxAU3+GJ8vcNaJtizRvMEx1RY5PBjMjyMa67eyOY9T6m1aYz0+SebjDv59oietp/3p+8OmXD5UiJuYw5vban5xJeENblMqHttPTyHwifQzeFP67Bg/abc3ruXAgUSgHgDrYYIPrh2HjyPZ3XA7w6PF8sqDisqPk4P5x9aVw0its4oRkA/6l94sKEbAwxlBhll0jwukWr8YTZIba0/dGy/l4qDvEoa7C/HZZUyOth0EEm2KD03d82XDMADn21pCO295kpoi15kiHPwCo/rm4oAxoefn4EKz6oB0InbQOF3aB97zAirXAbMuGvYcC99TNgADUnxctzSvSYkg69SH46/og6MEKq/qWpiUDUiO7T8zj8m/VuBlfNX0dDrIJdFYRWIzbWcV14bXhxEeT4HMK4DQxROTBzV0pF9wI94wZ9NP2uZ26FdP2YHdlX1+Xb7G76uWtNeJbfMFiFO07WZyaBqqmLhv0D1mk/1BTQKA8vsTcgw5179urqWm2P0dTM9ELMmq4txEW4Zvj8N7k/3uE1CDhb7nEbw/Kc6wk16oMCJJvPYzEfapUvfxWYBVIBK2yV7EcfGH5K4yVcRUOM3PDdpCglkZnEM1f+FC6YsoUeBtteEB7cgPaLKGwpKX1uj8M3FRwVIMHTxhYmZrpH7BOUDt80BRXMg8a0pk3doTXoaBR6CcfQsk0Vj2rPnKUsq1nCayXXun31lHn8Sg5O2UYadWQ1+NubogLCebDfKMbqYYa6TaNDW50RP8JJ7PA1IdqJu4p7Zit81jrJyIjzQhYa19XVIGRd1iKwrpJo1OkG3zu6ACKXd4x1/uki7jkgyOEnv7X/6JD8wRHdGDdRba61AnMtBTmLfP81RniSDKzhK1dFMgzpRITq89yHH1DP7VD8mez/EY1iID/9sETJQyumN/V/Vop+YgE28y5WSk9S+QqLJgQwkFzQZ42nXS1/EM4umODlARbWAbxIptFYmrudrFd858ai/m1yLY2mqjmfPDN2Et0nC/EFkABRTfBce2jreMkeCo1aKGdcWuD X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:04.1663 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 31dde2ea-0a2b-4962-37b1-08dce880e313 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6900 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_093914_915551_90631344 X-CRM114-Status: GOOD ( 15.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce a new IOMMUFD_OBJ_VDEVICE to represent a physical device, i.e. iommufd_device (idev) object, against an iommufd_viommu (vIOMMU) object in the VM. This vDEVICE object (and its structure) holds all the information and attributes in a VM, regarding the device related to the vIOMMU. As an initial patch, add a per-vIOMMU virtual ID. This can be: - Virtual StreamID on a nested ARM SMMUv3, an index to a Stream Table - Virtual DeviceID on a nested AMD IOMMU, an index to a Device Table - Virtual ID on a nested Intel VT-D IOMMU, an index to a Context Table Potentially, this vDEVICE structure can hold some vData for Confidential Compute Architecture (CCA). Add a pair of vdevice_alloc and vdevice_free in struct iommufd_viommu_ops to allow driver-level vDEVICE structure allocations. Similar to iommufd_vdevice_alloc, add an iommufd_vdevice_alloc helper so IOMMU drivers can allocate core-embedded style structures. Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/iommufd_private.h | 1 + include/linux/iommufd.h | 31 +++++++++++++++++++++++++ drivers/iommu/iommufd/viommu_api.c | 14 +++++++++++ 3 files changed, 46 insertions(+) diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h index c80d880f8b6a..0c56a467e440 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -132,6 +132,7 @@ enum iommufd_object_type { IOMMUFD_OBJ_ACCESS, IOMMUFD_OBJ_FAULT, IOMMUFD_OBJ_VIOMMU, + IOMMUFD_OBJ_VDEVICE, #ifdef CONFIG_IOMMUFD_TEST IOMMUFD_OBJ_SELFTEST, #endif diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index 069a38999cdd..510fc961a9ad 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -75,13 +75,30 @@ struct iommufd_viommu { unsigned int type; }; +struct iommufd_vdevice { + struct iommufd_object obj; + struct iommufd_ctx *ictx; + struct iommufd_device *idev; + struct iommufd_viommu *viommu; + u64 id; /* per-vIOMMU virtual ID */ +}; + /** * struct iommufd_viommu_ops - vIOMMU specific operations * @free: Free all driver-specific parts of an iommufd_viommu. The memory of the * vIOMMU will be free-ed by iommufd core after calling this free op. + * @vdevice_alloc: Allocate a driver-managed iommufd_vdevice to init some driver + * specific structure or HW procedure. Note that the core-level + * structure is filled by the iommufd core after calling this op. + * @vdevice_free: Free a driver-managed iommufd_vdevice to de-init its structure + * or HW procedure. The memory of the vdevice will be free-ed by + * iommufd core. */ struct iommufd_viommu_ops { void (*free)(struct iommufd_viommu *viommu); + struct iommufd_vdevice *(*vdevice_alloc)(struct iommufd_viommu *viommu, + struct device *dev, u64 id); + void (*vdevice_free)(struct iommufd_vdevice *vdev); }; #if IS_ENABLED(CONFIG_IOMMUFD) @@ -103,6 +120,8 @@ int iommufd_vfio_compat_set_no_iommu(struct iommufd_ctx *ictx); struct iommufd_viommu * __iommufd_viommu_alloc(struct iommufd_ctx *ictx, size_t size, const struct iommufd_viommu_ops *ops); +struct iommufd_vdevice * +__iommufd_vdevice_alloc(struct iommufd_ctx *ictx, size_t size); #else /* !CONFIG_IOMMUFD */ static inline struct iommufd_ctx *iommufd_ctx_from_file(struct file *file) { @@ -150,6 +169,12 @@ __iommufd_viommu_alloc(struct iommufd_ctx *ictx, size_t size, { return ERR_PTR(-EOPNOTSUPP); } + +static inline struct iommufd_vdevice * +__iommufd_vdevice_alloc(struct iommufd_ctx *ictx, size_t size) +{ + return ERR_PTR(-EOPNOTSUPP); +} #endif /* CONFIG_IOMMUFD */ /* @@ -163,4 +188,10 @@ __iommufd_viommu_alloc(struct iommufd_ctx *ictx, size_t size, struct drv_struct, member)), \ ops), \ struct drv_struct, member) +#define iommufd_vdevice_alloc(ictx, drv_struct, member) \ + container_of(__iommufd_vdevice_alloc(ictx, \ + sizeof(struct drv_struct) + \ + BUILD_BUG_ON_ZERO(offsetof( \ + struct drv_struct, member))), \ + struct drv_struct, member) #endif diff --git a/drivers/iommu/iommufd/viommu_api.c b/drivers/iommu/iommufd/viommu_api.c index c1731f080d6b..8419df3b658c 100644 --- a/drivers/iommu/iommufd/viommu_api.c +++ b/drivers/iommu/iommufd/viommu_api.c @@ -55,3 +55,17 @@ __iommufd_viommu_alloc(struct iommufd_ctx *ictx, size_t size, return viommu; } EXPORT_SYMBOL_NS_GPL(__iommufd_viommu_alloc, IOMMUFD); + +struct iommufd_vdevice * +__iommufd_vdevice_alloc(struct iommufd_ctx *ictx, size_t size) +{ + struct iommufd_object *obj; + + if (WARN_ON(size < sizeof(struct iommufd_vdevice))) + return ERR_PTR(-EINVAL); + obj = iommufd_object_alloc_elm(ictx, size, IOMMUFD_OBJ_VDEVICE); + if (IS_ERR(obj)) + return ERR_CAST(obj); + return container_of(obj, struct iommufd_vdevice, obj); +} +EXPORT_SYMBOL_NS_GPL(__iommufd_vdevice_alloc, IOMMUFD); From patchwork Wed Oct 9 16:38:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828831 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9CB6CEE32D for ; Wed, 9 Oct 2024 17:06:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DelhEmlnyMPfXXgn2PlMEYi6TuNVLiyt/1iWyZikR8w=; b=1BwO7enRhPcWBqJI/lzB9as2lb dlGZ7vZKh0hC1IL0ZMB4EViUdG8wSPJPruXy2VCcAErFTjEkkjPgEGAXVT+F8X4WR/pJaKIAD0CEm 1zYSDONEIjVqaMG7E0cclgcMrTa1Cj76TsrDHv7no0/bzP2uE5QoO8V3ehOVNyoLkrYv6NUJtdh1M LHSZBH6JNqKi+MMvkbxsVn72oPJ0wCyDGJwkNpzyd+yO2M60WhpVQXuJf8h7hkL7IXQ+huqVWnWYR 0nxwyWT+/64sKgkeOmmXLOw+a5olXzrGh0gDhxWUY3tQbZW1zXtwIB09eVI+pdBElgBjcqZO8VF9e fACnZcbQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1sya8J-0000000A7DV-2gNH; Wed, 09 Oct 2024 17:05:55 +0000 Received: from mail-co1nam11on20607.outbound.protection.outlook.com ([2a01:111:f403:2416::607] helo=NAM11-CO1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZiU-0000000A0Wi-0bFj for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:16 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ZkiPdGbo6BA7Xxyw4VmuZUTaoKAs7UQZe6YxxTSMaIUu2RCfkQdzxifBVuIV2ko2Ap/HFM5vTBu7ypvNvzOxiTaKSHZu439f5aHCHA7QryynQpoAFdy40N92lIOdJVyV3OrkkFrdcxuoMp0w6uP/669rSyhIWkCmtogwFc7w3/kLZBSxgf9jXrfP/tpRF+v/9KPAUxJMoo1hqOrwB3UpVByZGiRcMXqb83JvkZMa034xKYXHLmMRNlqcmnDlSbMozrBvh2m2JF7wBnYzuW47mloq7CmD0d0ooTgnT0Q166MmiZBXxkGhad3+zFlYDnzf/Ujg9n98yDr++2qRqiUvLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=DelhEmlnyMPfXXgn2PlMEYi6TuNVLiyt/1iWyZikR8w=; b=dG6g1+ZFPVmp+cZP/WF79vnWsfXL3+W8RUYgiSEVqSIBoDum/rQ8MJ80JfIGrt30MdwwJUHOW8v+90rURItyBWDFKEWieAezLQZWIH1nJ04QI7wz687fWG/Ulf1IN1FyVX3j+Oyob7gsc5d+7V7dl+37H0Uwvjd3pEZwpiM/LzR3Sehl4AX5LoeMIxMpo3uyH7ajbr6k4CgKAITGhLP1bbkVByiVrerYokHPZBYAbWHx1Ej8nxNXNg5mIR2vGUKCiiRULDpv6xOOxGHiEXBywAgtxCOSnmiiMysbTvnqvymfw/tklbEuMUc2VltjFQJVgoipeanZ3CSubbLrw9UVew== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DelhEmlnyMPfXXgn2PlMEYi6TuNVLiyt/1iWyZikR8w=; b=SdNEsAvBX1v2GnvLAVBsNOlYkgACmQCxTDvWSzej7EQhC4nNMmwxcFVEvSTSZ0H3AYYD7LAwU3PI7rEnV3O2vsv3gkypN3EuDpujjMDk1RbVqZWBLzYMRPlL27IYSCVCGdbRpGp7ExcHKH63n/V+NawKO/NVacZGEdj/FCEXL/5Ezyx8lloiuiw5NHA27/KZAGendwlGXuLCIFe2Pt7YfR2AW+BHJ/0TVxX6XgAUsWEvlj4XnEnb6wkOoDwTzgvOS/6A9WDqlWeKxeZ8sPBAtZEWbNBHvAg+kpwPHpEJORRfxrhcBytz3ACWr9bDB81YZlRDvYGUKyiUWE25+fCyxw== Received: from DS7P220CA0007.NAMP220.PROD.OUTLOOK.COM (2603:10b6:8:1ca::14) by DM4PR12MB6422.namprd12.prod.outlook.com (2603:10b6:8:b9::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.18; Wed, 9 Oct 2024 16:39:05 +0000 Received: from DS3PEPF000099E2.namprd04.prod.outlook.com (2603:10b6:8:1ca:cafe::e1) by DS7P220CA0007.outlook.office365.com (2603:10b6:8:1ca::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.18 via Frontend Transport; Wed, 9 Oct 2024 16:39:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by DS3PEPF000099E2.mail.protection.outlook.com (10.167.17.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:05 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:38:58 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:38:58 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:38:57 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 02/16] iommufd/viommu: Add a default_viommu_ops for IOMMU_VIOMMU_TYPE_DEFAULT Date: Wed, 9 Oct 2024 09:38:14 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E2:EE_|DM4PR12MB6422:EE_ X-MS-Office365-Filtering-Correlation-Id: 16f46474-795c-48f4-9034-08dce880e3ee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: bAnycWOBSR4K8bXxQ/Y25uwvnTBzP6IfroeClhTW18uM6FqMBld4/gW5iRleO3TUn3Iyf8oW5v/0P6/54pLTSW3r+s2A6+AyvMoCLfwrRU25mdDvH9p8KLs3Mrs+uDtywz3VGbj6i2+UsDy3KrAPMnoE9tUbY5kewXl+eXWa6wNUX5oN0maXF2FSGXgpRCHBvARCukfpbt4m5JOCankilmJdN4fx9M+weTJOKJjRssDuywhC/H0kRFVX7MOwX61jWsK9ix2bjDYiSakRGH89xnwkQ6Gb4QjhPxrDeqDh/IPphb1qIgobM+ALHZzwLGVaKD4xSLxuupWpE3MvbcqHdAB3rN5kzIdigT2XqrY8SUciFIppP8IK4eYEFAp979MohgjhsuXhnEPMdCZh0p9VfpAyojJOXa4AKRAtlWIGYEe26rV/7uEoDroSHLUGF3Xlu1wrDlY0FFdoxNRClHrwIWY2vWQjVy2MnAZz/QqDwq5yg8c1EeAd6P4xHpEjT7IkMKW9caWid+wrWF7mv3x4Oj1Y5xf68Thu+UNc0IvB1CO0OUnArcgpBWYEjw4/OycyOxVfWVBVadb/4yItSXM0OLI6Nxwkp4GuavXoKBK9N6a/bC2y8iiA2HwR8kwsGfIQHLnKVDUYJGubvzBrKAYi1l4xzKXLdNBzoN+OsP3EdlQ0mPEke9xBJX/nyK7Ka6/QRxsOezg11GtkbwCqa+rHKtGlKU8pj9nDY0lbWfCDpucUL2nDx3uMPo6Wa6DPdmnu8O4HabBtuOVRCH7rJLyHOdUo/KTRklgFrj1YHEHD99eVxEytTGRkDZucemMmc6edmKz2UochnIqn7OaL/dZFq/GPbnMcrseJEQtrWurA2a2Goziw8o0WhBwjr0XhEffBqTLhR9QMIPC+R5soN/jA+EYO7g/Gb9jKC3e6JvgG7o0WOripcWof6qNJ7RSOuhak5Gy5AGL4X/TAHI9cV3TMYntemsUs/xjlx8J9podLkcfjWQKEpeyBEAEb5fZ7345RNfCWCbQNZFKSd14bg0h6VjLf9qjxWp2/6miYaXbe/sFG0dzWN5N5M/GEk/7UxO3Si4LjGFgJvQ8nBqd9hWpD+P8kuP+1yiCeY5jWeeFRacfDUrRv5WSNHKV/AeM6gz4nxsCoplam3Vx5w8Z8fNpS13xDBxyIcM2EIlXpuVP3pRuKZ384oEdW+IHxG2NTR6yFolsBMSG3kJTTdCwJoFSv21qcJwEVTLgvQkJKoj+R2QO8WCjQQsSICTyM/av7XfJtT+Z7yqDE6p7bKeuAf1OPhSoeHgYIp5cnVnuJSYh82Oshe5YB+Mq8L/et+Yz2tLhVv1F913V3oyP7tWlMsEMLeNK2xDTghPYYt4SZ4nXI7ZzQwMXGC5+1Gj9bgz3Tu2ZS X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:05.5881 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 16f46474-795c-48f4-9034-08dce880e3ee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6422 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_093914_585870_1AD4D21A X-CRM114-Status: GOOD ( 16.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org An IOMMU_VIOMMU_TYPE_DEFAULT doesn't need a free() op since the core can free everything in the destroy(). Now with the new vDEVICE structure, it might want to allocate its own vDEVICEs. Add a default_viommu_ops for driver to hook ops for default vIOMMUs. Signed-off-by: Nicolin Chen --- include/linux/iommu.h | 4 ++++ drivers/iommu/iommufd/viommu.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 9105478bdbcd..1de2aebc4d92 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -44,6 +44,7 @@ struct iommu_dma_cookie; struct iommu_fault_param; struct iommufd_ctx; struct iommufd_viommu; +struct iommufd_viommu_ops; #define IOMMU_FAULT_PERM_READ (1 << 0) /* read */ #define IOMMU_FAULT_PERM_WRITE (1 << 1) /* write */ @@ -551,6 +552,8 @@ static inline int __iommu_copy_struct_from_user_array( * It is suggested to call iommufd_viommu_alloc() helper for * a bundled allocation of the core and the driver structures, * using the given @ictx pointer. + * @default_viommu_ops: Driver can choose to use a default core-allocated vIOMMU + * object by providing a default_viommu_ops. * @pgsize_bitmap: bitmap of all possible supported page sizes * @owner: Driver module providing these ops * @identity_domain: An always available, always attachable identity @@ -605,6 +608,7 @@ struct iommu_ops { struct iommu_domain *domain, struct iommufd_ctx *ictx, unsigned int viommu_type); + const struct iommufd_viommu_ops *default_viommu_ops; const struct iommu_domain_ops *default_domain_ops; unsigned long pgsize_bitmap; diff --git a/drivers/iommu/iommufd/viommu.c b/drivers/iommu/iommufd/viommu.c index 3a903baeee6a..f512dfb535fd 100644 --- a/drivers/iommu/iommufd/viommu.c +++ b/drivers/iommu/iommufd/viommu.c @@ -44,7 +44,7 @@ int iommufd_viommu_alloc_ioctl(struct iommufd_ucmd *ucmd) if (cmd->type == IOMMU_VIOMMU_TYPE_DEFAULT) { viommu = __iommufd_viommu_alloc(ucmd->ictx, sizeof(*viommu), - NULL); + ops->default_viommu_ops); } else { if (!ops->viommu_alloc) { rc = -EOPNOTSUPP; From patchwork Wed Oct 9 16:38:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21361CEE332 for ; Wed, 9 Oct 2024 17:12:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3jA11bv8t/1NmA3vYGVqYtdoZIwtXJymgG7aJf9h0vY=; b=2qqOuiOBtX/Ufd28Pwjq+IGc2p YunRpCJXntgOQBsPJRIPwstFiRznD+G+aGRiuffsY3bx0vbrdmFsRwuP9F8YZV88KMHTacAliTHZu 6rWjv1b9kOStrhOXhofvUFAFXckmFWBkEvrfF+Ld2nqfHToX7xXRJmFucncDiEnYZ/RkWICRxQWxP R+HGyEvLFQvOv4a0IoKLMQQoIkhsWp6+2vrgFTpxSyKgqA1L6I2aGVupCXqEc1zIZeAkspaBXwiH9 676X7EfTBprh97V2d5GQ/1ewyB6GE7uluTaqVQDuGK9wIH9QX9iOiajEmllHPw9GVBXIKx/dzwswE smuUpWTg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syaEk-0000000A816-3hfM; Wed, 09 Oct 2024 17:12:34 +0000 Received: from mail-dm3nam02on20622.outbound.protection.outlook.com ([2a01:111:f403:2405::622] helo=NAM02-DM3-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZiX-0000000A0Yv-06Zm for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:18 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=CNfagPiEKfCkBnpbP3xpAUFzLjYWdfNGHJwWs0EY5mJeV7/z8Y3W1lWgZwmGM7XT7bAV//9eAfhx3zuRe8MVdVdt2v/9ZXjUVLNnNDeq+HqfT/KolIFAKcnz95wP12kLlazdk1boVXGkVdSVnmFCGqF7dXCSnuVtz4arOtYVwB67GgGL+MEKGQL9BvJ/urZwhJLa0znOOjNtl0boNMKYSSodKTMH+t40RNEuwF8ebxDBJVeu6PCyMu/Oec1a9X7CAISIsr7ihkQPHhuGpA2snpbW1xhaz6AAPPQ/RbMraTaWkKCd1D1f7dP8jWcACPsFRcYWUAJiyYKKGSWk/wCPAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3jA11bv8t/1NmA3vYGVqYtdoZIwtXJymgG7aJf9h0vY=; b=GGrQnkCeF86MKl7vwnDEHOo2wrYhvBmFRM3DvpjdfcgZcZVJObaHXYZz5x8R6BOp0wUEboWzK/D271l0JB+4S+FF7ucDGIEQiw2T02AQZO5ZOhZkSh61Ilwy32rMxuIW89LGoRUNqQQ+sI0zX55OxvZW6SKDDHeaNcv5yXjcFtKYaamTh/nTo1waxNJ4ZOJMTZQuYBCfc12HD2B96q34NydBbVKsB/gGv9CnBTU0zwMzMmXgblPVxCstF5BedUKlaoHY3/96mZjsymfOtGHSBiEzSNUce4WBAxpR3NqTogzQyaF9TMs7oY/NVP5BOKmHRbKt+efHmQ/gwLsZn/1Asw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3jA11bv8t/1NmA3vYGVqYtdoZIwtXJymgG7aJf9h0vY=; b=HXM85HWMsFb9HUj0ncyvpXgbp+9hAcNoy3bhusMgzMHV2+t0ei53ReUe62/h59wtPB+3N8gOl6yTDstBeOJ1QU3iTG13pSt4l+AzegUW7gIAcZEGP0IjbeKXo5sMj/hvhPJY2GbE7ldIgzOtMtHg2BAceOPnk71jIc7vGIus0MvPbs0aF9juggwCP2Hf4ZJ+dYhV6tKxBUdVVHklaRxexnEzXZspwRHq0SRLDOH5MZp3gee9htGI5D8EPWR5fRpikJ9xhGMRnwfyBqbkcdTZvRJWfpqfOF4yLbWrb2tZluLC90j1q0l/Si3p8LJkORh4K72cnzYqJUZXvFfkRFwPVw== Received: from SA9PR11CA0030.namprd11.prod.outlook.com (2603:10b6:806:6e::35) by PH7PR12MB9075.namprd12.prod.outlook.com (2603:10b6:510:2f0::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.23; Wed, 9 Oct 2024 16:39:07 +0000 Received: from SA2PEPF00003F68.namprd04.prod.outlook.com (2603:10b6:806:6e:cafe::43) by SA9PR11CA0030.outlook.office365.com (2603:10b6:806:6e::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.17 via Frontend Transport; Wed, 9 Oct 2024 16:39:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SA2PEPF00003F68.mail.protection.outlook.com (10.167.248.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:07 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:00 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:38:59 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:38:58 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 03/16] iommufd/viommu: Add IOMMU_VDEVICE_ALLOC ioctl Date: Wed, 9 Oct 2024 09:38:15 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F68:EE_|PH7PR12MB9075:EE_ X-MS-Office365-Filtering-Correlation-Id: 71f1f6b5-af7b-4f63-2b08-08dce880e502 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: gPdF+C2WtwMvliRKQDJ0LoTT2isXYldq7xVHwhlL7W73qNG2vANo9FI3EHxjQ6Dw0myytNRRBzdv1h7d1uhJw+ard/bnbiI0zFlcub7J81Wnt4vI7v24ZICX/YtJj2bFJ+8v1uWpglRJTmFmoBrmgHzBPvqbY8vQrW6x/nIze5ClouVYU/bwnENc9yhoq+Tx86SNBv+ehm7F9zEOUEb7af8Pkt3P7t+dpHTQMLoNhtfQommuhevbTcgqLu3Ea9ePUZYIoS7N0IY1D3+zaJrNDY6jwhrp+fJuNOrEP8jLbFdgVIARAMZHn89UbIyLtF4jx38uwKeGrS/6zzUpR8t2st8IeBZlAhMrBeEujT+KgwlY3V3pZqNAOHSapS218zsWtT+FXt1IeYyvcUOmH6mHbmr3SBH/jIByuokkbs2bfu9T7XhbBcVpW8TCwQ/DcVoTbPVpJl3jA59A7dUx5RY7tY7Wyfi24dHprckHkUVe51T3sEFZULtR2B15Stu0CsEfatwjTY2ahAOm6RcCb+yxkGGMZiqTVbnTgfSM4oCvIA+2JIIh4hw14wopOy8Kugqxou79W9j6Bk3wdUjVZCGTyhAUeXsNAPG6Uz9VUatGiB6RHA/BcfYFracaknsTMRb1mPcEEMTUO9yiVnGhuoIhRpP9edxA7HNe2DTzOe1TeZWP0UrxVY9Xw7n48JCReIB2craxB9PtZ2PJ+r9jQ/SDuXc9RwlSu5DwiG6pxHCic8NB+G/3+DASQ2Lvz0Ggb/FMcFhAxQpqZpOlfxJkaD1ECX0h5W4o8yDU0oBGINE7kaPKHf+OagmX5FgsFU8sBJcaYySVP5aQVAVZoH0xc8vqqkkDWsgbzaS6VPhtGB0V17MuPDSEdKlZTMZpOK1aK+WxQ6srln2gFIGfxTAhi8USnKd6/mhtY4b++eFYTS/QmIJAB9QOa9atLKSz7D1C1ldXKZcTLkeN19qy35sxWA3nxPXbwlQF254oOlc6oP0AQIqn76Dt/UbjuIZpVZBv+aBTu3GeE/JoxaeMaPZG/1kaLvt7Glnwwd0sPvCVmASvfPnOxKJv2zZ0T6huelALL/kbsc5+N7QTkFZEQcJGxC+2n4OQimmXwnYyy7LmSXfyeU003FQu3EBexHvJ16d+bvGOTyHS1bT1OH30Mau7njwogcC4iZtV2GCKB2cw+/r/ViNxHM3o6LRiqbrX3HHmNY3qM73a5/I2bHF4abdy6x2S/aRD+o6N601Nk4+t4KWSH/+RD6vtu6bm+L09dDasSZseBOohOwvXSmTSLHk4Fb0hRK2+7EDWCsZTrAeAUioR2Q6ab885D4QabtvqrM2rFpdUcwQM8auiFNwv41owlZusEfePpR/zWkvCYpCmtuq9dcj+oZBKZa6dMqig94hkyknP X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:07.3944 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71f1f6b5-af7b-4f63-2b08-08dce880e502 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F68.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9075 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_093917_189966_3DB09C72 X-CRM114-Status: GOOD ( 19.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce a new ioctl to allocate a vDEVICE object. Since a vDEVICE object is a connection of an iommufd_iommufd object and an iommufd_viommu object, require both as the ioctl inputs and take refcounts in the ioctl handler. Add to the vIOMMU object a "vdevs" xarray, indexed by a per-vIOMMU virtual device ID, which can be: - Virtual StreamID on a nested ARM SMMUv3, an index to a Stream Table - Virtual DeviceID on a nested AMD IOMMU, an index to a Device Table - Virtual ID on a nested Intel VT-D IOMMU, an index to a Context Table Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/iommufd_private.h | 11 +++ include/linux/iommufd.h | 2 + include/uapi/linux/iommufd.h | 26 +++++++ drivers/iommu/iommufd/main.c | 6 ++ drivers/iommu/iommufd/viommu.c | 91 +++++++++++++++++++++++++ 5 files changed, 136 insertions(+) diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h index 0c56a467e440..e160edb22b67 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -409,6 +409,7 @@ struct iommufd_device { struct iommufd_object obj; struct iommufd_ctx *ictx; struct iommufd_group *igroup; + struct iommufd_vdevice *vdev; struct list_head group_item; /* always the physical device */ struct device *dev; @@ -523,8 +524,18 @@ static inline int iommufd_hwpt_replace_device(struct iommufd_device *idev, return iommu_group_replace_domain(idev->igroup->group, hwpt->domain); } +static inline struct iommufd_viommu * +iommufd_get_viommu(struct iommufd_ucmd *ucmd, u32 id) +{ + return container_of(iommufd_get_object(ucmd->ictx, id, + IOMMUFD_OBJ_VIOMMU), + struct iommufd_viommu, obj); +} + int iommufd_viommu_alloc_ioctl(struct iommufd_ucmd *ucmd); void iommufd_viommu_destroy(struct iommufd_object *obj); +int iommufd_vdevice_alloc_ioctl(struct iommufd_ucmd *ucmd); +void iommufd_vdevice_destroy(struct iommufd_object *obj); #ifdef CONFIG_IOMMUFD_TEST int iommufd_test(struct iommufd_ucmd *ucmd); diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index 510fc961a9ad..5a630952150d 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -72,6 +72,8 @@ struct iommufd_viommu { const struct iommufd_viommu_ops *ops; + struct xarray vdevs; + unsigned int type; }; diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 6ee841a8c79b..3039519d71b7 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -52,6 +52,7 @@ enum { IOMMUFD_CMD_HWPT_INVALIDATE = 0x8d, IOMMUFD_CMD_FAULT_QUEUE_ALLOC = 0x8e, IOMMUFD_CMD_VIOMMU_ALLOC = 0x8f, + IOMMUFD_CMD_VDEVICE_ALLOC = 0x90, }; /** @@ -894,4 +895,29 @@ struct iommu_viommu_alloc { __u32 out_viommu_id; }; #define IOMMU_VIOMMU_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VIOMMU_ALLOC) + +/** + * struct iommu_vdevice_alloc - ioctl(IOMMU_VDEVICE_ALLOC) + * @size: sizeof(struct iommu_vdevice_alloc) + * @viommu_id: vIOMMU ID to associate with the virtual device + * @dev_id: The pyhsical device to allocate a virtual instance on the vIOMMU + * @__reserved: Must be 0 + * @virt_id: Virtual device ID per vIOMMU, e.g. vSID of ARM SMMUv3, vDeviceID + * of AMD IOMMU, and vID of a nested Intel VT-d to a Context Table. + * @out_vdevice_id: Output virtual instance ID for the allocated object + * @__reserved2: Must be 0 + * + * Allocate a virtual device instance (for a physical device) against a vIOMMU. + * This instance holds the device's information (related to its vIOMMU) in a VM. + */ +struct iommu_vdevice_alloc { + __u32 size; + __u32 viommu_id; + __u32 dev_id; + __u32 __reserved; + __aligned_u64 virt_id; + __u32 out_vdevice_id; + __u32 __reserved2; +}; +#define IOMMU_VDEVICE_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VDEVICE_ALLOC) #endif diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index cbd0a80b2d67..9a8c3cbecc11 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -302,6 +302,7 @@ union ucmd_buffer { struct iommu_option option; struct iommu_vfio_ioas vfio_ioas; struct iommu_viommu_alloc viommu; + struct iommu_vdevice_alloc vdev; #ifdef CONFIG_IOMMUFD_TEST struct iommu_test_cmd test; #endif @@ -355,6 +356,8 @@ static const struct iommufd_ioctl_op iommufd_ioctl_ops[] = { __reserved), IOCTL_OP(IOMMU_VIOMMU_ALLOC, iommufd_viommu_alloc_ioctl, struct iommu_viommu_alloc, out_viommu_id), + IOCTL_OP(IOMMU_VDEVICE_ALLOC, iommufd_vdevice_alloc_ioctl, + struct iommu_vdevice_alloc, __reserved2), #ifdef CONFIG_IOMMUFD_TEST IOCTL_OP(IOMMU_TEST_CMD, iommufd_test, struct iommu_test_cmd, last), #endif @@ -493,6 +496,9 @@ static const struct iommufd_object_ops iommufd_object_ops[] = { [IOMMUFD_OBJ_VIOMMU] = { .destroy = iommufd_viommu_destroy, }, + [IOMMUFD_OBJ_VDEVICE] = { + .destroy = iommufd_vdevice_destroy, + }, #ifdef CONFIG_IOMMUFD_TEST [IOMMUFD_OBJ_SELFTEST] = { .destroy = iommufd_selftest_destroy, diff --git a/drivers/iommu/iommufd/viommu.c b/drivers/iommu/iommufd/viommu.c index f512dfb535fd..eb78c928c60f 100644 --- a/drivers/iommu/iommufd/viommu.c +++ b/drivers/iommu/iommufd/viommu.c @@ -9,6 +9,8 @@ void iommufd_viommu_destroy(struct iommufd_object *obj) struct iommufd_viommu *viommu = container_of(obj, struct iommufd_viommu, obj); + xa_destroy(&viommu->vdevs); + if (viommu->ops && viommu->ops->free) viommu->ops->free(viommu); refcount_dec(&viommu->hwpt->common.obj.users); @@ -72,6 +74,8 @@ int iommufd_viommu_alloc_ioctl(struct iommufd_ucmd *ucmd) */ viommu->iommu_dev = idev->dev->iommu->iommu_dev; + xa_init(&viommu->vdevs); + refcount_inc(&viommu->hwpt->common.obj.users); cmd->out_viommu_id = viommu->obj.id; @@ -89,3 +93,90 @@ int iommufd_viommu_alloc_ioctl(struct iommufd_ucmd *ucmd) iommufd_put_object(ucmd->ictx, &idev->obj); return rc; } + +void iommufd_vdevice_destroy(struct iommufd_object *obj) +{ + struct iommufd_vdevice *old, *vdev = + container_of(obj, struct iommufd_vdevice, obj); + struct iommufd_viommu *viommu = vdev->viommu; + struct iommufd_device *idev = vdev->idev; + + if (viommu->ops && viommu->ops->vdevice_free) + viommu->ops->vdevice_free(vdev); + + old = xa_cmpxchg(&viommu->vdevs, vdev->id, vdev, NULL, GFP_KERNEL); + if (old) + WARN_ON(old != vdev); + + refcount_dec(&viommu->obj.users); + refcount_dec(&idev->obj.users); + idev->vdev = NULL; +} + +int iommufd_vdevice_alloc_ioctl(struct iommufd_ucmd *ucmd) +{ + struct iommu_vdevice_alloc *cmd = ucmd->cmd; + struct iommufd_vdevice *vdev, *curr; + struct iommufd_viommu *viommu; + struct iommufd_device *idev; + u64 virt_id = cmd->virt_id; + int rc = 0; + + if (virt_id > ULONG_MAX) + return -EINVAL; + + viommu = iommufd_get_viommu(ucmd, cmd->viommu_id); + if (IS_ERR(viommu)) + return PTR_ERR(viommu); + + idev = iommufd_get_device(ucmd, cmd->dev_id); + if (IS_ERR(idev)) { + rc = PTR_ERR(idev); + goto out_put_viommu; + } + + mutex_lock(&idev->igroup->lock); + if (idev->vdev) { + rc = -EEXIST; + goto out_unlock_igroup; + } + + if (viommu->ops && viommu->ops->vdevice_alloc) + vdev = viommu->ops->vdevice_alloc(viommu, idev->dev, virt_id); + else + vdev = __iommufd_vdevice_alloc(ucmd->ictx, sizeof(*vdev)); + if (IS_ERR(vdev)) { + rc = PTR_ERR(vdev); + goto out_unlock_igroup; + } + + vdev->idev = idev; + vdev->id = virt_id; + vdev->viommu = viommu; + + idev->vdev = vdev; + refcount_inc(&idev->obj.users); + refcount_inc(&viommu->obj.users); + + curr = xa_cmpxchg(&viommu->vdevs, virt_id, NULL, vdev, GFP_KERNEL); + if (curr) { + rc = xa_err(curr) ? : -EBUSY; + goto out_abort; + } + + cmd->out_vdevice_id = vdev->obj.id; + rc = iommufd_ucmd_respond(ucmd, sizeof(*cmd)); + if (rc) + goto out_abort; + iommufd_object_finalize(ucmd->ictx, &vdev->obj); + goto out_unlock_igroup; + +out_abort: + iommufd_object_abort_and_destroy(ucmd->ictx, &vdev->obj); +out_unlock_igroup: + mutex_unlock(&idev->igroup->lock); + iommufd_put_object(ucmd->ictx, &idev->obj); +out_put_viommu: + iommufd_put_object(ucmd->ictx, &viommu->obj); + return rc; +} From patchwork Wed Oct 9 16:38:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D49ECEE330 for ; Wed, 9 Oct 2024 17:14:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=mmPe546eXRnRwO5Ecz4tLVsC8DfRpXPdFWPF5RSHKVY=; b=HnDh+iORgJSr8zq7gLEYDw6Xgp 9KpTEw819BB4Tu0VR43so67JChCUwuo8jBL15iplwHmaMasYuCpMv5UXd4p4crOLvi8HpC3mXq5yF fCMwEjdIq7pNRvkyLxnSBAdj3p+obh7cQq1i1gvI36jc1dVg7gtZzMqBcKg4SIDotg/XYXxz8hV6Y G7FZiVwSolCBAOm+cGNm4gOjtU5ai8Wa8tp6JUWnDBsH41KBvrfMwIUbHHRa1I4hMEFgxdqQQBHRG VLB5Xo8+RqAHaSioAwimj9l6NTLSI65xQiIvp5ogd0ZIGx/upGyUmEVEwyDqck+zZKwcsZrI6levK RWcvpJlQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syaG3-0000000A8KN-2mom; Wed, 09 Oct 2024 17:13:55 +0000 Received: from mail-co1nam11on2062c.outbound.protection.outlook.com ([2a01:111:f403:2416::62c] helo=NAM11-CO1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZib-0000000A0bN-1Se0 for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:22 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=HrlEX9yzicleVOxQL/tZg/NGrphzS2F59L0EhpEVkAOtC2vQI0we/LTm63JtZjGsDIHoNz+n7cD4vJxefv8uJT29M8JUr1OQv2beHVMDxxxncl1yhHS/TwyrOPDIg49iiWHvIJXdoK+6fAGmKgRlRcAOljQAAY+iaZZnmbCDdr3Mhl8cq/t1wISTuLHSJD/atQ8VWOyTfL7IjNXlaRlQ2a9AGRtejhRe9djPIEfPcMIxPH90NuAlZNpX6HJLpDQR2o+Za1KXyMv5y5GwXO4ehHoNwb4/BPbaXKb/4a24l1X7eftiXZZ80OIjBkK6wTm1anWP5OGYoP+w7+6Zuf/fbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mmPe546eXRnRwO5Ecz4tLVsC8DfRpXPdFWPF5RSHKVY=; b=xdk81qz2FYgV6Jtvh45P9IEJO2KykCcptgTZkOewrv+7wwaQHg1mvU5d9zUjKm3QDk5JrNmJ78oz8W6o4eioSYyKidpdU60XKvxC5M3ffhNzeQuyVUM9OS/5c4SprN5oS732X2cJi7X7vwUS4PW7kjq8cG5DmW/hgjixRj6ULPuPH76rqSMXAli4bk/cJm4g/plvElgwYPPIEB67Jup03kxiL/rEIc7aUg5pdn8acSqLE4LmkbBLT0/sL732673c/kcsLPz6gPCxaW8By4YTY9yGla1IjnW7KfUhb9IAhCAte1PWr3AOpO5EPtiZc/OVtSt6pGn5tSAvB/9Ef3NVHg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mmPe546eXRnRwO5Ecz4tLVsC8DfRpXPdFWPF5RSHKVY=; b=B4JT+4yz/SnAXrmbGkHxk9bU5IsRSr6Ddo5temXBJGBQH04mtO34yXrQ1mYrAQYNM3LmveQjVYAlBAo0CpgHSlpZ1YgLKzX4f+Xm/dTbRK0U6Ium+q65PJ0WX6RWhkHFwHjgCv8T0kah9no2bd4VWWQz3ROYqbvky+1VyVnqsG52fuFC0/1nUO4CzLIIDNrclPZJQiczFXDDXRUIcdfCz0NRW65+V/ugJXyDSXrbcUw41jdGGk1cKd8DD6PjaUy0ZYqABu50lZAlj6021bhZAONY7GZwDCzrCov6ylD/tqKFWfItdt+/XAWZlOQ5tNaV8So3c/vf7FPSuGUQZcjsWg== Received: from SA9PR11CA0011.namprd11.prod.outlook.com (2603:10b6:806:6e::16) by PH8PR12MB6722.namprd12.prod.outlook.com (2603:10b6:510:1cd::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.16; Wed, 9 Oct 2024 16:39:09 +0000 Received: from SA2PEPF00003F68.namprd04.prod.outlook.com (2603:10b6:806:6e:cafe::8c) by SA9PR11CA0011.outlook.office365.com (2603:10b6:806:6e::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.17 via Frontend Transport; Wed, 9 Oct 2024 16:39:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SA2PEPF00003F68.mail.protection.outlook.com (10.167.248.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:08 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:01 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:01 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:39:00 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 04/16] iommufd/selftest: Add IOMMU_VDEVICE_ALLOC test coverage Date: Wed, 9 Oct 2024 09:38:16 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F68:EE_|PH8PR12MB6722:EE_ X-MS-Office365-Filtering-Correlation-Id: 3db9b211-4d67-4c93-49bd-08dce880e5c3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: Fqh9pR2YNANsPPmUqtJ5iZaaWO85JterV0LuN4YF7DOlTEEdZp0tsrZm0ddf4b0GEuF6esiXNU2IEsfn4i4j6bXkLm/7k4jX97WwApTzzGC+KmdJShXETyGX0aNvQI2BQ1RuSzX74d9rtoDILrIrCk16zj4ztjmmD3iGSm/QN6I+4Q3QlDvmuL982pucm9GMWsMd5xTWtyDUZuJZ+C3/qKbWgEVcKWZmqpDFoRk9mcR7hd9kcBzxQBRtnfoi5Vja/9LnYvkvkxEihdo5a3iXw7Tv1YmVgnknVm8F2j8n0ECltY7D2ns0nvT2FtJoXr/xesG5KMIu/FXNxkrHq7gO372Aq6XwJJnT/1FxJ/EbljfCtIaUGQHkdP2O4yr2Czz2HYiElUM2WMg/cb/Wu9laOlulJ2tyWTlOMRpKCE62yu7Z2lgYNWDe32WLsOidnYwYU0Gy+7bcTXx9regQ/R9eK6/0BZcyuoxzx8p0ZNy2WC+ElW3h3msvnt+zdHffEkles4odm1ABmjea2gadOfpiQxC1dgHxna5ItOfj6Jxggu9F64t5T5oPDhBcGpLNzciJVGR7MRkvK7A5Ruj8ho3Orfy1KKr8jx3Upnwug73Y2wbj7SCAv0TVUXwjCOpnPrxkaRc1vn+plhRPc5wog+sx/fbdIFVDUKLWqEqBKbKISoPxTDTEB+4V85J/ZxENjsOL7oMXduPkMmfAkRunOLUgGOKWiTOlWT5qRnSILHSL2V1tzrhTf9+J/aVHcAHk1UGUXXXQv6qiz72PZ7vjPHqFgxPb/dJvBlYdxeXXFnVGYNzdID4+H1HZqBEQYG8T89cGf5e5/sk8ZE8eTCWX0oOS62HvZG0Q+WUYFj97nB0rhpbupOuEHytVH9tJ5yoJAprH4FbHd6IeaW1WNEPs1tOJ/RIWRmLC3WFvcrOfC21hH/BSlolJBUcAxpLofmKqM/jiHFl6aE0kGcN1Q+nlhBQu4QnDSfqZ2bw9iw8OtwjhL0QNZCUbrlF/1jgJQ0dLzIqSl7pWbyu3KETsXhz4+dRfEVSLr7SmjqunVxHqMfKMoiUpmh6VIFzEnj2BAXyprWEnsMig46vQ8CbA4Acbc+VPSoNzunHCKgMUKbARm82do+vz646Mv/QWG9OSItioASjo/dw4+FTcjS2KnWY//EjGAa3fssy1gSAYLq85Zu0cBTvWvS/fH0acnXbsDJyrtP9kvHC0nvrPugh61ptZr5Dy18zfOTTcdw/eXZ6NrgX0cg2wB/Suf2XweZ/H0ohFSzFBMcDp8HgmLDzNTwz8tfp2e2Xbb35hTgv4Wiz+TJQEu5DIXz4SGt5HcYBFyCzoo4B4yRr1fWi7vmhbPk1LoZ7IHlR1HG9D6dKCrXiyciNqvvg= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:08.6600 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3db9b211-4d67-4c93-49bd-08dce880e5c3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F68.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6722 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_093921_416691_74C802C7 X-CRM114-Status: GOOD ( 15.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a vdevice_alloc TEST_F to cover the new IOMMU_VDEVICE_ALLOC ioctls. Also add a vdevice_alloc op to the viommu mock_viommu_ops for a coverage of IOMMU_VIOMMU_TYPE_SELFTEST. The DEFAULT coverage is done via a core- allocated vDEVICE object. Signed-off-by: Nicolin Chen --- tools/testing/selftests/iommu/iommufd_utils.h | 27 +++++++++++++++++++ drivers/iommu/iommufd/selftest.c | 19 +++++++++++++ tools/testing/selftests/iommu/iommufd.c | 20 ++++++++++++++ 3 files changed, 66 insertions(+) diff --git a/tools/testing/selftests/iommu/iommufd_utils.h b/tools/testing/selftests/iommu/iommufd_utils.h index 307d097db9dd..ccd1f65df0b0 100644 --- a/tools/testing/selftests/iommu/iommufd_utils.h +++ b/tools/testing/selftests/iommu/iommufd_utils.h @@ -790,3 +790,30 @@ static int _test_cmd_viommu_alloc(int fd, __u32 device_id, __u32 hwpt_id, EXPECT_ERRNO(_errno, _test_cmd_viommu_alloc(self->fd, device_id, \ hwpt_id, type, 0, \ viommu_id)) + +static int _test_cmd_vdevice_alloc(int fd, __u32 viommu_id, __u32 idev_id, + __u64 virt_id, __u32 *vdev_id) +{ + struct iommu_vdevice_alloc cmd = { + .size = sizeof(cmd), + .dev_id = idev_id, + .viommu_id = viommu_id, + .virt_id = virt_id, + }; + int ret; + + ret = ioctl(fd, IOMMU_VDEVICE_ALLOC, &cmd); + if (ret) + return ret; + if (vdev_id) + *vdev_id = cmd.out_vdevice_id; + return 0; +} + +#define test_cmd_vdevice_alloc(viommu_id, idev_id, virt_id, vdev_id) \ + ASSERT_EQ(0, _test_cmd_vdevice_alloc(self->fd, viommu_id, idev_id, \ + virt_id, vdev_id)) +#define test_err_vdevice_alloc(_errno, viommu_id, idev_id, virt_id, vdev_id) \ + EXPECT_ERRNO(_errno, \ + _test_cmd_vdevice_alloc(self->fd, viommu_id, idev_id, \ + virt_id, vdev_id)) diff --git a/drivers/iommu/iommufd/selftest.c b/drivers/iommu/iommufd/selftest.c index 4fcf475facb1..87bc45b86f9e 100644 --- a/drivers/iommu/iommufd/selftest.c +++ b/drivers/iommu/iommufd/selftest.c @@ -136,6 +136,11 @@ struct mock_viommu { struct iommufd_viommu core; }; +struct mock_vdevice { + struct iommufd_vdevice core; + u64 rid; +}; + enum selftest_obj_type { TYPE_IDEV, }; @@ -560,8 +565,22 @@ static void mock_viommu_free(struct iommufd_viommu *viommu) /* iommufd core frees mock_viommu and viommu */ } +static struct iommufd_vdevice *mock_vdevice_alloc(struct iommufd_viommu *viommu, + struct device *dev, u64 id) +{ + struct mock_vdevice *mock_vdev; + + mock_vdev = iommufd_vdevice_alloc(viommu->ictx, mock_vdevice, core); + if (IS_ERR(mock_vdev)) + return ERR_CAST(mock_vdev); + + mock_vdev->rid = id; + return &mock_vdev->core; +} + static struct iommufd_viommu_ops mock_viommu_ops = { .free = mock_viommu_free, + .vdevice_alloc = mock_vdevice_alloc, }; static struct iommufd_viommu * diff --git a/tools/testing/selftests/iommu/iommufd.c b/tools/testing/selftests/iommu/iommufd.c index c03705825576..af00b082656e 100644 --- a/tools/testing/selftests/iommu/iommufd.c +++ b/tools/testing/selftests/iommu/iommufd.c @@ -129,6 +129,7 @@ TEST_F(iommufd, cmd_length) TEST_LENGTH(iommu_option, IOMMU_OPTION, val64); TEST_LENGTH(iommu_vfio_ioas, IOMMU_VFIO_IOAS, __reserved); TEST_LENGTH(iommu_viommu_alloc, IOMMU_VIOMMU_ALLOC, out_viommu_id); + TEST_LENGTH(iommu_vdevice_alloc, IOMMU_VDEVICE_ALLOC, __reserved2); #undef TEST_LENGTH } @@ -2470,4 +2471,23 @@ TEST_F(iommufd_viommu, viommu_auto_destroy) { } +TEST_F(iommufd_viommu, vdevice_alloc) +{ + uint32_t viommu_id = self->viommu_id; + uint32_t dev_id = self->device_id; + uint32_t vdev_id = 0; + + if (dev_id) { + /* Set vdev_id to 0x99, unset it, and set to 0x88 */ + test_cmd_vdevice_alloc(viommu_id, dev_id, 0x99, &vdev_id); + test_err_vdevice_alloc(EEXIST, + viommu_id, dev_id, 0x99, &vdev_id); + test_ioctl_destroy(vdev_id); + test_cmd_vdevice_alloc(viommu_id, dev_id, 0x88, &vdev_id); + test_ioctl_destroy(vdev_id); + } else { + test_err_vdevice_alloc(ENOENT, viommu_id, dev_id, 0x99, NULL); + } +} + TEST_HARNESS_MAIN From patchwork Wed Oct 9 16:38:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6AB8CEE332 for ; Wed, 9 Oct 2024 17:11:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=MWiiUBD/BDJcXPbCGKX09n29ZrUurzfWk4q0mppQ5WE=; b=iJHJOo8Ehyncr3vNMQniBcWgfe rFAM6lByrqAKNel/8OB3hJXmCTBI0DRnbk4JX4wjXM9+0++8YRJ3LhdbGQdnbIatyiSkw+UBKMVnD OpbBG2MOJvEkwl1ii2I5vNzljxtYIz7+2KdmCqy705BEXG8uUjnQ+zwu7hw9K/cPSgDRu4ePaUPqL qZGwcTRFafb21n6VrJNm+46vQr7fGvD55+w17TSMDc5OKOVcgTEJkntbYWxWD2g8CtZwtpuB8bC7E 6nJ8C7kZZIyrVvSRvz02jmQMm/kVFAxcwMEKw+5vqj97MIU1PlHN9bQWOGbA0QlkG53mfbRSkOAHT Kc1vfVyg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syaDT-0000000A7qQ-1KFh; Wed, 09 Oct 2024 17:11:15 +0000 Received: from mail-dm6nam04on20618.outbound.protection.outlook.com ([2a01:111:f403:2409::618] helo=NAM04-DM6-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZiX-0000000A0ZP-0I1n for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:18 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Xs4wqi3CiNENU8uDSHLvRSwsz086XfivDg0nxPR3VYYTiyc9+4DYqyLAw51KglEKtwzNsNc4bUYOpl+HL47Hm0n3ksoR6FP9qanE8OWs2YDWsxatZHsaJuBM5BPcM8j5EfmTnhZIg34EL8gk2N3Fm0Pr/q6l9M/UVZTe1abfvONRfF64BxS8x1ttpA7YwUgtJU+v7HpwvEq90tQs56ktuUoeQA4eBwi8a9NX6mcDjUP49ZUJy4xhy7kVomBh1IVys6c0C5aMbSwxxzhnY6c0XdH5edb6+UrAKz7+6RTqSODoXkXjU1aO/kLoP2PlRCOfyP5syqfO9c9UDuze+VFoPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MWiiUBD/BDJcXPbCGKX09n29ZrUurzfWk4q0mppQ5WE=; b=jaSNM8Cp1kdQg/StKL8V5UD4PeJxNKzEDtrv6WeQEyoVqMkmZk8b+nOr6rSIV+o+zq8AMluWowu31rYYJWAw6Cg1L6xDolMbxKbizCK4lyWt8H7dS3S+HVWChq3YuBgt1iYbh94vfgfIKYVDT8y0JVB/8R3MJiZ4AE+YTyqUpLsk/l/Lvia6ooHM+d57eKPY/DKT4e8SaA28ICXyxdilxJ+pnDtWWBuW4nbSFAkm4RLOT/H1EX1rB9pAddp7FVZSZhAM1k2DEsdFWsGTMBnFNknFpUpFIarOpnlUkfUqcJUGhydbEpAy5ryuRnG+g14dnOdDv9nCvGMC5tHC2UxC3w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MWiiUBD/BDJcXPbCGKX09n29ZrUurzfWk4q0mppQ5WE=; b=um+lzf/UrjeYsz3unV4AtoE+VCmCc028pTbioFOfqafe8VX5N0lWATNn26OhA+Ta6Re9mx+nUPPYuCUHYcQLkFy+RhsOz+6T9Qrgxs/1/ylFtR5/v7k4u6Hs99ctjyK2hTNu80OJZWooZNxCHtFiaFfZIIDbVFtoaqGOOexmkZff0OrJOU+m54NVscBOhikP3kQZsh8buNWQTj1V36sn6Ox8kJM2Kuk0O6dq5OMU+MPKFD2XStSUezzjtznYMRe//veCqu8zHql+q3HhMrG+W8Tbb9YhSB4J7gsKAfmVuWHinFq+9E3p/WD4+taTCnaQyPSPlGYwejxEoobaKaRaag== Received: from SN6PR08CA0019.namprd08.prod.outlook.com (2603:10b6:805:66::32) by MW4PR12MB7191.namprd12.prod.outlook.com (2603:10b6:303:22d::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.22; Wed, 9 Oct 2024 16:39:12 +0000 Received: from SA2PEPF00003F67.namprd04.prod.outlook.com (2603:10b6:805:66:cafe::a2) by SN6PR08CA0019.outlook.office365.com (2603:10b6:805:66::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.17 via Frontend Transport; Wed, 9 Oct 2024 16:39:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SA2PEPF00003F67.mail.protection.outlook.com (10.167.248.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:12 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:02 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:02 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:39:01 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 05/16] iommu/viommu: Add cache_invalidate for IOMMU_VIOMMU_TYPE_DEFAULT Date: Wed, 9 Oct 2024 09:38:17 -0700 Message-ID: <2b57c2f0721237488d194fb00f9d044d60e3038c.1728491532.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F67:EE_|MW4PR12MB7191:EE_ X-MS-Office365-Filtering-Correlation-Id: a1ae3f3a-62d2-415d-d25a-08dce880e7d6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: O400zNWdGDdrnWTdmwPosu7MwkP9abKytAKJ6yGrUWP0PjxEimpNhNPhnQfH47yNEMGoDTPp5ENhYhZVr9EyVOqUjliu0TXcBJaCLIlIxvG/nqQjl+BkU9GwM8+SdJJKvKeF+puYMId/6+z4OIMR0nWA4Q+YOu0WrmUjjZrLgexJwFMYEnyMK+Tr/rdG8CBqAGuKjOm/+lMWlaYknDvslJ6dXAoViA3Y13uSdTJLn4NwHevAx2rR4sa+FBRUMUR43w4BbMksjGCBG1fgE+cvOwspVM4dIu07rjU0ILsmcBmPMeT6idzVbhb5RD/L6h7uquKS6PJTSgBBRfTyaOVAQh3tjebsPhoTdcEsGSHVozuhj7DtvOUbNLBV+NN1xsJ57zV1uac9KM6VLxlQURChunhnpJyPM7PxSQ46Zbt3ceztqc8Wbl6YnhCwD/S4LkMWohIixbCeYf/sxmSWDRTj14g3JuMVkTDdCNM0/W8Qo/XPMd3gt39ga3W8rZyshDRuu/OzTjeWvqaHMAmMZcbYofrSwrV+64f+cXAJPO0kYR+VN5oovXytBSDapM510ZNvbS4yVYl9xLhHsM8rXf5Ke0UzmEG8kmUXt80ecenDGbumbzGrpnyIPswmBS/z8FwRvNj+aHj6zqXlsoMk8/2d4HCAGpW3Kp+ZQAk/BMkCEVYdOCQpjgyjjlcdgRDR7UYT2Y8F2TUggYagUWb04FfyoNpS1MbtkhkMla6g8xQ527wQJqJaIphmtj5vI5uFjp/IevneScf7YlBkYlGZRiWIztqNQqoP4l1cTgxTSrjGsGfhfWOMgHtj1T4qhEfgQx47cDgjHWIu21gbbKPwXViFVmq657Ryd+omhBfd1V9BuTwlxz5EzEDK2m8/25Z1Wf8HfofebtYSWOPCV3XKOyRS71gQ7sYe9yLGVvucCNnankIZKqPEQ0nbkXkzVLgueHo0oBtdN1U9BIBY2pJPlCiXg2C3y1VBk9ICkHDj9GEQjeXoJ8b9Hme+NGTFX4GGFNGPkld/eFkzVFf+Xs39xkmkWwk1cxcFI2FzIVeVjWThfjC/j8FQU9oKwsHEyMJimoS/lYQ+nJw6jLWN+BTTxXDctSi1TFC0s6NphWiT1t092NoR3xLxzYuhaMSnTQJYE1HHfP8OT7BL/Fn4ELL8klX+YBXouFkPvxGgvcPecMO/ludBuqOaysL3t/Ix7bAFT2m56Ryx2c4kBm5ptKa6AWbpC9b+kF3TYJEs6DZQHReA0r7olu8/CFFOOzHYuZ9WD/6bxI9VHxDc9dfOIYSzjGHjLcz1iBnXP7c4bR0fulMd+DoIphT7RCMq05MoJ+ESeppcRy90OdiIigFZ4oeGqFHZxYZglqkfN6m1E6xqiOm+gWw= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:12.1434 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1ae3f3a-62d2-415d-d25a-08dce880e7d6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F67.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7191 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_093917_207238_875DE953 X-CRM114-Status: GOOD ( 12.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This per-vIOMMU cache_invalidate op is like the cache_invalidate_user op in struct iommu_domain_ops, but wider, supporting device cache (e.g. PCI ATC invaldiations). Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- include/linux/iommufd.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index 5a630952150d..e58b3e43aa7b 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -14,6 +14,7 @@ struct device; struct file; struct iommu_group; +struct iommu_user_data_array; struct iommufd_access; struct iommufd_ctx; struct iommufd_device; @@ -95,12 +96,21 @@ struct iommufd_vdevice { * @vdevice_free: Free a driver-managed iommufd_vdevice to de-init its structure * or HW procedure. The memory of the vdevice will be free-ed by * iommufd core. + * @cache_invalidate: Flush hardware cache used by a vIOMMU. It can be used for + * any IOMMU hardware specific cache: TLB and device cache. + * The @array passes in the cache invalidation requests, in + * form of a driver data structure. A driver must update the + * array->entry_num to report the number of handled requests. + * The data structure of the array entry must be defined in + * include/uapi/linux/iommufd.h */ struct iommufd_viommu_ops { void (*free)(struct iommufd_viommu *viommu); struct iommufd_vdevice *(*vdevice_alloc)(struct iommufd_viommu *viommu, struct device *dev, u64 id); void (*vdevice_free)(struct iommufd_vdevice *vdev); + int (*cache_invalidate)(struct iommufd_viommu *viommu, + struct iommu_user_data_array *array); }; #if IS_ENABLED(CONFIG_IOMMUFD) From patchwork Wed Oct 9 16:38:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C380CEE330 for ; Wed, 9 Oct 2024 17:16:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=UYYC3COHkotNUNMY31Vzls0Pl9/pAN8f8XFYHFTkDqs=; b=Lhi+R6JZrSs02I0RSR0bLIsCwa 3IPGqmkKyCzMWvp5uevFWJwEMItIzKDQh4RogDpLI2w4G33a3Kw0TqXqLeZeEBBVvgE7Q3VUxhQk9 U247fZyzxNyg1znrbzQX0MLM4kZWzF3FLGoUbE7CcqiflvZd4E2qNOeCR5XUowlqyXP5JynLWwy0k ZkH8yphDp4Vc/Hh+is1FVaq0YYPjxmj63F3cE27wgDUNhdPdG9n35QAWDjWukDwc8Q81heJzutfC9 DgMs05YU7fv5mv/YwiEmyr040eJvIJvRbVoVG7QPbmwARXV5MvUqpWg06Y4prBYQcfFxkqnbtlgQl gl3S/VpQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syaIj-0000000A8xC-0wde; Wed, 09 Oct 2024 17:16:41 +0000 Received: from mail-dm6nam10on20601.outbound.protection.outlook.com ([2a01:111:f403:2413::601] helo=NAM10-DM6-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZib-0000000A0bl-46Tp for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:24 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=kUNdnzkj5OsLb7eOVmTkmw5h+HqCsekGpE4ambZLJIWqLQEHrwfKUm7G+9c2fl99mlaHNPUDkcEo2rTRz4VluKWYy9txIPBk8z0vTRPXB7tdpn2y37EiWxScho6VitMofO88h5QVijheAuWMTeQLhsDu/UabdFw457pkAO8gWf0zEW2ynty4R4jNl5N6HohDgbr98qluvevJp5AZoIkGI7ixcyvWEkdBbdA2JPPszkLCKK34Ghsa2mFy78TqXAmezPLiNv+VAxDddq0tRHwq62RTO86Z73Sfp44Wzep5nliv9Y2zQ8m9pfazKanLx/o9gseH+oobhPXy9SOydbl/uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UYYC3COHkotNUNMY31Vzls0Pl9/pAN8f8XFYHFTkDqs=; b=lvRhwXwGiPfVcFI7/IbR/4ULzWYv2fQnG3N9L4BUvCTu8fV3zhnUsgOABmGRATXpd08cTE4tSGC5i0uhhkIgK7E2jg53mBkpASyRNoagyewcAE1m/H+Szj1/oYClYa6hRY+qQiiBLL2S0v0gH1zmv661JbmGW2uXoTAp0CshFHiWKL3MxOEnFDwaCOdBnYqQTRSiRdBww34a93Zr56Nl5rZEom3BsQHWwp2apG9S13dWVVXsmH88vry7o/6yqN9AI9pnmnmLhvoGyNIXD1WyNkt/mzJt4xS5l0YX3FJ07oiKLfPbCjtd2oWabE0pPOk0G4v6TdblhJlwCtN1Iqz4mg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UYYC3COHkotNUNMY31Vzls0Pl9/pAN8f8XFYHFTkDqs=; b=OAKO/UTcHWBkS4/29mqPjweGNGPRiu6BcGE4kGUW5d+r0k1zGk9nAaNgSHtyuL98/I8YHOg5ejsCiCMM7RXh4nmY3Y2qZ4mb3fNRMf+eZOI+DiMh+ND5tBk/pwhCO7mRlW0clgqDgHAdbRCwYZhavkjg7nf+HfSMxBW0zvSYZP33SLYiAQLY+xxQnKj0f8s0mqLYuqk9HzKq3TM8UL52pXyBEokTMntOlFXuYL/4CvkLEeM1I+4ysjFGXXNJdFruiIsa3OqBwhQ21jYlEd3bZqG7jGJwlOpL/otwe9BdTXkjzJLUdaXI10efSpR15h9PGePFGIXyGwZSKWd5L4fLxw== Received: from CH0P223CA0003.NAMP223.PROD.OUTLOOK.COM (2603:10b6:610:116::15) by SA3PR12MB9227.namprd12.prod.outlook.com (2603:10b6:806:398::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.25; Wed, 9 Oct 2024 16:39:11 +0000 Received: from DS3PEPF000099DD.namprd04.prod.outlook.com (2603:10b6:610:116:cafe::27) by CH0P223CA0003.outlook.office365.com (2603:10b6:610:116::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.17 via Frontend Transport; Wed, 9 Oct 2024 16:39:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by DS3PEPF000099DD.mail.protection.outlook.com (10.167.17.199) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:10 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:04 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:03 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:39:02 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 06/16] iommufd/hw_pagetable: Allow viommu->ops->cache_invalidate for hwpt_nested Date: Wed, 9 Oct 2024 09:38:18 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DD:EE_|SA3PR12MB9227:EE_ X-MS-Office365-Filtering-Correlation-Id: 357eeda9-f4cf-45c8-31c5-08dce880e700 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: 5VgQk4MTgtzZ0YMznNjW6zzTYYQ+nYetJuYuJUjwvyO1GKF6SHGsHlcQDFgwumdz+tbcOLWISAykmmPwsoTORgdzx7+RjL/9RioMoekfCbeU0npW/KdGw0ZYmuNoOWDMmhP5NIySkt5u3cH8kVdTcb4jxyDKPK5V2FRt3jeb3AZYFiYQfsNuoiwimH0EVecrBFqZtnOYHfQlTDw4X2XSW40wO5zAiSp/A444Kkd2MAF9u/JHROC8VfUuA+uFwj3NaGWqFtNz+Pq9Yse/fiUKqYfNl9HjosQT8RfmeTZ8sNs1ObL6qS+kV4ZZyaR0bASMxNu2rEOySKK9rJWvcJ6NWEp2QDPUkfwrusm5axr0AVkUMSI3IuqJ1xoM0NW8d6Hzuf1EN++Af0I93ClLWlm7VTQUYE1N3k7sHJVu9s2hZtSFURsdqgjc6FKe/Mo2IaWsUC73mMPyPQbjRuTi8IpyhmmClR3g0Nns583W4wWzwAL7lHC7Lr0CsmkErpJ+zyK/AJZQ0xSbVJM6LvkCjTDAkpDxhB12HTXKLRpIyHyaaOcmA/MLb1VV7maPYkhuLIMYMGeYGYtYyJfY86JB2VQE7oYFfdbttOK4nlTiUKjEqsCAlULWFPdQNJc7Vce9u0ABCQ5TNTi53f2ef30w1O4kSXSCWgyG/ydHGhIlR7hm+VumWZybi4NwJTOglGZ1wYha0orDGVCJD6EQPNmWp7XRTy5WFklimq0AsDRhFAPvcQBfhjUz9xrB8oIWJ7Cf0QiPwz2A8cyksWadqUO5wudJoGhZvjayJZUlBn7gmesauJDEtiZWj0OaCgqYg8as8GVDanKj40CE6AVo08D2PhgMqcvprVEbuhn+FSdh0eP2zqkw7ioPryHWckQ7/rd6wiSgVBXR8dw28eeZZoYVBJXKwthLibqXVsoAYAx61BsSKTJjuatrVi8oYH1tq+75cZL1npmA3R73Mh26wYGWPrkX9+UlGMgomjU2tFtLBzDgzWimGvf1I4StwAp+2J4GyHG+oA+yBXtUbq/TISf/Q+5RiWrP1s8orTgOXWJghBgZiKDrMyg7xJPN8wo/g6gYZ5Y1Q3jNq9vK+qPEhL/udS9wOXzmSzQntp5PyCvlb0eKVQNHMM0RpMcAH4zRFFiPX3UUdN6upuYTESNnMxUQBKCB/SRMv37uWDg6jPI34u3VuEHpcsh18eq3vmxpyNm/Q1CMMvLd2h6r9tD7MampUgbX982TS37LiDG7YWluw/GVTklHj0vvRd+quOPjEFlBoHDhsRpYpnHjlV+awunvRnADDIiYY9BeY49Gpej5zHFuA1KYodGL9aIurq+BYAZuhkP6JclX0ba5Rjin981RBgAwbK5G3xwwwCEiSxiyAHYtW+JchGbi26VdMkIzjE3QqWic X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(7416014)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:10.7681 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 357eeda9-f4cf-45c8-31c5-08dce880e700 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DD.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9227 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_093922_134165_0E0DFF5A X-CRM114-Status: GOOD ( 12.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now cache entries for hwpt_nested can be invalidated via the vIOMMU's cache_invalidate op alternatively. Allow iommufd_hwpt_nested_alloc to support such a case. Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- drivers/iommu/iommufd/hw_pagetable.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/hw_pagetable.c index b88a638d07da..ccaaf801955c 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -202,6 +202,17 @@ iommufd_hwpt_paging_alloc(struct iommufd_ctx *ictx, struct iommufd_ioas *ioas, return ERR_PTR(rc); } +static inline bool +iommufd_hwpt_nested_has_invalidate_op(struct iommufd_hwpt_nested *hwpt_nested) +{ + struct iommufd_viommu *viommu = hwpt_nested->viommu; + + if (viommu) + return viommu->ops && viommu->ops->cache_invalidate; + else + return hwpt_nested->common.domain->ops->cache_invalidate_user; +} + /** * iommufd_hwpt_nested_alloc() - Get a NESTED iommu_domain for a device * @ictx: iommufd context @@ -257,7 +268,7 @@ iommufd_hwpt_nested_alloc(struct iommufd_ctx *ictx, hwpt->domain->owner = ops; if (WARN_ON_ONCE(hwpt->domain->type != IOMMU_DOMAIN_NESTED || - !hwpt->domain->ops->cache_invalidate_user)) { + !iommufd_hwpt_nested_has_invalidate_op(hwpt_nested))) { rc = -EINVAL; goto out_abort; } From patchwork Wed Oct 9 16:38:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01EE5CEE330 for ; Wed, 9 Oct 2024 17:20:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=C2hNGL8HNWFMZjoZoP0wFRbNYBNWQfrIOfJAbXCxZBQ=; b=uxC+Pqyu+eYgI429uooUDpkbz2 sYrQgjFxC9tDyOOPXwONxAghQEM34SFDtsLVz4BWnIHbqDiTc8QMvXp3GIDXsCv2D94qX9J9932gU 6hSGC9TOIwdNDLImU6K8tSoYdVutVQCcrwvQWWzGk/nZ2qdIjbxsfSEulXBQkOra4F2raYzCef4sF ChMYE3BE9sfh/psNo64tuOuCxaJYJCqQLJsIUFYXi44U5BEgJkWo2/w/nowBI/DghNx7r2yaklxiy Fe/1RkOsKuo6NvZk0HZXffb6rIxlhuqEc0zc3JkXz0dKlhLSE6t6aHiMZQkb6ebCurXPjqrAx6mJA KVFwKClw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syaMj-0000000A9pg-1sFZ; Wed, 09 Oct 2024 17:20:49 +0000 Received: from mail-bn8nam12on2060a.outbound.protection.outlook.com ([2a01:111:f403:2418::60a] helo=NAM12-BN8-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZij-0000000A0fy-1Jv5 for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:31 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=FkO74zRJTDl1wwtTce/dkx0DeH9OhRH9veMFthkbpx87MUhnUOyZ0cW9n1gUBCiCE7UfsErdbjOjxbWyd9IKH9ToUMgeujVD/waF804QQqqFrZ66zxGVvoSjThDtdByuJdsXG9fHjSYdWewfVegfDjR43tG9VbvmOWEMm4XxUheIT6IOUxGvdF3kvQ98aQgIGZWV5ApPp7ezu9SZckGF3p5MC/1FRQajtJ13zCDPX0INFja+Ecz4C+hCWfPe6LxrAL0hmH4ye7fV7KjQtSPXqqnacBE1z2clVol8n09TZ1/UF7FJ9ryIZyHIGYcob5mYt7d5GPgkwLAq3i5hbrVGfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=C2hNGL8HNWFMZjoZoP0wFRbNYBNWQfrIOfJAbXCxZBQ=; b=vHhOBQjMoLsMmX/rEccmK45BmmhPgiRfs3ru/KXkCUXc6LujhBXzEUfMD77S2kpIP5G1LRgRoLkJvc5SbCWF/6VjT85SPmw4nROk+sRfh3pBZdudR7Ix9TXvTBNFaRZlX3CgeqLZqz5di6BK+06WzmNNTE+oyhwF7+3FL7m0rguHRqnzzUIuA6hrUSXQqk/xb3DK8DR4u8xFOXU5ucy7laFjz0SpyOfBfx0m6epNCm+AanRAB0thE5Mvs6m8joVGFJ6UeLXEtxlrW8Rn1zHHP1QB4YGmgPBujRk1+aNkrTw/x6sR0hIoK796+oJ1RawRPYSWKNFmAbEH8XHmwQZKUQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=C2hNGL8HNWFMZjoZoP0wFRbNYBNWQfrIOfJAbXCxZBQ=; b=nEpfp46PxsDf0C204fr//Y9z+HV297eu/reJRcOWOiXMzB2FCjH+W46K0EDQLxboAdI6zSj/ljFaxCa4DNSfkvnr1rre7cMBVgdPU16q34EPx+dZHB1c8fgJ/X2pDfyQuZruJ9XW7kHUUKGXnodKnjPKCgfr0NqAXlgwcC1uNz0iQcIGgA8pN45c4OXa3H5O9N5/B6iANEHxXxLLAbASs0aFtHJk25u5OuCizCHECgKiyzVJdZBnm7mBAltIdeyOW94E70jsvgxcINeZSUCWo0N4Qa+VJ5o/H5BrPXJiYNom0uy7TOo7KPabAKHMkwSUeW0LqfDaWXkuVKBWdt8pXA== Received: from SA9PR11CA0009.namprd11.prod.outlook.com (2603:10b6:806:6e::14) by BY5PR12MB4321.namprd12.prod.outlook.com (2603:10b6:a03:204::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.18; Wed, 9 Oct 2024 16:39:16 +0000 Received: from SA2PEPF00003F68.namprd04.prod.outlook.com (2603:10b6:806:6e:cafe::fd) by SA9PR11CA0009.outlook.office365.com (2603:10b6:806:6e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.17 via Frontend Transport; Wed, 9 Oct 2024 16:39:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SA2PEPF00003F68.mail.protection.outlook.com (10.167.248.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:16 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:05 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:04 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:39:04 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 07/16] iommufd: Allow hwpt_id to carry viommu_id for IOMMU_HWPT_INVALIDATE Date: Wed, 9 Oct 2024 09:38:19 -0700 Message-ID: <75cde75987bf4a73ec34335e1c13efda93791989.1728491532.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F68:EE_|BY5PR12MB4321:EE_ X-MS-Office365-Filtering-Correlation-Id: 3dd9872e-e719-4d7f-c5bb-08dce880ea2f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: Rs5Jc/mtP5mRzU/zdWkeb8EP81zyYaWHhaA5Wba/octCH1A1+PtSwKxPvz11vX86qP7V3K0krGRLJSGD+s+wZ7ILm1AxSDHIhmGKUCLGYb3hlVh1bflFLOF3se/rQflEN9Qip56XOM2vsXK8s2/S4jQ0Lro8liOQE7mrauRI28gCfG5ZwgBqLfRg3OQkvw+kVWGCDilOiacnn/WEyIxxg7sdGa1RpUj/8PiifEB2fFdNoda2NV+8Itpn4n6eCamovy/n19QZoF6lKp4Nv76ULdBCm23ABebDeFtIB7LkGDEDO0CwOWGtWigwkeJafTmC6TQWmAfk8PoTqMxDYir3OM5+IfPcYzr8A8eaua5CnJoDLbL2ULDNgjrS6WBvB6nza4iZtCHj+4yiyZ1KL7cWfCwDqSDH/RnBrlxOt3iWgttVEL+nM6/8XQUO6Y9gepkjsWaoRgey9fxgslt1SOaWGWoi1sz3iNd14kc07chVFFp5q/LaJwFV0e7iBN0VduW2PU8PwFMv12Aqzj3UM8C8NWKbvvaoEozPYttGol+EUFLnLiS7Rzh3naQ6UXsbY10vbPFM23ep3WsrrFP8IQqCbBmhOPDPO+UXSSUr3b3lmU2OcYjxUS/7utbJrO2NIt2sXdmMsIUGbwP7CFuKEpSjuI43F69QUsCA395U2eriH5bMn35sY6ScQDI7v9Jlr9Da/oHG9SBjnnrA4UWroBb9W/JThLt/2l7zlRHoX+qxA3/9QLMO8yq6DDWJMrAmTf2TsP4A9FZOTM9h+Am6WWEhWFBCeqfealRq7sdsqfWCSDfu9NJn2GK7qbaNpkuzFYDCYCyEAI33gyGU8TpiVqJBX+EAO+FpOr7KJ+U8ewcbxdlGLKGVfE4sk8pDcTrWDOiwWJwyyPMQUJx71RLmKWmUm6LGmZNHpWdC+C87qtQyHEZD9CAbZFmxGHoJ4vcEmqK6/EuZ45L249DEY61zmc+JtE7ih9LPa53M4M1HzaYtE3l+/YDuy+IS9ADRlCXK0ZfSjObU63u3tHhqA6CnBdID6SGRGKtfPiFff4EtI2Mzz1emhsPe51N25wIjSgGIkmuVghT+sqAUYIljLoLAiXM2KcHzMcXuz6ah8VwIiYgoyWU/DmyGkwIAL2LA1EReNLnBu0uZQMlhHqSqFdiIRELIi2W0oMcUVvttheTLX7DYMQS8kqOiEcS21q1Svj63aQJau5UjY5rVtjE9MwveXCtJLhHQgKRDLpKMYD5AQXDYlWlG5PSaWqGgqeibc9dLVwMLJi8jzmERZxGRUru+Z5fbCTN7IyHkjQe+Xj3UZpkKicHUxp/RC4ZNDH6KL/WOCNuriqjQ5T8uq0enkPkKLpRo3EhTtj4iL8pa/QdWA2BwTE8LHwzwga5bcnawUYt50Azq X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:16.0818 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3dd9872e-e719-4d7f-c5bb-08dce880ea2f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F68.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4321 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_093929_390178_3C00DEA4 X-CRM114-Status: GOOD ( 18.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org With a vIOMMU object, use space can flush any IOMMU related cache that can be directed using the vIOMMU object. It is similar to IOMMU_HWPT_INVALIDATE uAPI, but can cover a wider range than IOTLB, e.g. device/desciprtor cache. Allow hwpt_id of the iommu_hwpt_invalidate structure to carry a viommu_id, and reuse the IOMMU_HWPT_INVALIDATE uAPI for vIOMMU invalidations. Drivers can define different structures for vIOMMU invalidations v.s. HWPT ones. Update the uAPI, kdoc, and selftest case accordingly. Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- include/uapi/linux/iommufd.h | 9 ++++--- drivers/iommu/iommufd/hw_pagetable.c | 32 +++++++++++++++++++------ tools/testing/selftests/iommu/iommufd.c | 4 ++-- 3 files changed, 33 insertions(+), 12 deletions(-) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 3039519d71b7..cd9e135ef563 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -728,7 +728,7 @@ struct iommu_hwpt_vtd_s1_invalidate { /** * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE) * @size: sizeof(struct iommu_hwpt_invalidate) - * @hwpt_id: ID of a nested HWPT for cache invalidation + * @hwpt_id: ID of a nested HWPT or a vIOMMU, for cache invalidation * @data_uptr: User pointer to an array of driver-specific cache invalidation * data. * @data_type: One of enum iommu_hwpt_invalidate_data_type, defining the data @@ -739,8 +739,11 @@ struct iommu_hwpt_vtd_s1_invalidate { * Output the number of requests successfully handled by kernel. * @__reserved: Must be 0. * - * Invalidate the iommu cache for user-managed page table. Modifications on a - * user-managed page table should be followed by this operation to sync cache. + * Invalidate iommu cache for user-managed page table or vIOMMU. Modifications + * on a user-managed page table should be followed by this operation, if a HWPT + * is passed in via @hwpt_id. Other caches, such as device cache or descriptor + * cache can be flushed if a vIOMMU is passed in via the @hwpt_id field. + * * Each ioctl can support one or more cache invalidation requests in the array * that has a total size of @entry_len * @entry_num. * diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/hw_pagetable.c index ccaaf801955c..211b3f8b4366 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -444,7 +444,7 @@ int iommufd_hwpt_invalidate(struct iommufd_ucmd *ucmd) .entry_len = cmd->entry_len, .entry_num = cmd->entry_num, }; - struct iommufd_hw_pagetable *hwpt; + struct iommufd_object *pt_obj; u32 done_num = 0; int rc; @@ -458,17 +458,35 @@ int iommufd_hwpt_invalidate(struct iommufd_ucmd *ucmd) goto out; } - hwpt = iommufd_get_hwpt_nested(ucmd, cmd->hwpt_id); - if (IS_ERR(hwpt)) { - rc = PTR_ERR(hwpt); + pt_obj = iommufd_get_object(ucmd->ictx, cmd->hwpt_id, IOMMUFD_OBJ_ANY); + if (IS_ERR(pt_obj)) { + rc = PTR_ERR(pt_obj); goto out; } + if (pt_obj->type == IOMMUFD_OBJ_HWPT_NESTED) { + struct iommufd_hw_pagetable *hwpt = + container_of(pt_obj, struct iommufd_hw_pagetable, obj); + + rc = hwpt->domain->ops->cache_invalidate_user(hwpt->domain, + &data_array); + } else if (pt_obj->type == IOMMUFD_OBJ_VIOMMU) { + struct iommufd_viommu *viommu = + container_of(pt_obj, struct iommufd_viommu, obj); + + if (!viommu->ops || !viommu->ops->cache_invalidate) { + rc = -EOPNOTSUPP; + goto out_put_pt; + } + rc = viommu->ops->cache_invalidate(viommu, &data_array); + } else { + rc = -EINVAL; + goto out_put_pt; + } - rc = hwpt->domain->ops->cache_invalidate_user(hwpt->domain, - &data_array); done_num = data_array.entry_num; - iommufd_put_object(ucmd->ictx, &hwpt->obj); +out_put_pt: + iommufd_put_object(ucmd->ictx, pt_obj); out: cmd->entry_num = done_num; if (iommufd_ucmd_respond(ucmd, sizeof(*cmd))) diff --git a/tools/testing/selftests/iommu/iommufd.c b/tools/testing/selftests/iommu/iommufd.c index af00b082656e..2651e2b58423 100644 --- a/tools/testing/selftests/iommu/iommufd.c +++ b/tools/testing/selftests/iommu/iommufd.c @@ -362,9 +362,9 @@ TEST_F(iommufd_ioas, alloc_hwpt_nested) EXPECT_ERRNO(EBUSY, _test_ioctl_destroy(self->fd, parent_hwpt_id)); - /* hwpt_invalidate only supports a user-managed hwpt (nested) */ + /* hwpt_invalidate does not support a parent hwpt */ num_inv = 1; - test_err_hwpt_invalidate(ENOENT, parent_hwpt_id, inv_reqs, + test_err_hwpt_invalidate(EINVAL, parent_hwpt_id, inv_reqs, IOMMU_HWPT_INVALIDATE_DATA_SELFTEST, sizeof(*inv_reqs), &num_inv); assert(!num_inv); From patchwork Wed Oct 9 16:38:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E205FCEE332 for ; Wed, 9 Oct 2024 17:15:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=n5W6GPvTFiR9C5kTo46PFn3r++s62U7OGDx4eFcBIAQ=; b=f9bIGXTPT1mdOjsHFc7vXeYlHa AhdzNIuQYkZCFOdl8FyQFdADQdSHDGcs4uuHBw0Bdw3KxWzacWsNSuZEjIK7oyK/GUrS5YWIw5mqv fbGRXp1nffYoWfoxvAuijoVNptfzDNaoosaXRXVH5qd2fVYFXxV+TGdwCeNyO6ETG8WWIp0r1xd1i PsNmveyx6LCjXPteMoAF38pp73pqloUeMWw7TjQSMwjPFaj2TZ6JiWe0bPbEAv7X1i0NPHkpHSiZw JxolRK++69q81Icb1GUA1bV722Pv3HwDPLsAaB5XdWOUGp3Hm3s3zmsSOe/7djTzefeoadSfZiAUf vgW4BMww==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syaHN-0000000A8f0-3z0K; Wed, 09 Oct 2024 17:15:17 +0000 Received: from mail-dm6nam10on20601.outbound.protection.outlook.com ([2a01:111:f403:2413::601] helo=NAM10-DM6-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZib-0000000A0bE-46wy for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:23 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=JvrS+iG2v82VUkTmprdialp9EXIbCS8w4/ez4HxBvKp9MQx0eyD9oyfJwP0Q8Z6czhyijsYq3HjmuAoq8Cf9JiD+NS5CfY+IR7yIzynbyk46RvwDbnspE6+GIG8gcFMkZw2xNyEAfrvVhQAgYikM9jtNWnpYFWbcK0wseCqfyY0r/JTpSrq+kSg6IqbOmHihEHvf5ZAE1ESwKULwNl9t72PxGJGBVO4cXumPXPIDQqV6YCrTnCtZBddtkl5GNfOjg40R6ThkGaHzOZsT/3Fb5BDhQwBlzEZCfEGzgjRKVTJERT8po2sBr5CSHr6qFVwalnQkVkI/GwoppwdnrK2/Xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=n5W6GPvTFiR9C5kTo46PFn3r++s62U7OGDx4eFcBIAQ=; b=aMa9wFU9I6o42uSt32TUyQpTDZIw37RLKka5EVlA+FP7G2B0YBQNHJ2WJVvLLqTbqJ8ljitbAFwUAlWTKvBzUj4Jt/h1b5aDjn5H/QBsX4H/lMaBuZPwinfnx2irzJ//Oan0P79Ve3inZw0CGoDhWQGC8varUQDfccq+zI6qR2zVNVHXbahLan3HBOsTabUKQppUo8seVzdGGThUUEh3pG9sIfXaqx53Jyq4hnVsyM562jdptuSIBCYtcUjVRQNZ8U6PMrMP+VFezHC7rBKWYdOENKtvgwILxUeLEKTBgUpeqGzh5CToQtr9wGMYbRiMmfg3MJNNUPX2rrOnCbHlGg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=n5W6GPvTFiR9C5kTo46PFn3r++s62U7OGDx4eFcBIAQ=; b=UK4+gB5IDRK8dp77bjjuyfwrja2NvkDRyZxV4T9i8WX3cMqyvinQd7vt3S8uOT2ClhuoaYhXOdh2wln1RjZ2ge+aOi0+Hlr++m9uRNHELElGjk8xs/R/LWgoo9h7v74GDD5MJk1mYboDHPJtEwinVHCvON0ursssYdFGB/SLzarOAE0ONwAVPJUcrkJMS0s4tOMTglOcGOpuNdkJ3QqEc6oN92Zkw5bpBj4I2ymrwIqWAb3ak5b+dZaFazKELzmbcjZcy7TcN8eDljjqA3DH3GNrqBQdyKI5memull8cquJ3Wg7jlx3tS/Pm/yxa6UZANjxRQSd9Ie92ay8VAz5Q6A== Received: from DS7P220CA0007.NAMP220.PROD.OUTLOOK.COM (2603:10b6:8:1ca::14) by MN2PR12MB4048.namprd12.prod.outlook.com (2603:10b6:208:1d5::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.16; Wed, 9 Oct 2024 16:39:13 +0000 Received: from DS3PEPF000099E2.namprd04.prod.outlook.com (2603:10b6:8:1ca:cafe::8c) by DS7P220CA0007.outlook.office365.com (2603:10b6:8:1ca::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.18 via Frontend Transport; Wed, 9 Oct 2024 16:39:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by DS3PEPF000099E2.mail.protection.outlook.com (10.167.17.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:12 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:06 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:06 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:39:05 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 08/16] iommu: Add iommu_copy_struct_from_full_user_array helper Date: Wed, 9 Oct 2024 09:38:20 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E2:EE_|MN2PR12MB4048:EE_ X-MS-Office365-Filtering-Correlation-Id: c6188e38-f4cd-4ca8-73b0-08dce880e81f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: HGAFqYDaK7ZO6Z+fJKC/4CnKViWSzIsKx/opY87fclkkwyf9fP48FL0W8ENBff/67UNb6x0vWMPijJ3ggGxPWQQtRAuPEjJlBKmkeyoRuoJ6Ygj+yhceWOcA9ZVN2CM3i5yh7rgkAsrolnqgwnN90sdIg/7pu8yW7b32WK1r0WtptWXTwvr8AwocrWibaqVMk5Pptw5IiBfhGuUZt1SXb5eWXYOvydq96FpWlb7eg1Z+Ls8uL0ybQ1yrDHzvnGQONRuUxWu6mXNgVn8CFx/mbk1azdy1Dop1VigKbGh4lLv6spZKa+wWEmOGBe3KabqEhqZof+IpSVnGImE/O7s94oIVpqgafnoTPSMEFoFGVApHxjfKnkY5U2SETuGgUZUgGHLwIcDqeD53Lyn7RDuTQAXT4XuNhFpQNMCUo5eoPx8b4Hwj5hhnuj+MLZomtvHxdgoJ83bfS5Sds3fT5H6oll7saHNI2zMABEUvV8wg6bLM5Hwe2+fM+fZVy5IeXFbni4atmdS4D05uIImc7T0Drl5YZ+S6QAZ1/rpqF6YiX9ylt0oTWnrlMbNON+QsXxStWHSv9jLEOTeqqlpHM9E29NXMpAb/bPquyY3uNfIpjpNnQow3ro4NJit1nB3zFLsLiqnj6HNSqA1If8rc8ImNJ2mqSq1znQVt85bG1Uhurb2ilba7/NIhVo2rZIzcNCIrkwGiu3S7A/dXWxtRstW4QsjlHPtFAtVSSC85XBbomOog+Fc8MxYj/92RGfMNYIPVmAqqp+jdFxWgXaxreMQ+gzm6RMfisNGo5ZV4iik+ZFXxENbqQ4VXn0vrmWxYRs3FqcHUESfaRGF+tjYTvGkNJ8at4sa186medla+ZfxdVFeGZwX4zwm7BSsyrq5aeVWXS+Nf5RSvn4YM5Gh2I24sts+7jxinLa6R+AoPv9AIqYpw0XktK3s1dWnJoacAGJvuj2zbU7KjKLK26H9t/IGChf6qscu5o8vYQ0WoFluOoACkA1bKjkmmDxgU16wTSsXDimmj8T85BANlUAQBHdmiOtoBrx2Txezx9YvVONwNCuB5LUpIUmdD+ApHTmWHSfxBGhS3WNGrXJh+XvjCqoRKfSqOVd6PjiGlHeV6yUm3WNsXZc3gJrkIl0La7JeGJS+pt6D57abJtTj5fw3eFjVlrsjs8g/DTpoarjfpqL7Y8OYL7G6Kr8xsgGTTXnblGfET22KZ23C7CBqH1OHhERXHUZKRKijvPtIt8K8tF4iywdvq2NCzAOemkJFnPUuTLQqd1Mo+N856ay+cFDtKK58jkC25OxrnIILyI/6H86tZoqsNuANsu1VLr+TNig0ipUmZwINcDbfAyTa7xd9s3WqSRj0PMNCXgUpgmNs1z1fOtdm+tZnnSzb3PI4OaZkR8prs X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:12.6194 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6188e38-f4cd-4ca8-73b0-08dce880e81f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4048 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_093922_105439_3A93EA77 X-CRM114-Status: GOOD ( 18.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jason Gunthorpe The iommu_copy_struct_from_user_array helper can be used to copy a single entry from a user array which might not be efficient if the array is big. Add a new iommu_copy_struct_from_full_user_array to copy the entire user array at once. Update the existing iommu_copy_struct_from_user_array kdoc accordingly. Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- include/linux/iommu.h | 49 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 1de2aebc4d92..c980fd0e2174 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -494,7 +494,9 @@ static inline int __iommu_copy_struct_from_user_array( * @index: Index to the location in the array to copy user data from * @min_last: The last member of the data structure @kdst points in the * initial version. - * Return 0 for success, otherwise -error. + * + * Copy a single entry from a user array. Return 0 for success, otherwise + * -error. */ #define iommu_copy_struct_from_user_array(kdst, user_array, data_type, index, \ min_last) \ @@ -502,6 +504,51 @@ static inline int __iommu_copy_struct_from_user_array( kdst, user_array, data_type, index, sizeof(*(kdst)), \ offsetofend(typeof(*(kdst)), min_last)) + +/** + * iommu_copy_struct_from_full_user_array - Copy iommu driver specific user + * space data from an iommu_user_data_array + * @kdst: Pointer to an iommu driver specific user data that is defined in + * include/uapi/linux/iommufd.h + * @kdst_entry_size: sizeof(*kdst) + * @user_array: Pointer to a struct iommu_user_data_array for a user space + * array + * @data_type: The data type of the @kdst. Must match with @user_array->type + * + * Copy the entire user array. kdst must have room for kdst_entry_size * + * user_array->entry_num bytes. Return 0 for success, otherwise -error. + */ +static inline int +iommu_copy_struct_from_full_user_array(void *kdst, size_t kdst_entry_size, + struct iommu_user_data_array *user_array, + unsigned int data_type) +{ + unsigned int i; + int ret; + + if (user_array->type != data_type) + return -EINVAL; + if (!user_array->entry_num) + return -EINVAL; + if (likely(user_array->entry_len == kdst_entry_size)) { + if (copy_from_user(kdst, user_array->uptr, + user_array->entry_num * + user_array->entry_len)) + return -EFAULT; + } + + /* Copy item by item */ + for (i = 0; i != user_array->entry_num; i++) { + ret = copy_struct_from_user( + kdst + kdst_entry_size * i, kdst_entry_size, + user_array->uptr + user_array->entry_len * i, + user_array->entry_len); + if (ret) + return ret; + } + return 0; +} + /** * struct iommu_ops - iommu ops and capabilities * @capable: check capability From patchwork Wed Oct 9 16:38:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828856 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE648CEE332 for ; Wed, 9 Oct 2024 17:18:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=U7Q8qwwTrrSSdW7fG33myEfWF0p4jjVxkA0leq9KTSw=; b=FGbAuVT1WFv4yGmKeIGAzXFzoj vzHq78sd3FsqWgqKzMNStc0UCmL92NndD0vq7TfUfudPN+LhU/tTbkkkQ/ZA+2mAECFBCXHgE9kJZ s4pAnm9SvH36vXLDJL1yHaNkbKXQxvbjmWQLvMBdvUlMeGFF671jrXZxs1dc13CmhkWnlsSi/hfrP FGzh3Bn8WPr7YW7b0/T+2ilBLbo+LIW3UuN02hsl3TdxdTWJSxAt1YgRvmCJYMHgBsya+kxm37XAx yD/WsbIH6TP4HIibxR193fTe0Xb3PJsV483+9Y+Tr0AewkWnbfiKusOPKusxW/29msd1gyA9Qd+ur 2DtJutbg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syaK6-0000000A9E6-24IY; Wed, 09 Oct 2024 17:18:06 +0000 Received: from mail-co1nam11on20628.outbound.protection.outlook.com ([2a01:111:f403:2416::628] helo=NAM11-CO1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZid-0000000A0dr-3o5S for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:26 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=J5CxpI7KZe4tBCcgmSFI1ol2dZlFKmTsW3CO5Up56sZ55PU+PaMGb4b5Y5y8UXw9KZFear/NnEvdxCH3a8SpMQyH1P5cw9s2OEETY+QcZGQ5S1GjKR3Rftszw5bn5FGwHqv5rO2iXUqaZMz1vjJkdvIhQfvGrSJPdYtu+I6xupxqUom6bYhK87f9+oYtvFv/ol0IWKdTOyjiNjY/HUq6IvL82Eyl2YrYCfFtz68U6z+99Zh0R5jxiOkCzB8Ings4ho7rDyhjiyA7nH/wrOI6W42k0uK04jglUPZloq2voUhYsYB+9Ah1Of8Ha4FJetf5F7lYdt7ibiZwdGAY0wiNtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=U7Q8qwwTrrSSdW7fG33myEfWF0p4jjVxkA0leq9KTSw=; b=BuRfBJ1hyLGd7AfoQonHHalFe/ZtjMbnqyPPfq9u+PICHBZ6WWj48RRgjFk0P/k+5DBHVw4yaAqzO9a167GCNff7GxJN6KszlGkbHYIYsQmheErLpiIrazlDxX/sa05n49vypWXKGOUC3PXjn0oHNOlA+rc12vKOI2FHezz0eLL5dQYOj6sZ9CysWI26j+Uv+Zf4jfbZlUZ28ThcwH2aVQIdSPRZfA50ZlBFFlyS68+RxvMY3FKBrmzMRIU/DiTxCArvhxPkWRutB4DV40x74UKvvjyrwtVWBNrNKhAFEZmLulXDCzg/baQ4VUJTlcHtkTwHcCOxl567ml0q+S+bPA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=U7Q8qwwTrrSSdW7fG33myEfWF0p4jjVxkA0leq9KTSw=; b=TFLQNZTiNjSXe9UHj0+keTAFY2F7HNhuDbBVhoIQyGpSSnGMqxjh7/0c1tsK2Irh+kD6/9ZTExBv//vvH5qHzwQBuo62QGulNyD+VPzzpMEExr0yaVO10J3b1sL7I5D3qtEOB3HQaJEtC8ys9Z6vtQtjxAIDr/GhAINi59iIm4VcszzMSBPDvwThIWbucF6qHE/O0ikYqzyFMvTHUpFSsOLEetwxmzEQwSP0090nvGKllWR+IpQKxw6o/vJwgKGE2F0a1RFO6mon0pCm918RC5XnseuFwtbeNES/gdBnCF9Br9Ja56DFeS04YE2MImevGCkr8YFqwDCcRM73Ieq7Ig== Received: from CH0P223CA0021.NAMP223.PROD.OUTLOOK.COM (2603:10b6:610:116::9) by IA1PR12MB6161.namprd12.prod.outlook.com (2603:10b6:208:3eb::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.19; Wed, 9 Oct 2024 16:39:15 +0000 Received: from DS3PEPF000099DD.namprd04.prod.outlook.com (2603:10b6:610:116:cafe::19) by CH0P223CA0021.outlook.office365.com (2603:10b6:610:116::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.24 via Frontend Transport; Wed, 9 Oct 2024 16:39:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by DS3PEPF000099DD.mail.protection.outlook.com (10.167.17.199) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:14 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:08 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:07 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:39:06 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 09/16] iommufd/viommu: Add vdev_to_dev helper Date: Wed, 9 Oct 2024 09:38:21 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DD:EE_|IA1PR12MB6161:EE_ X-MS-Office365-Filtering-Correlation-Id: f4cdfb1d-4df3-4ceb-1662-08dce880e96c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: oItx2jOkrrQvONCqxDCrtrEXhNvgU5hdh51R/+7SLBvOl7J1iXxp93nWj3LURjmKxXTQyVT4wR4wvtb963XbpuSvfp0NnEggeD9V3gykpnLmSxuBNgHAsu+uDjrfpvkCPq/ZQJwhKxUQk07U4NfDA3V79rGkt2fRYjC7j3DjqsFf1sTuEcA3n15lqTGls5Pfr9vWmKgMnlMnZEEa7ZUeQ6ia5ByT7yeWj9n4pPFLhcUAsw1YFrVQfmaHm+0N2eQgsuqsJPdSwKD2qTNdUkVw4A1E8hOcYLg6XthGKY6Obe3s1MPfuBbfIS3guc5+RiCnwKjaB5qNjXxFHySjRVIRArhXJIoBXx03+/WsWkSqFIyIgmnMqi0a/NkTL40ZeB6Cw2sZ0I+zm3SFWPm6LwAexZb+h/zOhMNc5BcBHnWsORR1sFnvOHlExTMG+af5FW46JQSGeBYWLcqUmYkBxtCJv5zD3Mka1y1zOMFQwYR2dj2ge/GKczB9qxpIOzXuqxEbbWya627voGjQd79/vjVNRYfkV5p4CvQv8eUys20MlihZEuPNa6Sb5etrv+wnZvcInACpC6iGdbRqwrIP9+/P+pcZJdljIQSSKjEQzRgGRD/wRMrrbkBMKbnGU4WXG7Mp5q6OITWYS7Knk8ex4bs5BbcQa/ATmM4+yER/OIYEQaX5DiQ0V92ZP6ThMSUewerBBPfFO8cgwyb+DDzu9oNX2kPFGrbiYsT65RgSvgkSIWia7fJl1xMei28ino5615cLosxpV9fcY7o+5NbcfmjAAgHa55p0ZIgxO1Oe9gGo4qF+Do3S2Batu1Kbfqt1vDHeZGzjWjVgjAG971zCg8/sM+NER/XBE2kcGwN2dreXErFPd6iJUTa+TWvh8pdJmxTxsb4dJOEcv2QA5VHeeF92lmE8u6Z4FGNv6uSq2uKrgvUpuWWtrnicZQ7CmyxVQJM+51Qrgex6gp6AnnfnqqV7nisyoeBH87mDMha2hFE0EB0ek8UbhBmwcNrTU+/0w067/+Zwn5lyLLoEpDGO3sCG8JTxqliyJCaRWURDwaT57O8OmTzNJ6t/DVUltYfW7TDQQyV+DRyW6Q8+fQ4DqSCvt/1EAtMF4OAmjY/CCCd3KLhK8ySteds921JwpOVYUIVUOcXP2RXVOGW9xYU3yDH3uIeEsmIfzTJWg1Z5zi6z+HCjpmysccErMJ91KzKbQR+j1jyTAIXDY12ORFlZofvX/K9szObV+tTit+WiItqduCh3J68z211U1oUBucm3986+3pjlGHJB0EohPsyb4zXnHiS6n2Wmk2TdPz1/y8YlhpipEwdCM+okYNazpv6C2kZbRLo145XG1qrz7j8ANnENbJosURLNg0QFNGpXQR75vFo= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:14.8150 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f4cdfb1d-4df3-4ceb-1662-08dce880e96c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DD.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6161 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_093924_095241_FAF1482F X-CRM114-Status: UNSURE ( 9.67 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This avoids a bigger trouble of moving the struct iommufd_device to the public header. Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- include/linux/iommufd.h | 7 +++++++ drivers/iommu/iommufd/viommu_api.c | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index e58b3e43aa7b..18d9b95f1cbc 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -85,6 +85,7 @@ struct iommufd_vdevice { struct iommufd_viommu *viommu; u64 id; /* per-vIOMMU virtual ID */ }; +struct device *vdev_to_dev(struct iommufd_vdevice *vdev); /** * struct iommufd_viommu_ops - vIOMMU specific operations @@ -134,6 +135,7 @@ __iommufd_viommu_alloc(struct iommufd_ctx *ictx, size_t size, const struct iommufd_viommu_ops *ops); struct iommufd_vdevice * __iommufd_vdevice_alloc(struct iommufd_ctx *ictx, size_t size); +struct device *vdev_to_dev(struct iommufd_vdevice *vdev); #else /* !CONFIG_IOMMUFD */ static inline struct iommufd_ctx *iommufd_ctx_from_file(struct file *file) { @@ -187,6 +189,11 @@ __iommufd_vdevice_alloc(struct iommufd_ctx *ictx, size_t size) { return ERR_PTR(-EOPNOTSUPP); } + +static inline struct device *vdev_to_dev(struct iommufd_vdevice *vdev) +{ + return NULL; +} #endif /* CONFIG_IOMMUFD */ /* diff --git a/drivers/iommu/iommufd/viommu_api.c b/drivers/iommu/iommufd/viommu_api.c index 8419df3b658c..281e85be520d 100644 --- a/drivers/iommu/iommufd/viommu_api.c +++ b/drivers/iommu/iommufd/viommu_api.c @@ -69,3 +69,10 @@ __iommufd_vdevice_alloc(struct iommufd_ctx *ictx, size_t size) return container_of(obj, struct iommufd_vdevice, obj); } EXPORT_SYMBOL_NS_GPL(__iommufd_vdevice_alloc, IOMMUFD); + +/* Caller should xa_lock(&viommu->vdevs) to protect the return value */ +struct device *vdev_to_dev(struct iommufd_vdevice *vdev) +{ + return vdev ? vdev->idev->dev : NULL; +} +EXPORT_SYMBOL_NS_GPL(vdev_to_dev, IOMMUFD); From patchwork Wed Oct 9 16:38:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828857 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7DC37CEE332 for ; Wed, 9 Oct 2024 17:19:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Adhn2ntk7aCGtHZ2wiYuwOVsWCP5l+BSEnYAMVhXZVE=; b=zdZPaOB8kEnPHC3Tg6bSFtdSYC d3z/oQZGmsWs6jQTI8lMp6uEaFe7E/HkcL5X7Vdx9TTNZbZq0ydd1lEgu3ppaUlnk6bwN4wq0X12z jIp8LyeEPwQhlnn7l/igynz7XMnHKEpHNMQQh2VOdpJcDUFot2KLX+/oaTk1QhDzyD5+X2up5ogfa VBxr3x0qcv6MZUJ8jrcZ4tNfojKQ1PBcTXmcW0BFE9aQmrpPQ8GL6FRJA8EddsYAlKE2SdSPM/0cM YGjy2lUb3afcoWNsN06GijmJFnTCj6rlgN9hE+DTkEsc9ISst/i30drqCmBEKgUDtNgyql/EEZkQ3 e9Xom7Ag==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syaLO-0000000A9Sr-19Ki; Wed, 09 Oct 2024 17:19:26 +0000 Received: from mail-co1nam11on20600.outbound.protection.outlook.com ([2a01:111:f403:2416::600] helo=NAM11-CO1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZii-0000000A0fs-1aAJ for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:30 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=IqLlaYlpK7bGam83dYa8+3SleejDfblM6O1DRPCfrtxSyhkGsnlEuV3eofh8ArMd9rKG+46lozT0LJYDfGOY7iNWPc9dqgJf6GCI2PwiSZkthDFv5C/5rueW1MXfNa2mmke4bgAEIXFxypldt8THeoIcBrdjsbDPePIixOftkzPcSaIiXAl/+NLNWXonwThntJRANNGGMrfE91sRjd8YoWqoqvagHrEVnC/56WrG6X1TIQ6uwxxvhzAgqOqhekWBTV41fPOJ1imWWwFl6eywBEYGv2Go7gQeYB7lHWN+UDQNPM7LFqaFChnnzRvpCyztRNkopQDYAKTTIvExeabPyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Adhn2ntk7aCGtHZ2wiYuwOVsWCP5l+BSEnYAMVhXZVE=; b=xRlbEl3UZgQmbphiL9B4XyZSYxrZi3M7Ph24vGnUDLcV54CDYrVNOksZku+RHeAx+E9xhZ1zJl+j1rV0mMiy3sRrGRprcxU6netmU5j7dBHD9DdjocIWAelz6t4Qg78NXjpLArDyyxKSck3KOyR9yk8hnceHlg8o1CPKoz0e0hjQRao6zNXiOphuMM4GVhAQBiOftKoST+z+DTLX54fAZUi3HwYbWOQrWQCT4IFOQ5En3dd5eibwE5AfhHodq7e9zUFxHzsbbDqPIbiO3JG9drbx6NKSf+saz1csDnc1xP47Mp+icH+IrKhwknn2zfdj/KRuhKrN7JN9gqKNCDwWhA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Adhn2ntk7aCGtHZ2wiYuwOVsWCP5l+BSEnYAMVhXZVE=; b=R79tyU9OVw6JysBxVygTen/PpK3J7rRFuJYcTiFjJrlz2i2TpRl3lxnbIV2JuGozGa67vTOpynN83haDZGWyWMWpAdtMG8FuX7vv2PE3ewJq4x1pXLUxdDn11wBH+cPrWm9gcCaEVIzF4Eoeu3GBulDnTlxjlRhh3B1N/YG+MCmFmaVmGu+9eYfZaubmZqHIuYdj7LfR/R7awmAUc6wAgeTAi7Aa1kam3dP9oN1SO9Mon/fsv1suoDgZtorse5Jd/xbxHPhuuonoK6jS07pEhcrde/9JuZJ11KkV9XG25U3uv20gyQ0Rzz4tAllP5TeTyB0WWIxkprSNWFbvtJBlEw== Received: from DS7P220CA0003.NAMP220.PROD.OUTLOOK.COM (2603:10b6:8:1ca::17) by DS7PR12MB6005.namprd12.prod.outlook.com (2603:10b6:8:7c::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.23; Wed, 9 Oct 2024 16:39:17 +0000 Received: from DS3PEPF000099E2.namprd04.prod.outlook.com (2603:10b6:8:1ca:cafe::7b) by DS7P220CA0003.outlook.office365.com (2603:10b6:8:1ca::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.18 via Frontend Transport; Wed, 9 Oct 2024 16:39:17 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by DS3PEPF000099E2.mail.protection.outlook.com (10.167.17.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:17 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:09 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:09 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:39:08 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 10/16] iommufd/selftest: Add mock_viommu_cache_invalidate Date: Wed, 9 Oct 2024 09:38:22 -0700 Message-ID: <4a080b2ad3c543a09b01bd021ff7d3fbc5294ce4.1728491532.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E2:EE_|DS7PR12MB6005:EE_ X-MS-Office365-Filtering-Correlation-Id: f20e77ce-b3d2-49b8-795a-08dce880eb0e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: ptxMRwfCmo0q591pqhXS9njqQBiIZ2pZZQY0f8VGwvVG92dKMA9UFw1uitMl8l7HZr8grEvRLhaqo/SdPuyhUClVocartmFDrMdvBKxLt8PHT18DPlCe00BFQ1fvnBrLRN5RuuQYxa7FDVkmPZpgbgh0Yj/XSLuXAZFhtV2wS8I/2O+gOrzsEr9PDQYNSTrIMLMkFRMV3cpm+rQt7x4Tt/z6ZVpe2iSbSo8o4hx4yYaskySIEBtZv3Zn2lDaVGEsDrVbWOvOoBKhstsF3tP8LkRsC6f+DZcYgtRJzvbnW/9W3heoWfR9drpo7mw/7a68x6E1yvFqC7vOrrJvHPzLmir+/+ArFX1f7HIaK4IeOaLvmFxeBPVIo/6oI/YVNh5NFGwzXj77GyoZOta6aOUOp3vhi2n3p0h1PUfSej/E0a20NIq/Nt7UeOUQp2kw+MRoQkJRKC/BOUPjGeTtP4BYJO8sMrITiW0w+SiDerTh9z8mFvbug4VwypWMPyHl2abSuMUM08OJjdyV9BVfxSuV/zEB4ILiAMZ0VhDsIkaGmU1H6sO4vLQGGuWj1Qm8feH+t3P1Bm1q/ZBxevDLwg+M8MfD2LggVN8XnvJc/fUsVaF3anGrjo2lEnKpzwoKucpe3DIWEoI13RZGRa1y89TrtgG847s9HTK2HLDfyrDgmob7AJyCgQexuCculkb1DjfUZz1dVDqu20bmzhayFA09vmaBBEVWGcnYylOs7jibLmscj3QeoQ46/FnMpwhzcRvktETFXZ9DllBLlF0RbR0ljSyZYCfAFePmbIeDJPR+pyObUnTz0VvjcXQO5hbED2kkao6A3yNIxUKg5zrOCDEVtc3PDyRRDOXBKWzsgoGi/fvNMAUlAB05YqmREpB2hOdFwAE+eCCMYbTEninMv47mjK3f9OP4gZf/620wXZCN36556Uhazh4uQTalc4FmP6d3ENSYJObZi3zmeFXE3Z7TMg6rfLHz7n/v4tjiHZjRSDl874SJA47RXL93YFV6BJ/T8aUCVD9tf3/+YWc+PSID+4Q4F7EJkNIDi9k/wgLnAJMyN6IY9Ob3OkwaMRZOdtfUdG+koZc+v9euBNCej6dZbNe+alCZoMIgr2EkCNTf9dA2q+aLS0Qj48lSfXFeLKOWSU7ZM+2qzPSOrDoeTr/X/Atfo8wgZjkclZ2IaYA9nsneVBi+bF7AMaOF+WDo7Sh27OMtCnaFXKuJkCNtoHhXdSopjaXKNzAen+28Ma69bXvfTC7F6g2A5Rcir3N7ijQyh0b6mZu+af0ddb7jPCr4eqE/pD95B6XQcr4qb8ZU6scBI/rdz9/p3H1ARovcdCt28Or37N1slNWyg9aDvoovpk+r/z4Ax7AT0056ggtlr+8dy6TR1dygzB6t66molKFA X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:17.5413 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f20e77ce-b3d2-49b8-795a-08dce880eb0e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6005 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_093928_447471_BA57F3B9 X-CRM114-Status: GOOD ( 22.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Similar to the coverage of cache_invalidate_user for iotlb invalidation, add a device cache and a viommu_cache_invalidate function to test it out. Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/iommufd_test.h | 25 +++++++++ drivers/iommu/iommufd/selftest.c | 79 +++++++++++++++++++++++++++- 2 files changed, 103 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommufd/iommufd_test.h b/drivers/iommu/iommufd/iommufd_test.h index edced4ac7cd3..05f57a968d25 100644 --- a/drivers/iommu/iommufd/iommufd_test.h +++ b/drivers/iommu/iommufd/iommufd_test.h @@ -54,6 +54,11 @@ enum { MOCK_NESTED_DOMAIN_IOTLB_NUM = 4, }; +enum { + MOCK_DEV_CACHE_ID_MAX = 3, + MOCK_DEV_CACHE_NUM = 4, +}; + struct iommu_test_cmd { __u32 size; __u32 op; @@ -152,6 +157,7 @@ struct iommu_test_hw_info { /* Should not be equal to any defined value in enum iommu_hwpt_data_type */ #define IOMMU_HWPT_DATA_SELFTEST 0xdead #define IOMMU_TEST_IOTLB_DEFAULT 0xbadbeef +#define IOMMU_TEST_DEV_CACHE_DEFAULT 0xbaddad /** * struct iommu_hwpt_selftest @@ -182,4 +188,23 @@ struct iommu_hwpt_invalidate_selftest { #define IOMMU_VIOMMU_TYPE_SELFTEST 0xdeadbeef +/* Should not be equal to any defined value in enum iommu_viommu_invalidate_data_type */ +#define IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST 0xdeadbeef +#define IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST_INVALID 0xdadbeef + +/** + * struct iommu_viommu_invalidate_selftest - Invalidation data for Mock VIOMMU + * (IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST) + * @flags: Invalidate flags + * @cache_id: Invalidate cache entry index + * + * If IOMMU_TEST_INVALIDATE_ALL is set in @flags, @cache_id will be ignored + */ +struct iommu_viommu_invalidate_selftest { +#define IOMMU_TEST_INVALIDATE_FLAG_ALL (1 << 0) + __u32 flags; + __u32 vdev_id; + __u32 cache_id; +}; + #endif diff --git a/drivers/iommu/iommufd/selftest.c b/drivers/iommu/iommufd/selftest.c index 87bc45b86f9e..8a1aef857922 100644 --- a/drivers/iommu/iommufd/selftest.c +++ b/drivers/iommu/iommufd/selftest.c @@ -149,6 +149,7 @@ struct mock_dev { struct device dev; unsigned long flags; int id; + u32 cache[MOCK_DEV_CACHE_NUM]; }; struct selftest_obj { @@ -578,9 +579,80 @@ static struct iommufd_vdevice *mock_vdevice_alloc(struct iommufd_viommu *viommu, return &mock_vdev->core; } +static int mock_viommu_cache_invalidate(struct iommufd_viommu *viommu, + struct iommu_user_data_array *array) +{ + struct iommu_viommu_invalidate_selftest *cmds; + struct iommu_viommu_invalidate_selftest *cur; + struct iommu_viommu_invalidate_selftest *end; + int rc; + + /* A zero-length array is allowed to validate the array type */ + if (array->entry_num == 0 && + array->type == IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST) { + array->entry_num = 0; + return 0; + } + + cmds = kcalloc(array->entry_num, sizeof(*cmds), GFP_KERNEL); + if (!cmds) + return -ENOMEM; + cur = cmds; + end = cmds + array->entry_num; + + static_assert(sizeof(*cmds) == 3 * sizeof(u32)); + rc = iommu_copy_struct_from_full_user_array( + cmds, sizeof(*cmds), array, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST); + if (rc) + goto out; + + while (cur != end) { + XA_STATE(xas, &viommu->vdevs, (unsigned long)cur->vdev_id); + struct mock_dev *mdev; + struct device *dev; + int i; + + if (cur->flags & ~IOMMU_TEST_INVALIDATE_FLAG_ALL) { + rc = -EOPNOTSUPP; + goto out; + } + + if (cur->cache_id > MOCK_DEV_CACHE_ID_MAX) { + rc = -EINVAL; + goto out; + } + + xa_lock(&viommu->vdevs); + dev = vdev_to_dev(xas_load(&xas)); + if (!dev) { + xa_unlock(&viommu->vdevs); + rc = -EINVAL; + goto out; + } + mdev = container_of(dev, struct mock_dev, dev); + + if (cur->flags & IOMMU_TEST_INVALIDATE_FLAG_ALL) { + /* Invalidate all cache entries and ignore cache_id */ + for (i = 0; i < MOCK_DEV_CACHE_NUM; i++) + mdev->cache[i] = 0; + } else { + mdev->cache[cur->cache_id] = 0; + } + xa_unlock(&viommu->vdevs); + + cur++; + } +out: + array->entry_num = cur - cmds; + kfree(cmds); + return rc; +} + static struct iommufd_viommu_ops mock_viommu_ops = { .free = mock_viommu_free, .vdevice_alloc = mock_vdevice_alloc, + .cache_invalidate = mock_viommu_cache_invalidate, }; static struct iommufd_viommu * @@ -627,6 +699,9 @@ static const struct iommu_ops mock_ops = { .dev_disable_feat = mock_dev_disable_feat, .user_pasid_table = true, .viommu_alloc = mock_viommu_alloc, + .default_viommu_ops = &(struct iommufd_viommu_ops){ + .cache_invalidate = mock_viommu_cache_invalidate, + }, .default_domain_ops = &(struct iommu_domain_ops){ .free = mock_domain_free, @@ -759,7 +834,7 @@ static void mock_dev_release(struct device *dev) static struct mock_dev *mock_dev_create(unsigned long dev_flags) { struct mock_dev *mdev; - int rc; + int rc, i; if (dev_flags & ~(MOCK_FLAGS_DEVICE_NO_DIRTY | MOCK_FLAGS_DEVICE_HUGE_IOVA)) @@ -773,6 +848,8 @@ static struct mock_dev *mock_dev_create(unsigned long dev_flags) mdev->flags = dev_flags; mdev->dev.release = mock_dev_release; mdev->dev.bus = &iommufd_mock_bus_type.bus; + for (i = 0; i < MOCK_DEV_CACHE_NUM; i++) + mdev->cache[i] = IOMMU_TEST_DEV_CACHE_DEFAULT; rc = ida_alloc(&mock_dev_ida, GFP_KERNEL); if (rc < 0) From patchwork Wed Oct 9 16:38:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828860 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DDF45CEE330 for ; Wed, 9 Oct 2024 17:22:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=5asN4gechTz+hjEKh9L0yFbZdpPyBvxZHorkwZtYA64=; b=ZC+hYs4YheJekTh5gG3gU9vkYm 6mz1yNgN2AJi1N0nWWdUSjyBXqhqZXQm2RFxnDVyqjCgz+pJ1wbRN2FADxXWsOl9cBzmGrML6BSUa R8ha+gAgSCSXxeJYkAxswCcnXBdspCAVgZAaH1Wgt6xpq+NHMb4GVEITLFizcwJtaRX9grRQ5e3bj E1cd/Li9XiOc3GBGvuRiPBSK/khRkRqHQhSbxjjW6QAH/DTdRFVfcdu/LjnugShCa0K36HaKwYW1c /D3lLqTuUJR/neYV24ovGCZa8gNWPTtrsFxxxFTw83cHk1igs7czCoqBksO3ngr2n+/EFHGGpb2zx GM0dfrlw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syaO3-0000000AA6B-0tov; Wed, 09 Oct 2024 17:22:11 +0000 Received: from mail-dm6nam10on20600.outbound.protection.outlook.com ([2a01:111:f403:2413::600] helo=NAM10-DM6-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZik-0000000A0hW-3BVK for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:32 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=aS7naL7bzzm1MJ3g2j98KntXlFprYZMmQbIpdMqnoKc4jqSVInjiAFkigiNEg2ZvUznDj4OtX2Xb6ZMrKd4g3g4FZpI+BRUnIKjVQj0CKq39JmmU+rYmcuda1Aosu99CvXqfaTOKqXlZdVLXR54VSW7Zv7eOHqrXTeZya/2DlgEGUejcMBrfOlQsPKH7A6VAe/70CsicLkDjAOZNaEDWyhIu45AB08+cXDZVhvpzYawJhndG5gT89qNdE/K12DjV+aFaGYayt5PKy31k/wzi7rJKuWGm8Y4iNyX6sJKpaWDFCvQhm2x5ky+yospH9qe4LR4efvD2yEKUyywQTRLm8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=5asN4gechTz+hjEKh9L0yFbZdpPyBvxZHorkwZtYA64=; b=VF4aK9RqtQ9gTnb3ApCPMRxepE+UnZ02OsbE9KXTmGH5CNCMi14ewElqszmqxuE9K44TELP7CHJzfRlvEyqrAK+kU0aw76zKyXKGeDYAtzz/bgGqJ8VC2rJV8fVcy4kDXXwrP++iNuO607c1HC2vO9RIVIB0zMbVBJrJqcT/U7keXtOXZ0FjmtIwgDQC+pGAsQkVgWwblNHm8U1zxVhj8vF5PLGSUn417XkJVEfTmocf0kFzNC789fAeLCeqpMt24KM0izmloTfOM+ZejkzBIg6Cvd7RtS+q6kN2sMbt300+t3hhaUZZ2NaXXWK1ohUu35B97eQ1Ir7C3h5rlVLiPw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5asN4gechTz+hjEKh9L0yFbZdpPyBvxZHorkwZtYA64=; b=HJOKSvMdmE4vw6olASvB0mBRfcSUA5FNRjO33W9xUwMm5o5pb3Z6Zn3inxk5eXCuWabJCkFe2HWqZO8FaAo2Ww8Adux8dPgMT+tsInJo82s4j7o6ap3gjANImbWE3E1Cyw36SOqTheLgVJ42E4XJbe73wwLZSa/NFLR7dflOB8XJapqYPjOlFX229ir2q8n2uJ/Q43KUM9saUigADaiULnfNFj5LvkSgEgB+vDStcwQhwQGnlNiUnJa4i24nLINyrkvXkYN2k3nfile+eZm+uOulRZ58c1xQ8zuJJkUaLmU+W9URFcb5ECeNR7hHcNawZBOiHDNefJgBQKRKKDsLEw== Received: from SN6PR01CA0028.prod.exchangelabs.com (2603:10b6:805:b6::41) by DS0PR12MB7780.namprd12.prod.outlook.com (2603:10b6:8:152::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.23; Wed, 9 Oct 2024 16:39:21 +0000 Received: from SA2PEPF00003F64.namprd04.prod.outlook.com (2603:10b6:805:b6:cafe::2e) by SN6PR01CA0028.outlook.office365.com (2603:10b6:805:b6::41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7982.34 via Frontend Transport; Wed, 9 Oct 2024 16:39:21 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SA2PEPF00003F64.mail.protection.outlook.com (10.167.248.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:21 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:10 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:10 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:39:09 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 11/16] iommufd/selftest: Add IOMMU_TEST_OP_DEV_CHECK_CACHE test command Date: Wed, 9 Oct 2024 09:38:23 -0700 Message-ID: <021a42e13a7aeded63451279480510a8bc8a4833.1728491532.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F64:EE_|DS0PR12MB7780:EE_ X-MS-Office365-Filtering-Correlation-Id: c80f0764-2d26-4761-8ba3-08dce880ed59 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: VCBjyiU6rosXqAtV/WX06NgOMqlrvMpRtf78rhRK9VAOj6oYv5BW+stkLs0BqJlCGP7GIAOMWlLQj0gO3R2d1gX+D5A9be/nJH4TGuQgEY4Cs6WnM/Pm9QLtJcrIj+T2zrxHCfiJiVYhwARSl75hXI55V+daOpjCql/tfxw1hXyO8NuYogEbswXmNHIGaRqlHGj3XOLtQsedwAsfzhCN3XGsRiukpe81TLpDAgBdvJYSLCTMgp0ad2wrYHueO+rTOnEV+1Z6eIsA3dJBxw5WvmmegUmvHeLzlYvahcsmL9IKclvlQfipgnEvAsIwLdsF9Evy0vrCKRGB/5QA0g4Hd61q2EYGp8u4eaRLCCF9RMnnaw+I0Tnuhce8uYxx30dYc1v3ObtTjk2sd3AuaXae3AQtE2X4gxIDcN2Yxew3UhPkNJ3TxLdXwo76ckPFSZyrGMGqq8SCMVXpKPHmZa7r0dNXU+DxaLoGulMeDbldvu1UKn/gJ0/JodQ7CNKqg2fB4tS91F9xPGT4k/Pdi80xOfS3mQsfKtH5BdSwo1X4ssyfG9Zc0NRC1mDYG5mEsqV1WdRfqYw+1Q6ih1sL0p9gvcbTRBvMazbzgAz8d4yh1VUQZ5Rd3V2ePVJAuTt23XGHL4v3Swhk53YgnDg6vVEVKY7akFjy2V085ucokG7xtsIdqs8vSg5rYxH3NZVwXV/lRg0NT+l8354ai5TGQ78EfNbGfkWkGGHUM8aDEeA3J9RPqNrcj4PPs/96IcI0BVfYF3/OuhEESYIoZbkcmvdd89Mxugzk+5H8eULz55nI1VyhB1xNPnjNuTvmT7zUdp6Zo/vsWcIukJzoIsPOh8Hmm/8YO/Q6/k4ccXxQQAQgF3Fj1WOSP12OTfTlT9gM1nqeWvyJQ0FebmUOXpdIb+383euH+bDnBZBKfHfOm4U9Rc5ecGNpXhy+RY9Una961BeKnxe69EFw4UyTsxyLW9TVrBDYP5m+PkFmt92kCY2PSCNEszSST4eV6RngwsFXwxEIgI7uyjror/lEXSFohOh1u3qWXKQHBJF0KXOl8vNgPLIUeYzR2IQCRCrCYx0D9YGHVAnFhbBWhSyiY4LMETWvjvl95UoBJJHXsPUgopIPlz/fAu39FWqn+JFNPzWChWwRpH1YQJPXTJnGmJuEBplKMrN/7ky0q216N0CTNi4P1d3rRiymcKUSej90fexMy26wop0Va4O5jtQ2Ubz/4pZvkBBzC9H9t75Lb/1K/mhUYIj5+Zu7lNOhj+JqfW/SZm7OroG8zYsnSb9TJJ/mU6eekZoYAltkTnOiRw/JFyG0h+z6moTmjCImFZPlxl2xXl9h5Te986XdBvwOm/XKPYSZnAblRhiJdZpM1pKi74Iq9kYDggYKH5WaiKRm7Z2EySzb X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:21.3575 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c80f0764-2d26-4761-8ba3-08dce880ed59 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F64.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7780 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_093930_917881_E8911AED X-CRM114-Status: GOOD ( 16.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Similar to IOMMU_TEST_OP_MD_CHECK_IOTLB verifying a mock_domain's iotlb, IOMMU_TEST_OP_DEV_CHECK_CACHE will be used to verify a mock_dev's cache. Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/iommufd_test.h | 5 ++++ tools/testing/selftests/iommu/iommufd_utils.h | 24 +++++++++++++++++++ drivers/iommu/iommufd/selftest.c | 24 +++++++++++++++++++ tools/testing/selftests/iommu/iommufd.c | 7 +++++- 4 files changed, 59 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommufd/iommufd_test.h b/drivers/iommu/iommufd/iommufd_test.h index 05f57a968d25..b226636aa07a 100644 --- a/drivers/iommu/iommufd/iommufd_test.h +++ b/drivers/iommu/iommufd/iommufd_test.h @@ -23,6 +23,7 @@ enum { IOMMU_TEST_OP_DIRTY, IOMMU_TEST_OP_MD_CHECK_IOTLB, IOMMU_TEST_OP_TRIGGER_IOPF, + IOMMU_TEST_OP_DEV_CHECK_CACHE, }; enum { @@ -140,6 +141,10 @@ struct iommu_test_cmd { __u32 perm; __u64 addr; } trigger_iopf; + struct { + __u32 id; + __u32 cache; + } check_dev_cache; }; __u32 last; }; diff --git a/tools/testing/selftests/iommu/iommufd_utils.h b/tools/testing/selftests/iommu/iommufd_utils.h index ccd1f65df0b0..b3da8c96a828 100644 --- a/tools/testing/selftests/iommu/iommufd_utils.h +++ b/tools/testing/selftests/iommu/iommufd_utils.h @@ -234,6 +234,30 @@ static int _test_cmd_hwpt_alloc(int fd, __u32 device_id, __u32 pt_id, __u32 ft_i test_cmd_hwpt_check_iotlb(hwpt_id, i, expected); \ }) +#define test_cmd_dev_check_cache(device_id, cache_id, expected) \ + ({ \ + struct iommu_test_cmd test_cmd = { \ + .size = sizeof(test_cmd), \ + .op = IOMMU_TEST_OP_DEV_CHECK_CACHE, \ + .id = device_id, \ + .check_dev_cache = { \ + .id = cache_id, \ + .cache = expected, \ + }, \ + }; \ + ASSERT_EQ(0, \ + ioctl(self->fd, \ + _IOMMU_TEST_CMD(IOMMU_TEST_OP_DEV_CHECK_CACHE),\ + &test_cmd)); \ + }) + +#define test_cmd_dev_check_cache_all(device_id, expected) \ + ({ \ + int c; \ + for (c = 0; c < MOCK_DEV_CACHE_NUM; c++) \ + test_cmd_dev_check_cache(device_id, c, expected); \ + }) + static int _test_cmd_hwpt_invalidate(int fd, __u32 hwpt_id, void *reqs, uint32_t data_type, uint32_t lreq, uint32_t *nreqs) diff --git a/drivers/iommu/iommufd/selftest.c b/drivers/iommu/iommufd/selftest.c index 8a1aef857922..ac3836c1dbcd 100644 --- a/drivers/iommu/iommufd/selftest.c +++ b/drivers/iommu/iommufd/selftest.c @@ -1106,6 +1106,26 @@ static int iommufd_test_md_check_iotlb(struct iommufd_ucmd *ucmd, return rc; } +static int iommufd_test_dev_check_cache(struct iommufd_ucmd *ucmd, + u32 idev_id, unsigned int cache_id, + u32 cache) +{ + struct iommufd_device *idev; + struct mock_dev *mdev; + int rc = 0; + + idev = iommufd_get_device(ucmd, idev_id); + if (IS_ERR(idev)) + return PTR_ERR(idev); + mdev = container_of(idev->dev, struct mock_dev, dev); + + if (cache_id > MOCK_DEV_CACHE_ID_MAX || + mdev->cache[cache_id] != cache) + rc = -EINVAL; + iommufd_put_object(ucmd->ictx, &idev->obj); + return rc; +} + struct selftest_access { struct iommufd_access *access; struct file *file; @@ -1615,6 +1635,10 @@ int iommufd_test(struct iommufd_ucmd *ucmd) return iommufd_test_md_check_iotlb(ucmd, cmd->id, cmd->check_iotlb.id, cmd->check_iotlb.iotlb); + case IOMMU_TEST_OP_DEV_CHECK_CACHE: + return iommufd_test_dev_check_cache(ucmd, cmd->id, + cmd->check_dev_cache.id, + cmd->check_dev_cache.cache); case IOMMU_TEST_OP_CREATE_ACCESS: return iommufd_test_create_access(ucmd, cmd->id, cmd->create_access.flags); diff --git a/tools/testing/selftests/iommu/iommufd.c b/tools/testing/selftests/iommu/iommufd.c index 2651e2b58423..d5c5e3389182 100644 --- a/tools/testing/selftests/iommu/iommufd.c +++ b/tools/testing/selftests/iommu/iommufd.c @@ -222,6 +222,8 @@ FIXTURE_SETUP(iommufd_ioas) for (i = 0; i != variant->mock_domains; i++) { test_cmd_mock_domain(self->ioas_id, &self->stdev_id, &self->hwpt_id, &self->device_id); + test_cmd_dev_check_cache_all(self->device_id, + IOMMU_TEST_DEV_CACHE_DEFAULT); self->base_iova = MOCK_APERTURE_START; } } @@ -1386,9 +1388,12 @@ FIXTURE_SETUP(iommufd_mock_domain) ASSERT_GE(ARRAY_SIZE(self->hwpt_ids), variant->mock_domains); - for (i = 0; i != variant->mock_domains; i++) + for (i = 0; i != variant->mock_domains; i++) { test_cmd_mock_domain(self->ioas_id, &self->stdev_ids[i], &self->hwpt_ids[i], &self->idev_ids[i]); + test_cmd_dev_check_cache_all(self->idev_ids[0], + IOMMU_TEST_DEV_CACHE_DEFAULT); + } self->hwpt_id = self->hwpt_ids[0]; self->mmap_flags = MAP_SHARED | MAP_ANONYMOUS; From patchwork Wed Oct 9 16:38:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73322CEE330 for ; Wed, 9 Oct 2024 17:25:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=POe16X6GwCo2gRYg7xg4TtCfWFBZbXsj/TKr5W1vlNg=; b=HgSTPXwR+kwkaEY6kwbD54SxbK 0O4mLIalJCMz8cYlBTLVLvej06aNFcQ8fswInKipvq6pFJI59mIMf9M8o0HJZClb+hU5y3flAA/I0 iJzsc/86iFOVGvzf7Jvb6VNcYw+vVKEQymSX0o+No9iSzX0b2z5ooL/uoYPgGTKEGLEi5joraw+mo lxWN6eDZ5wZjGRHPNNNL6uB5SWdIKS11aDUmFLwesUY84CA/i/Eo6ZdBrDZsrXyFc1hFZCiuRBb+d 8di9xn7+SYFmOezyVAgtiPa6wxMwHgVnzbtUZ4iTjx5fTPUtUwhL4RoTzm/WxOcHmE9YNajlF0WQ8 5Z8nWF0w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syaQc-0000000AALD-28J5; Wed, 09 Oct 2024 17:24:50 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZir-0000000A0lZ-0TRo for linux-arm-kernel@bombadil.infradead.org; Wed, 09 Oct 2024 16:39:37 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Type:Content-Transfer-Encoding :MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From: Sender:Reply-To:Content-ID:Content-Description; bh=POe16X6GwCo2gRYg7xg4TtCfWFBZbXsj/TKr5W1vlNg=; b=GS8II0C2mu+sgsAgUIjo5v1Plf X4uSnabDAYbcgqyNYdHsnYvrmiD5OKs3m2k/DJxN/BKPLR0bTtiBt1FtUB7ZY9LmUNWe7yv/xM6QW q2Tw8HUJQWkW72d408dZsorj3WJugw6PPSZxUqYLdnsUCDeyPh1DcjlPPwjw3zX+leIS5SFFnwiAx HEGf0f1MAlOZ/aFiUWBPT7DiCzSokMUXvmYi9+2xsyY887JPYfsZ107vUG0oONOa9sdaY0DIsWcHE 3L3uc8uYcV7bUv12RNW2kISmZ1h7R1YG7Q3oLx8bf+yEBu3Ru3jWod0QECbDX47zRPvWjTtVzEHeU 8sjPRZtA==; Received: from mail-co1nam11on20607.outbound.protection.outlook.com ([2a01:111:f403:2416::607] helo=NAM11-CO1-obe.outbound.protection.outlook.com) by desiato.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZin-000000052jo-43DP for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:35 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=LaFtw89AcmEZOHPs20brj+2z12qL7MpFLD8SNCGIJyF5V49BHAUqedm5dyhs3AcBOBb/1xs9ylh3JD0i0lZZo5i6IYmhLgBGRGoXQC+3jkhROQPzSMHvT3r0LFnxWTwHWp57C+aNOfoleMO5VGMduDt6MUbytQ2mzHjvT+yyGcL5Qi77AtvjP2jVEiTRvOtZwMHtYG4nhYb6jI19cHukyiQmNfBw9PPEz4q2UD4gY4w6D2HQCLNhmo05xjiR1fTb9xhbWaPT2QBNDBqaIgwBApe5fUcaFU0n3c3UtGM+l6ijrdCwjjYfIAwVYdSsvUtvNn6LYJvvrcaW+U2hANf25g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=POe16X6GwCo2gRYg7xg4TtCfWFBZbXsj/TKr5W1vlNg=; b=skHIzhhXey2eNLFW/c3m6B44tlILswtN7qxBJU9FIl/KNPhtZ9UgX5ShusoYfy4fNG8JAsL0AjlkX2nqe483MVbLku4ClOK2OTAC/+GPCFFRP1yENY0AvND5mMEhxFvw9hegZuhpZJpWgfO22QtJc/40gR6fDdrfTW8pL1qUoVi9ca0qVaQK/GxyHvvbGURKyXNk32V6KlVLy5pInJ8/75NqYnkMN6CSz1JFIftl3blGVsnnG5lYqYB9nYvPrEa6SAlt3BUjAKAQ1tc36Psf04m8nYIMJnJ0PqHqtTXGUfzeBdBYD3Y4dx6ioEnvgSor1fdA2FgXX0oebFxLVZusjg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=POe16X6GwCo2gRYg7xg4TtCfWFBZbXsj/TKr5W1vlNg=; b=QjYdkPw3YXxAlnjXwboYvuzS2WPIpjvQ60lwA7w5MuFhVs2eWrXGgrC/QJ2bgaD48piAm+a8wxgTzKp3eEth5mfb6hpnlb9B6YZziRVQa+kz3+9Ef7zOcID0DFiYts4OBW6R/RxyJZ97YionJfQQZAI4m4E6eTE9SAwXseb7hu14EAiu9eNK1fqARQCT5dbcy3kfdXdbe0i91liOeTrhtIY5JGLZfWI4z2XxslJv+tQ5jcRwdYY5jKcw8z84j96YOfkXPM2TGNI4m78EvJ4hQdwcFSaWP4ZVnR/C1PoBsPe5waqY8/ekyP40HjY9uy3LP+KXvPD8y20KrpRDRfT9hA== Received: from SA1P222CA0119.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:3c5::18) by SA1PR12MB7221.namprd12.prod.outlook.com (2603:10b6:806:2bd::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.23; Wed, 9 Oct 2024 16:39:22 +0000 Received: from SA2PEPF00003F63.namprd04.prod.outlook.com (2603:10b6:806:3c5:cafe::45) by SA1P222CA0119.outlook.office365.com (2603:10b6:806:3c5::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.17 via Frontend Transport; Wed, 9 Oct 2024 16:39:22 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SA2PEPF00003F63.mail.protection.outlook.com (10.167.248.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:22 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:12 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:11 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:39:10 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 12/16] iommufd/selftest: Add vIOMMU coverage for IOMMU_HWPT_INVALIDATE ioctl Date: Wed, 9 Oct 2024 09:38:24 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F63:EE_|SA1PR12MB7221:EE_ X-MS-Office365-Filtering-Correlation-Id: 836f147a-b245-4354-993e-08dce880ee00 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: r+MLT17+spxX2L3QYgnK/LC+tx2XvAOgqxvt4F2JTjdcpF6pmElCTzbK1SbvCqFz4q6uBt5sgFqaaaYV6VblEPGgyoQCTE+7Nqc5ZuOsDTYnhB68gmD9if32XHtNIx4kzUqJXyrfVohU/1D2GVDP6RYsDp+X+xnYIu88QTlKsds0hfjaix+TsKmd6aRzE5eE5IMpEbi+3oXNNg4F7vyB7nwwUkRrpqE4BHQAENjhHu/xcgI01gbNxszjLD3lDWpIgy19QdR8nioniTwACaEkizG7+cbjwpO8xdeZgO0pJ82DSOgWffAB8Tfi/qILqJo31TJ+Z+t5+hsvVdGG+7Ac+MzZ/ujC/fZpUBluF45zkpCAduh41Yyc6J3BTGlH9qK415Y8DSi6ToatQ+bWrvrlUYUWLMGR+Zj/y8rfIZPhwWH+7udVSRpuS4aq57qloytrG0CThO4sdfYDn57RJQXxfmPGam5EMy/mBCPtBSn2NNAHhQTfFxPrNsXNWp+yiWYPg77bwI5EWK/a7Xi59mvxP4iIWahZy2kv2czNNFqtNl8m7ttvauAmAlDV6hy86F7uhYfY0UBHHvr7/yHq5m9RML01ECzzbMQQ5YFX1bMmZ9UPBU+f2krQJSH8jZyGT3urMANNz11iiLMqs2VGJoJOpglwlaXTirKafRM5NvLbwAS2hTBM89KiH/FiSauVfinn6+j/XwG14L0xus7erdF0+t8V4e81NW0nkstA1CUGmLawo52ID/u47CkMDuij/udh1rkuT87OPbF+nzwZLX7Zu6Y0cvoF/nUj45wmFSYNq8zf90N16uUv+yTF5DU7ogZUmvUQLTDkz7o03FMkLwZ3K4DsHVh2+sQB4G+j5Rx3ONEtbZcKq5IED6nYNxRm5Ga4vkY3nbDbYnlGrmCexE4s4mYmG4EHfBlYiYvAQZq3h/oZlzn3wJqteM7TrxxTjyfib/OPjz4ZGaLzSVETWusujmp4Yb6K9nT3LfuGoqPfZ3pWqVgL4VS8CU/nqaJdQ1FB4LJVAh5NrS8eSjJ2m3EIpU2+rSvD1XFX+ciU1jA2D9BmKt4WK+J9gd8gf59r9bdaSapHMayIg2RiOgJSFULwCFdiQiLi/lpxCpiHdalVVCe5xaaD2IjVvZUoMxMiRy9tkpOFElpU7QwchdZC+YxGeo+L/HCA6hAMzgN/82tmHKWNvR+b++d2ofRy0IYy40L21sU+GwAaXiQWNz/TcTRanKTc3S5FD/+5OuCTXeAamw4x5tSmq+6/o4tAlXlnVP7jnmVOA6nOXv6VlzBYNfQSjnYtkAi7oZXXk2Xy5wYwYCrwmEi9tNuehrJuLvj6G7rl3NLHTwrlml++aU13GvEjbma1Da2BN7mv3VDBQHF9B/B/t7/y+2gO1Ol3gW+Yd8hA X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:22.4992 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 836f147a-b245-4354-993e-08dce880ee00 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F63.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7221 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_173934_255781_6809C122 X-CRM114-Status: GOOD ( 14.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a viommu_cache test function to cover vIOMMU invalidations using the updated IOMMU_HWPT_INVALIDATE ioctl, which now allows passing in a vIOMMU via its hwpt_id field. Signed-off-by: Nicolin Chen --- tools/testing/selftests/iommu/iommufd_utils.h | 32 ++++ tools/testing/selftests/iommu/iommufd.c | 173 ++++++++++++++++++ 2 files changed, 205 insertions(+) diff --git a/tools/testing/selftests/iommu/iommufd_utils.h b/tools/testing/selftests/iommu/iommufd_utils.h index b3da8c96a828..29e9cd1fdd82 100644 --- a/tools/testing/selftests/iommu/iommufd_utils.h +++ b/tools/testing/selftests/iommu/iommufd_utils.h @@ -289,6 +289,38 @@ static int _test_cmd_hwpt_invalidate(int fd, __u32 hwpt_id, void *reqs, data_type, lreq, nreqs)); \ }) +static int _test_cmd_viommu_invalidate(int fd, __u32 viommu_id, void *reqs, + uint32_t data_type, uint32_t lreq, + uint32_t *nreqs) +{ + struct iommu_hwpt_invalidate cmd = { + .size = sizeof(cmd), + .hwpt_id = viommu_id, + .data_type = data_type, + .data_uptr = (uint64_t)reqs, + .entry_len = lreq, + .entry_num = *nreqs, + }; + int rc = ioctl(fd, IOMMU_HWPT_INVALIDATE, &cmd); + *nreqs = cmd.entry_num; + return rc; +} + +#define test_cmd_viommu_invalidate(viommu, reqs, lreq, nreqs) \ + ({ \ + ASSERT_EQ(0, \ + _test_cmd_viommu_invalidate(self->fd, viommu, reqs, \ + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, \ + lreq, nreqs)); \ + }) +#define test_err_viommu_invalidate(_errno, viommu_id, reqs, data_type, lreq, \ + nreqs) \ + ({ \ + EXPECT_ERRNO(_errno, _test_cmd_viommu_invalidate( \ + self->fd, viommu_id, reqs, \ + data_type, lreq, nreqs)); \ + }) + static int _test_cmd_access_replace_ioas(int fd, __u32 access_id, unsigned int ioas_id) { diff --git a/tools/testing/selftests/iommu/iommufd.c b/tools/testing/selftests/iommu/iommufd.c index d5c5e3389182..5a41bac3c1ab 100644 --- a/tools/testing/selftests/iommu/iommufd.c +++ b/tools/testing/selftests/iommu/iommufd.c @@ -2495,4 +2495,177 @@ TEST_F(iommufd_viommu, vdevice_alloc) } } +TEST_F(iommufd_viommu, vdevice_cache) +{ + struct iommu_viommu_invalidate_selftest inv_reqs[2] = {}; + uint32_t viommu_id = self->viommu_id; + uint32_t dev_id = self->device_id; + uint32_t vdev_id = 0; + uint32_t num_inv; + + if (dev_id) { + test_cmd_vdevice_alloc(viommu_id, dev_id, 0x99, &vdev_id); + + test_cmd_dev_check_cache_all(dev_id, + IOMMU_TEST_DEV_CACHE_DEFAULT); + + /* Check data_type by passing zero-length array */ + num_inv = 0; + test_cmd_viommu_invalidate(viommu_id, inv_reqs, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* Negative test: Invalid data_type */ + num_inv = 1; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST_INVALID, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* Negative test: structure size sanity */ + num_inv = 1; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs) + 1, &num_inv); + assert(!num_inv); + + num_inv = 1; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + 1, &num_inv); + assert(!num_inv); + + /* Negative test: invalid flag is passed */ + num_inv = 1; + inv_reqs[0].flags = 0xffffffff; + inv_reqs[0].vdev_id = 0x99; + test_err_viommu_invalidate(EOPNOTSUPP, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* Negative test: invalid data_uptr when array is not empty */ + num_inv = 1; + inv_reqs[0].flags = 0; + inv_reqs[0].vdev_id = 0x99; + test_err_viommu_invalidate(EINVAL, viommu_id, NULL, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* Negative test: invalid entry_len when array is not empty */ + num_inv = 1; + inv_reqs[0].flags = 0; + inv_reqs[0].vdev_id = 0x99; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + 0, &num_inv); + assert(!num_inv); + + /* Negative test: invalid cache_id */ + num_inv = 1; + inv_reqs[0].flags = 0; + inv_reqs[0].vdev_id = 0x99; + inv_reqs[0].cache_id = MOCK_DEV_CACHE_ID_MAX + 1; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* Negative test: invalid vdev_id */ + num_inv = 1; + inv_reqs[0].flags = 0; + inv_reqs[0].vdev_id = 0x9; + inv_reqs[0].cache_id = 0; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* + * Invalidate the 1st cache entry but fail the 2nd request + * due to invalid flags configuration in the 2nd request. + */ + num_inv = 2; + inv_reqs[0].flags = 0; + inv_reqs[0].vdev_id = 0x99; + inv_reqs[0].cache_id = 0; + inv_reqs[1].flags = 0xffffffff; + inv_reqs[1].vdev_id = 0x99; + inv_reqs[1].cache_id = 1; + test_err_viommu_invalidate(EOPNOTSUPP, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(num_inv == 1); + test_cmd_dev_check_cache(dev_id, 0, 0); + test_cmd_dev_check_cache(dev_id, 1, + IOMMU_TEST_DEV_CACHE_DEFAULT); + test_cmd_dev_check_cache(dev_id, 2, + IOMMU_TEST_DEV_CACHE_DEFAULT); + test_cmd_dev_check_cache(dev_id, 3, + IOMMU_TEST_DEV_CACHE_DEFAULT); + + /* + * Invalidate the 1st cache entry but fail the 2nd request + * due to invalid cache_id configuration in the 2nd request. + */ + num_inv = 2; + inv_reqs[0].flags = 0; + inv_reqs[0].vdev_id = 0x99; + inv_reqs[0].cache_id = 0; + inv_reqs[1].flags = 0; + inv_reqs[1].vdev_id = 0x99; + inv_reqs[1].cache_id = MOCK_DEV_CACHE_ID_MAX + 1; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(num_inv == 1); + test_cmd_dev_check_cache(dev_id, 0, 0); + test_cmd_dev_check_cache(dev_id, 1, + IOMMU_TEST_DEV_CACHE_DEFAULT); + test_cmd_dev_check_cache(dev_id, 2, + IOMMU_TEST_DEV_CACHE_DEFAULT); + test_cmd_dev_check_cache(dev_id, 3, + IOMMU_TEST_DEV_CACHE_DEFAULT); + + /* Invalidate the 2nd cache entry and verify */ + num_inv = 1; + inv_reqs[0].flags = 0; + inv_reqs[0].vdev_id = 0x99; + inv_reqs[0].cache_id = 1; + test_cmd_viommu_invalidate(viommu_id, inv_reqs, + sizeof(*inv_reqs), &num_inv); + assert(num_inv == 1); + test_cmd_dev_check_cache(dev_id, 0, 0); + test_cmd_dev_check_cache(dev_id, 1, 0); + test_cmd_dev_check_cache(dev_id, 2, + IOMMU_TEST_DEV_CACHE_DEFAULT); + test_cmd_dev_check_cache(dev_id, 3, + IOMMU_TEST_DEV_CACHE_DEFAULT); + + /* Invalidate the 3rd and 4th cache entries and verify */ + num_inv = 2; + inv_reqs[0].flags = 0; + inv_reqs[0].vdev_id = 0x99; + inv_reqs[0].cache_id = 2; + inv_reqs[1].flags = 0; + inv_reqs[1].vdev_id = 0x99; + inv_reqs[1].cache_id = 3; + test_cmd_viommu_invalidate(viommu_id, inv_reqs, + sizeof(*inv_reqs), &num_inv); + assert(num_inv == 2); + test_cmd_dev_check_cache_all(dev_id, 0); + + /* Invalidate all cache entries for nested_dev_id[1] and verify */ + num_inv = 1; + inv_reqs[0].vdev_id = 0x99; + inv_reqs[0].flags = IOMMU_TEST_INVALIDATE_FLAG_ALL; + test_cmd_viommu_invalidate(viommu_id, inv_reqs, + sizeof(*inv_reqs), &num_inv); + assert(num_inv == 1); + test_cmd_dev_check_cache_all(dev_id, 0); + test_ioctl_destroy(vdev_id); + } +} + TEST_HARNESS_MAIN From patchwork Wed Oct 9 16:38:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828861 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B4D1FCEE332 for ; Wed, 9 Oct 2024 17:23:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=OodBFEyxwxkpxrU3O1vgTk+R9PWLfXORshgxazPXvZ4=; b=dcqpYGlfPzb73wt6Nji9/NcCE2 tiZ6Jqruq225iLu0XVnklHBrN5M2oPqEhdZwhItSqAlEHJd5w9LsG9pVGjDt+JeNf5Q4PxNUeojZV n7LqqvsVqMohwykhULzfK4re4ibdcl4bGSnNdKFxtmdX654TZgvGx4hVz4zDRKnqPuGIVXt6Sg6SM aZbOwOKZm7qqlXq0vGXdjkDtB2oOHtm+6+EryXBelCf9AM/Oj9soXQcbNOWqFa3gIvN05c+W/JP5f Z9MrjmJ5Bsoc93kNQsw8UsqdVtaMTAyeNVPX3CHVAhTPmztpl+6kcelM1aTkMuPswTNCzG9wAwJtW YZ1+KVFg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syaPL-0000000AAE2-01WF; Wed, 09 Oct 2024 17:23:31 +0000 Received: from mail-mw2nam12on2060a.outbound.protection.outlook.com ([2a01:111:f403:200a::60a] helo=NAM12-MW2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZil-0000000A0ha-3fgl for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:33 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=yRvFDZ/0TyEaagc6SIJMHgniMDEiuxE6vbHWaKw19bKXMMTyhFQgpuwgfGj38vESn8q2Sk+KZbAel64Tx51bt/M3Q25g1ZznjQf6zBbl3wJHURIG3OE0WNizHWXcG2SZ+i+8bLQLGsQ2TLCj1iiKp012fxF9e8JKe8xHsM3Ae1lNhkvBVCMOe7Bzb6TE6PF7lvq6RrvBkZK9np/rFcU2tCD5TeSsxpRN+VWYHQu6RDGrL5AMzEysmS0xK2msaaBNiHE748znV94MSIeLJA1YVSne+f5D1s46pw9CxB9h3iT7XBLuNxLQwueJdEwDbeZ3gzelKT8PKBQiK1VRVPLsMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=OodBFEyxwxkpxrU3O1vgTk+R9PWLfXORshgxazPXvZ4=; b=JPA5TzOT54r4NyXMTiBEZdKRVcs15DPMSGYEje92zsgKix3q80FOIm6jErxhzUEghucRAuEwPLQHzVd7FSfpgYvcgtJBsxwQJlg33PbWWYIlpfQHf8QVEmaj2Mu6AUUm1A7J3N1XxXXUsugo77035Zfte3rUtw5I5C3x/0JmZw5VKLg3jIybXZipfX/WYWsVsH6oCLiLH3Wc3rd1AIf0YECikY6i3C76QNhWAASpYKn1bBB9zTK2hra2FwM/Zt41oFK6JxomeSjtPKxNnZztLrLQro+VDCCeqyhOElzMpZW3dE056jZFeUtLnt7KcJLW6o7w/1Z269k77rSS54WRng== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OodBFEyxwxkpxrU3O1vgTk+R9PWLfXORshgxazPXvZ4=; b=mcNDv7s+Px+D3C6FBcux3JBQntKe1RirC4Xy6M6ZBznU5iQ246cEnZmvEToz9/Gp3sMBFEemWyPzRSNAbw2tN8uA2nSAyTCo+kHSDEubhpLcgOv+wTkXQ+oJMoI6RkIK3KmOjM+Pw7nAm9Gjzw8/NqPZX46vTCj2oauRzXyuz3TEqdW6p/nC49LAftSOeUSNsKitVSqEXgQ0UgbLyk+NZLZ6Pb9iUxMUy1GCaXspP8gJS84EhnRdUTenWyZBYXyg82WOSZHy7zfMg+2XuRaqL/rinTxPTkSCGwW6Oce6Q8zhmup6SBixtkCpUqUy7vts3MhFnFzmtNMhTT3GhlE1zg== Received: from SA1P222CA0121.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:3c5::9) by IA1PR12MB7543.namprd12.prod.outlook.com (2603:10b6:208:42d::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.25; Wed, 9 Oct 2024 16:39:24 +0000 Received: from SA2PEPF00003F63.namprd04.prod.outlook.com (2603:10b6:806:3c5:cafe::9) by SA1P222CA0121.outlook.office365.com (2603:10b6:806:3c5::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.17 via Frontend Transport; Wed, 9 Oct 2024 16:39:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SA2PEPF00003F63.mail.protection.outlook.com (10.167.248.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:24 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:13 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:13 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:39:12 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 13/16] Documentation: userspace-api: iommufd: Update vDEVICE Date: Wed, 9 Oct 2024 09:38:25 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F63:EE_|IA1PR12MB7543:EE_ X-MS-Office365-Filtering-Correlation-Id: b9d69071-26c0-4b60-b679-08dce880eeff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: 0ept51ItioDuIg4wBzv79WSFxk5016dRRfCeIcdHt0XM/NMrWer0hBP2GgboW268npaAFHZykiK0d4MLkmaxaYHzTtU4IhiopPUKk+608lMZJZeNR0jiCjfvp4x6HzH6ndwkCy0QXCK7zFcDaA4+6JwDXvDWEAoL4SxOk7w9ZQye8eVD7IuqyUJxShZPz/HxYcMe2DgJ0mhuiqT9qmQM70oPZsAoC5IP9+EJlSsdMrEKHR147CnbSUaGwyQ8h+H+LfLGuxRaWX1a562r46eR50xEPIhuRs4A3ZNZFe0AVCuUNXIXidi6o524Kz9ULYpjhYqqJaRMRlF5bskm03wX8PMGFeS+sApXCfcTglDiyzNvhoC1KG4sB+ffK4iDxx4Y5STErVvFua6PTG1tv1WATvKE/26kDMjeYLGUUsTWH6zD0ErLYxHUYVCL5mq89bVm3CX0WsA0UCfwY4IGACZDpXUOowCgpzQBN0DW+h5AJjR/iqJyu05DuJYpekpVK02/r9UJ7m68fP/xdtKXpKVMANhIJo1eDiYpwUTgWR82zo3TKl0WQGCJddmFoVXOUNLAZK6F4ug2tGjWtj3Qr1vcRnPUBnafptw7ztU7INw5btfKi3xDJR9ulWsZhWUiYyniz8BI3i7aGhQgYasi/Kdtuc8VMd4mk+5oF5iI4dgVEsN7eIVLPW1vBh4NtR+3mZ5Ked3vnw29TK8vN55HrxE6z27ozMYzV5C2ipCwi7ikD6eaDhsGkPuFdmVGlZabo4QjKiVf4DJ46CDk16eAtz8RxOd/DdbFFCLW28LIIn0+R7PJyJvnlZG6gqYV1PV0Ep56GKRlYEfPYwWYDFDFCzSz7rEEeeLrwGTlpAIEPAh5be3tdIKxoaojGrUOm5WeII2yFNmGvZY4EqGIyiL7P0trcacmQAbtM+SgAmHYJyf9U6uEy2Udgpq01v9Xub7iLFgaANZ6S7V+Qmn7xvKegF8L997rIpVMPB2IWCNkeFOGarveRZDMf7GLkN8k2Aw8pgNlTLd5vx8l0xirvtMwP/0s2ClS2xt6VfmjWUUyUlWkk+mgGoQXgGrsKDqCL/vP5RCYc2cL3Nl0oXYzZFW6zGGtGCGKnaaEsKxLn64NnQ+SZ3DHdUuv/atYtEJrIKCRXffuwshdotfFHJDmBm+5+LjmPkAfiqg6NBRYzbao9Bm+U2GEeZ/uICmd2LDG+YRUb33BZ/E337EoYhDYWyKbY+bYwCw8mgWv+nVu9yO42K4dyxpv/xzRTgfoGVoZo3wNSn7lMs/x9hYTUVox1f8YGvLjjtHE1S1bE0BmP5x45q6sPC8zEmUEJi58fAMPllKY48/679KWxQ37Z7VrpCAs0rxPZVFMRH8r0h7eCFc7/UjLgPF5ln+GqeRHaO+yt9iCTQIF X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:24.2023 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9d69071-26c0-4b60-b679-08dce880eeff X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F63.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7543 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_093931_958156_ADC30A01 X-CRM114-Status: GOOD ( 17.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org With the introduction of the new object and its infrastructure, update the doc and the vIOMMU graph to reflect that. Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- Documentation/userspace-api/iommufd.rst | 58 ++++++++++++++++++------- 1 file changed, 42 insertions(+), 16 deletions(-) diff --git a/Documentation/userspace-api/iommufd.rst b/Documentation/userspace-api/iommufd.rst index 37eb1adda57b..3c27cc92c2cb 100644 --- a/Documentation/userspace-api/iommufd.rst +++ b/Documentation/userspace-api/iommufd.rst @@ -94,6 +94,19 @@ Following IOMMUFD objects are exposed to userspace: backed by corresponding vIOMMU objects, in which case a guest OS would do the "dispatch" naturally instead of VMM trappings. + - IOMMUFD_OBJ_VDEVICE, representing a virtual device for an IOMMUFD_OBJ_DEVICE + against an IOMMUFD_OBJ_VIOMMU. This virtual device holds the device's virtual + information or attributes (related to the vIOMMU) in a VM. An immediate vDATA + example can be the virtual ID of the device on a vIOMMU, which is a unique ID + that VMM assigns to the device for a translation channel/port of the vIOMMU, + e.g. vSID of ARM SMMUv3, vDeviceID of AMD IOMMU, and vID of Intel VT-d to a + Context Table. Potential use cases of some advanced security information can + be forwarded via this object too, such as security level or realm information + in a Confidential Compute Architecture. A VMM should create a vDEVICE object + to forward all the device information in a VM, when it connects a device to a + vIOMMU, which is a separate ioctl call from attaching the same device to an + HWPT_PAGING that the vIOMMU holds. + All user-visible objects are destroyed via the IOMMU_DESTROY uAPI. The diagrams below show relationships between user-visible objects and kernel @@ -133,23 +146,26 @@ creating the objects and links:: |____________| |____________| |______| _______________________________________________________________________ - | iommufd (with vIOMMU) | + | iommufd (with vIOMMU/vDEVICE) | | | - | [5] | - | _____________ | - | | | | - | [1] | vIOMMU | [4] [2] | - | ________________ | | _____________ ________ | - | | | | [3] | | | | | | - | | IOAS |<---|(HWPT_PAGING)|<---| HWPT_NESTED |<--| DEVICE | | - | |________________| |_____________| |_____________| |________| | - | | | | | | - |_________|____________________|__________________|_______________|_____| - | | | | - | ______v_____ ______v_____ ___v__ - | PFN storage | (paging) | | (nested) | |struct| - |------------>|iommu_domain|<----|iommu_domain|<----|device| - |____________| |____________| |______| + | [5] [6] | + | _____________ _____________ | + | | | | | | + | |----------------| vIOMMU |<---| vDEVICE |<----| | + | | | | |_____________| | | + | | | | | | + | | [1] | | [4] | [2] | + | | ______ | | _____________ _|______ | + | | | | | [3] | | | | | | + | | | IOAS |<---|(HWPT_PAGING)|<---| HWPT_NESTED |<--| DEVICE | | + | | |______| |_____________| |_____________| |________| | + | | | | | | | + |______|________|______________|__________________|_______________|_____| + | | | | | + ______v_____ | ______v_____ ______v_____ ___v__ + | struct | | PFN | (paging) | | (nested) | |struct| + |iommu_device| |------>|iommu_domain|<----|iommu_domain|<----|device| + |____________| storage|____________| |____________| |______| 1. IOMMUFD_OBJ_IOAS is created via the IOMMU_IOAS_ALLOC uAPI. An iommufd can hold multiple IOAS objects. IOAS is the most generic object and does not @@ -212,6 +228,15 @@ creating the objects and links:: the vIOMMU object and the HWPT_PAGING, then this vIOMMU object can be used as a nesting parent object to allocate an HWPT_NESTED object described above. +6. IOMMUFD_OBJ_VDEVICE can be only manually created via the IOMMU_VDEVICE_ALLOC + uAPI, provided a viommu_id for an iommufd_viommu object and a dev_id for an + iommufd_device object. The vDEVICE object will be the binding between these + two parent objects. Another @virt_id will be also set via the uAPI providing + the iommufd core an index to store the vDEVICE object to a vDEVICE array per + vIOMMU. If necessary, the IOMMU driver may choose to implement a vdevce_alloc + op to init its HW for virtualization feature related to a vDEVICE. Successful + completion of this operation sets up the linkages between vIOMMU and device. + A device can only bind to an iommufd due to DMA ownership claim and attach to at most one IOAS object (no support of PASID yet). @@ -225,6 +250,7 @@ User visible objects are backed by following datastructures: - iommufd_hwpt_paging for IOMMUFD_OBJ_HWPT_PAGING. - iommufd_hwpt_nested for IOMMUFD_OBJ_HWPT_NESTED. - iommufd_viommu for IOMMUFD_OBJ_VIOMMU. +- iommufd_vdevice for IOMMUFD_OBJ_VDEVICE Several terminologies when looking at these datastructures: From patchwork Wed Oct 9 16:38:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828864 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7146ECEE336 for ; Wed, 9 Oct 2024 17:26:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Xr5DrQg+G8cc8Z6dXFXieKIV4iiNu6QvzVxFa7fDZHI=; b=avWVMz57TqV0AS9NSgayynHBki WHx8CXE72OIa2v3WbRe2aBzw+BUIBmz8j2XlMDDfQQyn7BLKBfAxmdkJjKVbSHDILc7uSbtoQ3bHP yVXCkGp3C93kwBwxuDN8iuIh5y8qirCGSMJI99f2/4gh2PsfgtKl9lgQuGUd00IB7+2fB9phWiBfC oFcJWgY8W3223LfayJtsKfnOiH3k+BFFnIIvd05vf4sPY5mDkYE3G/xXOjlExnVYfGYv/tspYbXYX sHNUrTCVWTAhiSM3o0Q+ykdMyUw5hfT8D10TdpRaW7PJvt3XzoSpn0mWy9w/ZsPhHPjo40PFPLlb5 1fjL4lOQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syaRu-0000000AAWc-2EFo; Wed, 09 Oct 2024 17:26:10 +0000 Received: from mail-dm6nam12on2061e.outbound.protection.outlook.com ([2a01:111:f403:2417::61e] helo=NAM12-DM6-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZiq-0000000A0lB-3TKz for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:38 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=rXmRqyQ1h11lqqeSYcMgE/Q7Y0qXltEipEkjH1GyZv2lqzPKYuD6e3lMyqNeQZ84/VB7+8vC1hBXi8uiwf3yJZok6EdFfvhsrfmVEiN/XpxiZYBbOFMcHJinnh3V6LdU9Vzdxub4fV08D536s1hscSoelsboBhUTvB4p7NUy9igoai55m30Q1UaHrcSGNc3MC7heAyzHeenykgzBFrb/C5RUa2fiWW+L41unm32EG2nJEgglikvR8BbZ0LKaZlf0FQUCIHt8jAW8WfoXVxlckLlUMksv53jgSMDUD2d8oQuzpgDsd7+OP/0QhrwuPB+aLkrFdRSrQD1BCuhEBYF9cA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Xr5DrQg+G8cc8Z6dXFXieKIV4iiNu6QvzVxFa7fDZHI=; b=qZ6kJ7qgeRjGr1sYJMpnPxclVMkJF+Kwi6avYL4CLHyDQElL9Ft0fAdCqs2Hypa8XYeIEejTAmFMdB546Jur/TEnHDrhR9dLVewhsHCyFE30taHtvFILT2UKnS5V+4XrXeMvTs4+ysSLNzUfYX83MNUn0vttiVOBG4ZgR+su71ERX6plmgSw1QUE150LVEkit70MVPUZy16VbGnw/aS+Qj425pLVTYW0pjeLp+rxZOAZUskbe080zT2Xs7ybUIK6DI9V9ALvPM0OSR3GiDpJjb2IVqwUZ7LVln0N96pkAz83m4TyjZW0Wh/b2uHU0yke27D5Tl8/K84Unvuuucn+0A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Xr5DrQg+G8cc8Z6dXFXieKIV4iiNu6QvzVxFa7fDZHI=; b=omHmj42JfieeE+yv2daKJ07i8S63yv4TBc6kHz9A1daXdExg7d/UBJlfvfK4PvZ0v4CTfh0O7zVuzZuWlgXnThwlU9hDdjW2WwAzSmoTSATQjp6jzgSffdG5ZLd+axW917VxpAqiUpIz/2s3NCEEIJa5FlTGrlFJDMyxhaKjRy46tZKaVy59LQSWZ7L/1XDScd3VEnBgFzZ4UaHTQiDb29Awk3V64W68JtqSh/gLcW2STDKJ3wbyvLr5UbzUURngP5iQ2FTy6ebPiuCF0jv6EGsyaY70dU91LFIASraeZMg7o+Rt8n3YA1gu0EQ5Sb6gAbqQzy6+zuciqKy3/WFSkw== Received: from SN6PR01CA0026.prod.exchangelabs.com (2603:10b6:805:b6::39) by DS0PR12MB7993.namprd12.prod.outlook.com (2603:10b6:8:14b::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.16; Wed, 9 Oct 2024 16:39:25 +0000 Received: from SA2PEPF00003F64.namprd04.prod.outlook.com (2603:10b6:805:b6:cafe::72) by SN6PR01CA0026.outlook.office365.com (2603:10b6:805:b6::39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7982.34 via Frontend Transport; Wed, 9 Oct 2024 16:39:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SA2PEPF00003F64.mail.protection.outlook.com (10.167.248.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:25 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:15 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:14 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:39:13 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 14/16] iommu/arm-smmu-v3: Add arm_vsmmu_cache_invalidate Date: Wed, 9 Oct 2024 09:38:26 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F64:EE_|DS0PR12MB7993:EE_ X-MS-Office365-Filtering-Correlation-Id: 31a3db6f-b132-40b4-fa31-08dce880efce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: FuhbHLYqiUVQtBmDjd82dpZ0I8Lu0fGConN5xnj0bmKTW0z0SShQpJ7DunDAhw+QmtA8Kfd1arKzmhRKbWWXwg7Zq7r69VCMtUZ6KFJm4du4TWu00ZkrkuKObkI6moI7hzyeCwU8G6aikBUWDU0Ot1kedPd56HHgvY0RX144EB8dDqCmLyYEolanNgSE8HWq7ySO8EJuBbGWfTcCSJ7k26wGIkDeisVw7UgxXH9Sc2W5D1pCL/NLb4tjm/stZCm8bgHif8z6WB+IMW/DHWYATg8XpwYnLv83URW+CbsFeN17SQV9Kl6Gp1RIGU7XCWEo1X5LYZILSWWX/VQXckFgQxCtY5V/Z6x+w893zdOYcp5L+XI6LTY1BL470tCRyVhUJg0jzK1K3MFbWNO6a1y0Ad5VBZZqfx7UzW5GZG+fOkShJLjUMy+EUF8xK5hGPOQK1caYJjkpsL8/vewOh+hWhcx3Cx8Jb4PlMbyVStlH287P8xheC71PVuKIO/vIWYECG1NLr+dCjn1d/6p17HfQn13fRdqGIRlBiDFtgdANjaK3JqVt4gxS+wXiPx5zbGfSNvNqSkoIQUjPG79AZo26uFK2+snfX3C3SuiOugxdXHLuIfJ2cD02t5BTppYTeZq1H1E/FT/MTthBLGYe8hYsXW9odFDkR77ra0U8uz9XX6Xm3AEwysEIj+2fI66zSgZCPRbUkT/dbZcSAhhPK0Y2eWVKTj/B2Dvzw2oQ0ku6LtLG8RsBb8OPjFeZPKBv7KKeH1vsMGFLVQvkGf6User6GMGlNUZIbHxJVXglwrkdZg+5ipj82o58tYipwhXRRe5Dwd1xDzeyUxAzBqh/j0/SZFqU3Y/MvQ0YLDSjzKafqscgxYaCSThrPOdubbCclpQWt7gxcnVzcW8gcx5+ur5ndHbGUH0dLNH6dnHjLij4kR3WMZtcp9MJdqtwAp4J3plDmXxtfaQo+ch4eaZtYta6B2ZxzJ7TFESRkYvZuWLpn7vpyD6SrnFZjGOZjQ6Ct/JKgJu57BLxugopTYlV3Lw+oswmiPnhTrsH5hRdio4XcB7/AHc4utoY2iedYjiiALFNKwbV5D+JfkOQTegEkeyn8tn3Ke+oesxj6WePcEVXmPKrD1Wdl7GpRcmSWHu+odB6cwrHRlZnLX7i0zGM6zVd+ICIw3it5MWuEyXm3uzDEUyARAUde5Lm6EypwFgeSaPHG8LcBtHdK3CwS8aGF1+3KzV+uIlkWfQ1R9r61+TDISrt5QzBJdw6IGhglN83pTM3ERDY5dvpDf1BDi9hGdWDM9WdFLn0HVmDjv4C58aGHx+kScLTwhMIUT/QwMwGQsgXQWd9yjJUMM7pxFcFg3KC8kyz1D5xpEVoAXE20Mze280XDd7l3lmonEp9Vt8iUaq1 X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:25.5294 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 31a3db6f-b132-40b4-fa31-08dce880efce X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F64.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7993 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_093936_957611_BF711329 X-CRM114-Status: GOOD ( 22.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Implement the vIOMMU's cache_invalidate op for user space to invalidate the IOTLB entries, Device ATS and CD entries that are still cached by hardware. Add struct iommu_viommu_arm_smmuv3_invalidate defining invalidation entries that are simply in the native format of a 128-bit TLBI command. Scan those commands against the permitted command list and fix their VMID/SID fields. Co-developed-by: Eric Auger Signed-off-by: Eric Auger Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 + include/uapi/linux/iommufd.h | 24 ++++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 131 +++++++++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 6 +- 4 files changed, 162 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 844d1dfdea55..000af931a30c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -529,6 +529,7 @@ struct arm_smmu_cmdq_ent { #define CMDQ_OP_TLBI_NH_ALL 0x10 #define CMDQ_OP_TLBI_NH_ASID 0x11 #define CMDQ_OP_TLBI_NH_VA 0x12 + #define CMDQ_OP_TLBI_NH_VAA 0x13 #define CMDQ_OP_TLBI_EL2_ALL 0x20 #define CMDQ_OP_TLBI_EL2_ASID 0x21 #define CMDQ_OP_TLBI_EL2_VA 0x22 @@ -949,6 +950,10 @@ void arm_smmu_attach_commit(struct arm_smmu_attach_state *state); void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, const struct arm_smmu_ste *target); +int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, u64 *cmds, int n, + bool sync); + #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); bool arm_smmu_master_sva_supported(struct arm_smmu_master *master); diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index cd9e135ef563..d9e510ce67cf 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -684,9 +684,11 @@ struct iommu_hwpt_get_dirty_bitmap { * enum iommu_hwpt_invalidate_data_type - IOMMU HWPT Cache Invalidation * Data Type * @IOMMU_HWPT_INVALIDATE_DATA_VTD_S1: Invalidation data for VTD_S1 + * @IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3: Invalidation data for ARM SMMUv3 */ enum iommu_hwpt_invalidate_data_type { IOMMU_HWPT_INVALIDATE_DATA_VTD_S1 = 0, + IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3 = 1, }; /** @@ -725,6 +727,28 @@ struct iommu_hwpt_vtd_s1_invalidate { __u32 __reserved; }; +/** + * struct iommu_viommu_arm_smmuv3_invalidate - ARM SMMUv3 cahce invalidation + * (IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3) + * @cmd: 128-bit cache invalidation command that runs in SMMU CMDQ. + * Must be little-endian. + * + * Supported command list only when passing in a vIOMMU via @hwpt_id: + * CMDQ_OP_TLBI_NSNH_ALL + * CMDQ_OP_TLBI_NH_VA + * CMDQ_OP_TLBI_NH_VAA + * CMDQ_OP_TLBI_NH_ALL + * CMDQ_OP_TLBI_NH_ASID + * CMDQ_OP_ATC_INV + * CMDQ_OP_CFGI_CD + * CMDQ_OP_CFGI_CD_ALL + * + * -EIO will be returned if the command is not supported. + */ +struct iommu_viommu_arm_smmuv3_invalidate { + __aligned_le64 cmd[2]; +}; + /** * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE) * @size: sizeof(struct iommu_hwpt_invalidate) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 5e235fca8f13..1b82579eb252 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -191,6 +191,14 @@ arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, if (smmu_parent->smmu != master->smmu) return ERR_PTR(-EINVAL); + /* + * FORCE_SYNC is not set with FEAT_NESTING. Some study of the exact HW + * defect is needed to determine if arm_vsmmu_cache_invalidate() needs + * any change to remove this. + */ + if (WARN_ON(master->smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) + return ERR_PTR(-EOPNOTSUPP); + ret = iommu_copy_struct_from_user(&arg, user_data, IOMMU_HWPT_DATA_ARM_SMMUV3, ste); if (ret) @@ -213,6 +221,127 @@ arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, return &nested_domain->domain; } +static int arm_vsmmu_vsid_to_sid(struct arm_vsmmu *vsmmu, u32 vsid, u32 *sid) +{ + XA_STATE(xas, &vsmmu->core.vdevs, (unsigned long)vsid); + struct arm_smmu_master *master; + struct device *dev; + int ret = 0; + + xa_lock(&vsmmu->core.vdevs); + dev = vdev_to_dev(xas_load(&xas)); + if (!dev) { + ret = -EIO; + goto unlock; + } + master = dev_iommu_priv_get(dev); + + /* At this moment, iommufd only supports PCI device that has one SID */ + if (sid) + *sid = master->streams[0].id; +unlock: + xa_unlock(&vsmmu->core.vdevs); + return ret; +} + +/* + * Convert, in place, the raw invalidation command into an internal format that + * can be passed to arm_smmu_cmdq_issue_cmdlist(). Internally commands are + * stored in CPU endian. + * + * Enforce the VMID or SID on the command. + */ +static int +arm_vsmmu_convert_user_cmd(struct arm_vsmmu *vsmmu, + struct iommu_viommu_arm_smmuv3_invalidate *cmd) +{ + cmd->cmd[0] = le64_to_cpu(cmd->cmd[0]); + cmd->cmd[1] = le64_to_cpu(cmd->cmd[1]); + + switch (cmd->cmd[0] & CMDQ_0_OP) { + case CMDQ_OP_TLBI_NSNH_ALL: + /* Convert to NH_ALL */ + cmd->cmd[0] = CMDQ_OP_TLBI_NH_ALL | + FIELD_PREP(CMDQ_TLBI_0_VMID, vsmmu->vmid); + cmd->cmd[1] = 0; + break; + case CMDQ_OP_TLBI_NH_VA: + case CMDQ_OP_TLBI_NH_VAA: + case CMDQ_OP_TLBI_NH_ALL: + case CMDQ_OP_TLBI_NH_ASID: + cmd->cmd[0] &= ~CMDQ_TLBI_0_VMID; + cmd->cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, vsmmu->vmid); + break; + case CMDQ_OP_ATC_INV: + case CMDQ_OP_CFGI_CD: + case CMDQ_OP_CFGI_CD_ALL: + u32 sid, vsid = FIELD_GET(CMDQ_CFGI_0_SID, cmd->cmd[0]); + + if (arm_vsmmu_vsid_to_sid(vsmmu, vsid, &sid)) + return -EIO; + cmd->cmd[0] &= ~CMDQ_CFGI_0_SID; + cmd->cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, sid); + break; + default: + return -EIO; + } + return 0; +} + +static int arm_vsmmu_cache_invalidate(struct iommufd_viommu *viommu, + struct iommu_user_data_array *array) +{ + struct arm_vsmmu *vsmmu = container_of(viommu, struct arm_vsmmu, core); + struct iommu_viommu_arm_smmuv3_invalidate *last; + struct iommu_viommu_arm_smmuv3_invalidate *cmds; + struct iommu_viommu_arm_smmuv3_invalidate *cur; + struct iommu_viommu_arm_smmuv3_invalidate *end; + struct arm_smmu_device *smmu = vsmmu->smmu; + int ret; + + cmds = kcalloc(array->entry_num, sizeof(*cmds), GFP_KERNEL); + if (!cmds) + return -ENOMEM; + cur = cmds; + end = cmds + array->entry_num; + + static_assert(sizeof(*cmds) == 2 * sizeof(u64)); + ret = iommu_copy_struct_from_full_user_array( + cmds, sizeof(*cmds), array, + IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3); + if (ret) + goto out; + + last = cmds; + while (cur != end) { + ret = arm_vsmmu_convert_user_cmd(vsmmu, cur); + if (ret) + goto out; + + /* FIXME work in blocks of CMDQ_BATCH_ENTRIES and copy each block? */ + cur++; + if (cur != end && (cur - last) != CMDQ_BATCH_ENTRIES - 1) + continue; + + /* FIXME always uses the main cmdq rather than trying to group by type */ + ret = arm_smmu_cmdq_issue_cmdlist(smmu, &smmu->cmdq, last->cmd, + cur - last, true); + if (ret) { + cur--; + goto out; + } + last = cur; + } +out: + array->entry_num = cur - cmds; + kfree(cmds); + return ret; +} + +const struct iommufd_viommu_ops arm_vsmmu_ops = { + .cache_invalidate = arm_vsmmu_cache_invalidate, +}; + struct iommufd_viommu * arm_vsmmu_alloc(struct iommu_device *iommu_dev, struct iommu_domain *parent, struct iommufd_ctx *ictx, unsigned int viommu_type) @@ -225,7 +354,7 @@ arm_vsmmu_alloc(struct iommu_device *iommu_dev, struct iommu_domain *parent, if (viommu_type != IOMMU_VIOMMU_TYPE_ARM_SMMUV3) return ERR_PTR(-EOPNOTSUPP); - vsmmu = iommufd_viommu_alloc(ictx, arm_vsmmu, core, NULL); + vsmmu = iommufd_viommu_alloc(ictx, arm_vsmmu, core, &arm_vsmmu_ops); if (IS_ERR(vsmmu)) return ERR_CAST(vsmmu); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 6a23e6dcd5cf..a2bbd140e232 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -766,9 +766,9 @@ static void arm_smmu_cmdq_write_entries(struct arm_smmu_cmdq *cmdq, u64 *cmds, * insert their own list of commands then all of the commands from one * CPU will appear before any of the commands from the other CPU. */ -static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq *cmdq, - u64 *cmds, int n, bool sync) +int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, u64 *cmds, int n, + bool sync) { u64 cmd_sync[CMDQ_ENT_DWORDS]; u32 prod; From patchwork Wed Oct 9 16:38:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC797CEE336 for ; Wed, 9 Oct 2024 17:27:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=mhNOrtl8ngqFvDkhNDxq9eJsPpkGfYBdkM2wPGCOqls=; b=LMxN2XFntKQMbqbca9OgyiA7Vl iKPKPc6mOernxiMDgXK/wvpYdfv4zS4nnkUtHxBg5fxn8CJCQQik788/xCNSSM1E7xPIwVPUuduEZ USVS8iLX1ILMGtlZy8i4Y8OYOFe9t6WmC8RdHl+fmNB7mgALq7uynW6sHnGkdikyVFUP3yPtm8Opc SubyfayElhX1X7FABv2chW2kPiGfJUnWwDw9PnWb0jbzAEqnUlwx873OgrC8DC0WHdplQtRLHe3eG vOj8GczjM3jqXWLdbOE7aKdhgqjCNTBgfjl9OQQNWqdqhGFuiSwYkilzx/kGiO7kDSbbW2FppvtKh UtyjR6hA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syaTB-0000000AAeS-4955; Wed, 09 Oct 2024 17:27:29 +0000 Received: from mail-sn1nam02on20625.outbound.protection.outlook.com ([2a01:111:f400:7ea9::625] helo=NAM02-SN1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZis-0000000A0mB-1DQo for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:40 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=tqQW/iuDu0OPAQSHMzb5UUmd+JmjC17sWS/bPIQ+2Ug6ovvB5vyHjdaEGE/fdSPDvuou5jfH2QcEmz4+o7Hhai2lTipVccs7q/zlXYA24gm8B6xOWnTuRsnlHwowjiM0Mij5B0d7MbpQHcc9eTM/a/SQ31azmfVOUbUVlI1zyeaiDi7ImtGOsIV76/v70mB7XeX1aia5T5NCtv+wIFZU6GBVMt1F4Skl5MtQE6YjzTMtTrzF4CgYIV+GK9yDigPXkny+j2jLiGPranxyP5pTpDgw77nmn4RA2zVSRolmHcndfdhuZp6ENvKvzmHnlA6KZRjZ3c94gO9vgxwAcpInRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mhNOrtl8ngqFvDkhNDxq9eJsPpkGfYBdkM2wPGCOqls=; b=PxWKkXyNeKEljbRjE3967yQKocGcYsUJ9n6Otm0ciFKIVSdmvL49sHVLaaOBJvjK91/i6M+bvTupUsQxrM9E7DRY8OVInSTToDf2/URPc5T33fq/0/LblQ3cK1hET8OBSU7sLkNRtdvxnZ4CyxWwVd6aTHwfMH0mbpHhyCr9BABAw4Ja10O+keTm2WCjLLtutQxT8cJQb+KsDZexupoNPi+Im3jXMK12a4vTKNDGctnKS3KA6k/8zpiujcukcxCkDNDHwGhT5dZfgxMl/1+2ncL7fF/U9f2BgsiBbVRhF99IWTjfBiZ7C0Qio2v0Z5cYZA+P4OSWxEvA0mMqkbslAg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mhNOrtl8ngqFvDkhNDxq9eJsPpkGfYBdkM2wPGCOqls=; b=bLaWzkSoexE3I9fpEvt/PMDHfi7X0Q8cKQUVGKHoW8RlNBToHl0/mL9UfB7XQsbe+TwDaahgGfIqD99MIsymrzOdGZcZDakDmngbkFni6lUm+5gUkw5DovahWFZMXdyH+/JaMvYCu8KQH5mCPchM6Qe/6GZ9NzeVl8FTeJVEPDA7xypm5nLkgJw7tRFJY/58/H1mNYomPRJlG6R6zvUeicDLRE45tbsuR1CdhLKc7M6mpSYPfLdAWBJlNeuQFnxddOfmESsRUafRhWqkz9Bmunh4XrX2pTT58tWsXR8eQ9PKngC0SFIrL1ro3qq1cujbURqqjQ6R4MJnGq0+qm6D2w== Received: from DM6PR02CA0146.namprd02.prod.outlook.com (2603:10b6:5:332::13) by CH3PR12MB8403.namprd12.prod.outlook.com (2603:10b6:610:133::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.23; Wed, 9 Oct 2024 16:39:29 +0000 Received: from DS3PEPF000099DF.namprd04.prod.outlook.com (2603:10b6:5:332:cafe::38) by DM6PR02CA0146.outlook.office365.com (2603:10b6:5:332::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.17 via Frontend Transport; Wed, 9 Oct 2024 16:39:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by DS3PEPF000099DF.mail.protection.outlook.com (10.167.17.202) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:28 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:16 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:15 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:39:15 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 15/16] iommu/arm-smmu-v3: Allow ATS for IOMMU_DOMAIN_NESTED Date: Wed, 9 Oct 2024 09:38:27 -0700 Message-ID: <6c6a25c296eb988d590883c296c21ebbedd53f72.1728491532.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DF:EE_|CH3PR12MB8403:EE_ X-MS-Office365-Filtering-Correlation-Id: 9fb22699-253f-4f66-b349-08dce880f1d2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: maQjsK/scGjNzLapr+wPuvlvX7d6caK/9hF1tYo7phZauhoe7RW20GAjGf/ZupFPF+mci0cJsnw1Nb/jJtS7OprDhCwF5QwICm1ZtNqNxkEnHWCM8X965BeWdhu4mYrXLk/eaNHQls10NvgvzkL3yo10UrPr2KmV4sD5xaSvpH/otbLFk0cx7B4fzUP5SK1yL874iJEn42I5GG22FSfkD77IL00kQyp+opO9FY3G3Aqd9PAV9Vk1WE/yPpBXEbgpzGasNZJNs2N7+fG6G916Z7b+jE8PpK1DiRdDo3J9qRl+06dvFN15cICpBRU7JuPZPMa2NOKgj0ZxijhBUJv86z0anQml1L7O2shSQD8ZTDGAnCn7hIARQXijvbTzGtvQGHLB9DZ5/B3TCS6cUeBG6bwNGDFdPeFnFrN9HMCwqHlXdNKFUh5GwCDZVm1y8+trLgDOe9AtluenSONsvf/uhkQdsHrv+RzRm5O8YR6c7Uxgk+lHANfctqLdYPUqwzf1MFKAr5rZOiBOI2gzLHjSib+xxw1shUvZCray+OIdDhP8zM5wJ6Ktr9E2VaJvmcGSSdlSSaTfPInjeqB8Tj6W8X2l4Du8gNdnL1Txmfzg9uN50olQEyRGcaM1czDN05IbG+QCudCD6MaMOYNgsxGBWguNndnoPs6C7ZEFAbKRA8DcuUqDTCdw1shCuyscrwhHcxFyqSJmieF3d9hjGJwHuX/Lj9dDzhsOICIVojTrtp+/QbgpyfNELZbQbacCl40dtgPIUccPgcoGlUN8HInz3XS4gd/Q6BLhZohtj1JGmqoYusUak4TWsUh2sK6IRsrUEUTYxs4SBE0eMbqb4nuIyMCVn8P+QI1evRnekOYHNjqcmj2cm8W8zMkl19IbFQHQFoiWf+E0B4LmwP5hkjfghhtNl7dluzPPsgbqgIR5xYqvdyyMormnKAS7VlYZQ4AnbgcLOfeGLE1IovhQYBjWlGHZShQYku7R0xqer13TcTCMfMhvLuXjteJ+fpVAaXMMqrXdqQEBPUmQ1kY1om3SI0uWQej0w1ST+ynVZxkPd1pXM7f11upVNse2MlCBggltwGtSZJPZfIZkJf7qww9JC0/gnBtKC9Zf80Qa5V9PLdlamTAIpoSZxtsPsz8kq3S7JUTdxrYXhaXgNYN3xSRhjA4rsa0PX4wA/VEPw5Y43iFVaorGz2vFnNCdpCnJ38+DGxCFaPMQuUO5PV/e6tHquL1kcZ7+pPmWrkxV30waanoDvOsloTQbd0iKqJrFqrb7EgnGqY9Xd9kteIucU9MiwQQF6VphX8rNwBRypEQnGGc1r1IfccEUztbqmf1FuKnlks4uuPj23DYOENtI5BqBAhXaVtarpdN3+rmRk0GpwQc= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(7416014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:28.8936 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9fb22699-253f-4f66-b349-08dce880f1d2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8403 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_093938_492006_E42EAAA8 X-CRM114-Status: GOOD ( 21.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jason Gunthorpe Now, ATC invalidation can be done with the vIOMMU invalidation op. A guest owned IOMMU_DOMAIN_NESTED can do an ATS too. Allow it to pass in the EATS field via the vSTE words. Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++- include/uapi/linux/iommufd.h | 2 +- .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 31 ++++++++++++++++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 27 +++++++++++++--- 4 files changed, 54 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 000af931a30c..470bc3ee25ef 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -305,7 +305,7 @@ static inline u32 arm_smmu_strtab_l2_idx(u32 sid) #define STRTAB_STE_1_NESTING_ALLOWED \ cpu_to_le64(STRTAB_STE_1_S1DSS | STRTAB_STE_1_S1CIR | \ STRTAB_STE_1_S1COR | STRTAB_STE_1_S1CSH | \ - STRTAB_STE_1_S1STALLD) + STRTAB_STE_1_S1STALLD | STRTAB_STE_1_EATS) /* * Context descriptors. @@ -838,6 +838,7 @@ struct arm_smmu_domain { struct arm_smmu_nested_domain { struct iommu_domain domain; struct arm_smmu_domain *s2_parent; + bool enable_ats : 1; __le64 ste[2]; }; @@ -879,6 +880,7 @@ struct arm_smmu_master_domain { struct list_head devices_elm; struct arm_smmu_master *master; ioasid_t ssid; + bool nested_ats_flush : 1; }; static inline struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index d9e510ce67cf..9527a4ecfd56 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -404,7 +404,7 @@ struct iommu_hwpt_vtd_s1 { * a user stage-1 Context Descriptor Table. Must be little-endian. * Allowed fields: (Refer to "5.2 Stream Table Entry" in SMMUv3 HW Spec) * - word-0: V, Cfg, S1Fmt, S1ContextPtr, S1CDMax - * - word-1: S1DSS, S1CIR, S1COR, S1CSH, S1STALLD + * - word-1: EATS, S1DSS, S1CIR, S1COR, S1CSH, S1STALLD * * -EIO will be returned if @ste is not legal or contains any non-allowed field. * Cfg can be used to select a S1, Bypass or Abort configuration. A Bypass diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 1b82579eb252..b491017921df 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -103,8 +103,6 @@ static int arm_smmu_attach_dev_nested(struct iommu_domain *domain, .master = master, .old_domain = iommu_get_domain_for_dev(dev), .ssid = IOMMU_NO_PASID, - /* Currently invalidation of ATC is not supported */ - .disable_ats = true, }; struct arm_smmu_ste ste; int ret; @@ -115,6 +113,15 @@ static int arm_smmu_attach_dev_nested(struct iommu_domain *domain, return -EBUSY; mutex_lock(&arm_smmu_asid_lock); + /* + * The VM has to control the actual ATS state at the PCI device because + * we forward the invalidations directly from the VM. If the VM doesn't + * think ATS is on it will not generate ATC flushes and the ATC will + * become incoherent. Since we can't access the actual virtual PCI ATS + * config bit here base this off the EATS value in the STE. If the EATS + * is set then the VM must generate ATC flushes. + */ + state.disable_ats = !nested_domain->enable_ats; ret = arm_smmu_attach_prepare(&state, domain); if (ret) { mutex_unlock(&arm_smmu_asid_lock); @@ -140,8 +147,10 @@ static const struct iommu_domain_ops arm_smmu_nested_ops = { .free = arm_smmu_domain_nested_free, }; -static int arm_smmu_validate_vste(struct iommu_hwpt_arm_smmuv3 *arg) +static int arm_smmu_validate_vste(struct iommu_hwpt_arm_smmuv3 *arg, + bool *enable_ats) { + unsigned int eats; unsigned int cfg; if (!(arg->ste[0] & cpu_to_le64(STRTAB_STE_0_V))) { @@ -158,6 +167,18 @@ static int arm_smmu_validate_vste(struct iommu_hwpt_arm_smmuv3 *arg) if (cfg != STRTAB_STE_0_CFG_ABORT && cfg != STRTAB_STE_0_CFG_BYPASS && cfg != STRTAB_STE_0_CFG_S1_TRANS) return -EIO; + + /* + * Only Full ATS or ATS UR is supported + * The EATS field will be set by arm_smmu_make_nested_domain_ste() + */ + eats = FIELD_GET(STRTAB_STE_1_EATS, le64_to_cpu(arg->ste[1])); + arg->ste[1] &= ~cpu_to_le64(STRTAB_STE_1_EATS); + if (eats != STRTAB_STE_1_EATS_ABT && eats != STRTAB_STE_1_EATS_TRANS) + return -EIO; + + if (cfg == STRTAB_STE_0_CFG_S1_TRANS) + *enable_ats = (eats == STRTAB_STE_1_EATS_TRANS); return 0; } @@ -170,6 +191,7 @@ arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, struct arm_smmu_nested_domain *nested_domain; struct arm_smmu_domain *smmu_parent; struct iommu_hwpt_arm_smmuv3 arg; + bool enable_ats = false; int ret; if (flags || !(master->smmu->features & ARM_SMMU_FEAT_NESTING)) @@ -204,7 +226,7 @@ arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, if (ret) return ERR_PTR(ret); - ret = arm_smmu_validate_vste(&arg); + ret = arm_smmu_validate_vste(&arg, &enable_ats); if (ret) return ERR_PTR(ret); @@ -215,6 +237,7 @@ arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, nested_domain->domain.type = IOMMU_DOMAIN_NESTED; nested_domain->domain.ops = &arm_smmu_nested_ops; nested_domain->s2_parent = smmu_parent; + nested_domain->enable_ats = enable_ats; nested_domain->ste[0] = arg.ste[0]; nested_domain->ste[1] = arg.ste[1] & ~cpu_to_le64(STRTAB_STE_1_EATS); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index a2bbd140e232..1cb4afe7a90a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2107,7 +2107,16 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, if (!master->ats_enabled) continue; - arm_smmu_atc_inv_to_cmd(master_domain->ssid, iova, size, &cmd); + if (master_domain->nested_ats_flush) { + /* + * If a S2 used as a nesting parent is changed we have + * no option but to completely flush the ATC. + */ + arm_smmu_atc_inv_to_cmd(IOMMU_NO_PASID, 0, 0, &cmd); + } else { + arm_smmu_atc_inv_to_cmd(master_domain->ssid, iova, size, + &cmd); + } for (i = 0; i < master->num_streams; i++) { cmd.atc.sid = master->streams[i].id; @@ -2630,7 +2639,8 @@ static void arm_smmu_disable_pasid(struct arm_smmu_master *master) static struct arm_smmu_master_domain * arm_smmu_find_master_domain(struct arm_smmu_domain *smmu_domain, - struct arm_smmu_master *master, ioasid_t ssid) + struct arm_smmu_master *master, ioasid_t ssid, + bool nested_ats_flush) { struct arm_smmu_master_domain *master_domain; @@ -2639,7 +2649,8 @@ arm_smmu_find_master_domain(struct arm_smmu_domain *smmu_domain, list_for_each_entry(master_domain, &smmu_domain->devices, devices_elm) { if (master_domain->master == master && - master_domain->ssid == ssid) + master_domain->ssid == ssid && + master_domain->nested_ats_flush == nested_ats_flush) return master_domain; } return NULL; @@ -2670,13 +2681,18 @@ static void arm_smmu_remove_master_domain(struct arm_smmu_master *master, { struct arm_smmu_domain *smmu_domain = to_smmu_domain_devices(domain); struct arm_smmu_master_domain *master_domain; + bool nested_ats_flush = false; unsigned long flags; if (!smmu_domain) return; + if (domain->type == IOMMU_DOMAIN_NESTED) + nested_ats_flush = to_smmu_nested_domain(domain)->enable_ats; + spin_lock_irqsave(&smmu_domain->devices_lock, flags); - master_domain = arm_smmu_find_master_domain(smmu_domain, master, ssid); + master_domain = arm_smmu_find_master_domain(smmu_domain, master, ssid, + nested_ats_flush); if (master_domain) { list_del(&master_domain->devices_elm); kfree(master_domain); @@ -2743,6 +2759,9 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, return -ENOMEM; master_domain->master = master; master_domain->ssid = state->ssid; + if (new_domain->type == IOMMU_DOMAIN_NESTED) + master_domain->nested_ats_flush = + to_smmu_nested_domain(new_domain)->enable_ats; /* * During prepare we want the current smmu_domain and new From patchwork Wed Oct 9 16:38:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13828866 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BF38CEE336 for ; Wed, 9 Oct 2024 17:28:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=B+qA0TvXiEAf71akvo2Q6CNGY6zTvvtj1HugivbJ7RM=; b=jBjp9H01nw4wneDd9qe5OtbLsE lxnG39g/FdNVEtrepXtVnAL/txAbeIkostwpeAHuwxeTbrBFIX3jxT4n00MpAep0mFO7w3SsuGYSB iRXf1esM9mVXzgOGZSbk5WQW1VDKDkSG+g46lFFfUDPfNdKtSOrfjVc0oa2F1B6UOdTULVU/tZUdw ByeI4eImTjPrSVGx24xSnjO4CaUTpqBNvG5+GG80Mv8cXRDELbsezr7IP5KQEAVRr+bB+6h9+eG15 5tpxFyxGOfeiHVI0wlNNfI5cJwjkgmy+tVFqGca3dhfH3ZQ3VXTcv18YReSGX3b3sKk1NmQ7sh7Eq 0e4i6+wg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1syaUT-0000000AAmr-1vdb; Wed, 09 Oct 2024 17:28:49 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZiw-0000000A0oI-0zHI for linux-arm-kernel@bombadil.infradead.org; Wed, 09 Oct 2024 16:39:42 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Type:Content-Transfer-Encoding :MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From: Sender:Reply-To:Content-ID:Content-Description; bh=B+qA0TvXiEAf71akvo2Q6CNGY6zTvvtj1HugivbJ7RM=; b=RmIya6ApLnLluCo9chwufERBRw D129o0Cp5955ZA80n5kuzK/+1JJeerpjrJeioQTvXRK2V7YJopl1pbz6+rurWghA06FSAwZihDElR P/mdlUq4cVpDNmBdwjfFmzmRgsVcbqE0xqqmMxqN88FTssU66uazsPcYDzqBxj4rBHNrokaRVkRSX J+6jXRPbFajvI4YRFys4sWG6xR55eM4p4Fen5fNBb9hH49qLfFPuzvds+tkeNDf+RljdBdEPqgdd9 7W75C/ZQKaRrxsUJOkwqvvBW8ARuZcV9NR17/KG2W3R3jZnUBnHy2oarY5LYWWbaEKvZ6jW41wVYK EGmD2UnQ==; Received: from mail-dm6nam11on2061c.outbound.protection.outlook.com ([2a01:111:f403:2415::61c] helo=NAM11-DM6-obe.outbound.protection.outlook.com) by desiato.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1syZit-000000052k8-0Z8w for linux-arm-kernel@lists.infradead.org; Wed, 09 Oct 2024 16:39:40 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ZWmg2brFGXCt6vN0Ikn+Y4xNhOUhxAgRmsgMCcQZm2sFDaXr9j9elCXxcSEO33iM1iFgjlW0O04ZQk9UwDmGXCMGW721W+rLf0LxWBolMhDZszao6Tj3A8XZbsxvJ7l4s1VZMZ9xwr8d8yOCibF3DQ0tG27oJhI7zPevQPMkKEWyQRA8yyU5xTH7hv6aThPV/RmhmMS/t8C6vhiiDy0YV0R6Q2lBEYsSt0yfPL13EAjG1ijfxy0tnFN9n/8dbAFntum0uc0L26MG16WirBr76FcftxJfE5CP+OPqAkgMZhp9HsdeONBvHNjXIfwdbHiMnjzNAv8HcS92DL6HLBDlqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=B+qA0TvXiEAf71akvo2Q6CNGY6zTvvtj1HugivbJ7RM=; b=iBwM3Aw6JCSlZBdPUNX3GhSGuVmcCen5M4affLvK5ysAbzJyyXWy2J2ok5QQc1KkqNqN6bnmCrCF/TD3V9S32FfBqRrAQ1eYs/RLH/ZwYBbzNNSI3Du1rVkPo4ykN2+Aigi0WWrxVmAnh+toUAJBx/9H5skrEQ4TQDf9vd/S5YbiQeynq4b1YAeAApuV7LSvwyVTtZIiwoamIZnHBpZKVNrlWzuTYSa34+lOE4Ka5S02hjClwrfaZ/s/9gR+soDK3rBA0QvhFxezWhNLXLKABB0wFbmhOcy3dhUOowULJ8YwvzezYne15JCTjRFcJSH1MCjw3OSBHCFsmNGLrIHvbA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=B+qA0TvXiEAf71akvo2Q6CNGY6zTvvtj1HugivbJ7RM=; b=icI4F0stppVz2SeREutZiKSgxEIaUSekgrQvhI6vPLCIlRsndYoupmYfsfcLRNo/ElghTcdlcfgsX4av5QMP5FL11aCi6jYGTD6Vm+aDh5ZDzJqVOTaf1Px/AcP0zcV2sMAZO/Ml4nLQI+EDxU2P57Gdn9Y9txkpKcfVtmo1rtfy9wbZDhtEJ6kMYwL4c+YI8xBpgfO3kCYfYMX66urooIZWuhmI3ciRBj8GqfZEk+XqZL0fSM/NMLGtXP2CBcPmLgG69BmcxE8ZXQAxSEJWQLUS5eohSCqHDsOmu1278/aKLdiDtrZ9rYps3v6rX7xgF/v1rf4hfgoFthxTv+oONA== Received: from SA1P222CA0110.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:3c5::22) by DS0PR12MB6390.namprd12.prod.outlook.com (2603:10b6:8:ce::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.16; Wed, 9 Oct 2024 16:39:28 +0000 Received: from SA2PEPF00003F63.namprd04.prod.outlook.com (2603:10b6:806:3c5:cafe::5) by SA1P222CA0110.outlook.office365.com (2603:10b6:806:3c5::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.17 via Frontend Transport; Wed, 9 Oct 2024 16:39:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SA2PEPF00003F63.mail.protection.outlook.com (10.167.248.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Wed, 9 Oct 2024 16:39:28 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:18 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 9 Oct 2024 09:39:17 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 9 Oct 2024 09:39:16 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 16/16] iommu/arm-smmu-v3: Update comments about ATS and bypass Date: Wed, 9 Oct 2024 09:38:28 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F63:EE_|DS0PR12MB6390:EE_ X-MS-Office365-Filtering-Correlation-Id: a1d9fedd-59e9-4d15-ea16-08dce880f1b7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: lcOCo9ImSp4HoRXegM+zQ769ZLy8cJEoQ6uZONhprDKXJlTop9mz1h9VNQfMoy2VWShcS//GUs7S4RoHPaYl+rXmJb2yEFUf7W6zgfJ2dA4WngDMYwOEuN5gvUVz8Ugmi/vxnkx6g70l+JIThEx831dK/f41v962HccPHlmSpyVE3Bpcd3cX/3cShS8LRC54RC1syEnfuZlK06RdHVtTWkEk7sTUe3/2+ip+JndEN493V65JC0WKZSCyd2x1oXL3AeIQtPK4iwPXjCfI6qUQvR6HUvPKD7gc3lPcsyBxAW7tDznzQa4oP1zEU1YDTTvo2VcRyMi2Xfco7QjdC4BSlooDbHVybQGwGc2HvztvhxHmeuCoPb9ldcuSo5Zkjg0r2H/QK9JflFFNSzDYTiGHx/uw4liofEX6meO2vGLNmKT7sp487BNUtI6N3TbI1kB9J8SrM7tecmgNpZyyZfVTfS7geqQOfSeYmMNQT0SYjqxqGHoJB7/W5ZEo0x+K2ivG2TynD5eXp4pV0gv3tc3wlgSkkXI0Uq/+cVRQ1R5iqb1BpsVOz7a51w2PIgZVmWB6u2q2t9OJ1pFL4uGIPu4sghcRlk3VDLLRGJ1tnCyT/HoNzrBWnoHUE6o5DjfQHu1lAfVyy+oyBquS9rppWVeh2WHmAxOjW82ApaEXEcPjHjWh7c/SsU21erLB5OLwk/HsKsDmxVMPEUYV5SAcUJmXk9BV328IOyBBUnpuXjrTE5qCmLVCkekSvuDEARe6P8GAtOnk9XHU+KHBU1kAzzGB5Dw1DW9HNccH8K9yzejQM2vU7ekWQjPwrgxpZblVDgWUDOz+NJlLOHhQ5bL4kvW5c5rwmKR1fpcp9C2xUQ2UzSXkg+t71gmSRyo9g/b+35ILIinTGtBCMZVUoaNDBC7715nYiCGKC7NKfmhDz1VHwDYB75GU94kD22h2akBy6MNmjnb7VwX7wNl/qfUtmitnQq1Le2Oweg/9da8TkD3IX484jnCL1rxNqbfOLBKGUIIcpmc8CwwuZ/iIEG8XIsKsxEWzt3R4gm5QGIPo0MCrEgKn2GaHpvx0R6dvaCKTMQbIHp+GtZJqLbb0jqZqnEEh6Wz5TXoVrXrwY/Iq+5fjsnMORCyJg/RKzgOd8aft0f2WNl66yqABU6tuSfcEsRL6MpIxWh8boOyvomUusS6AEkyGk2tlAzYrs6l9xZC4l7e2RGyaMTPtGWFs1QEfdUbW5kU+uRtqIb90eb4zMLsyFigFDcaLiHf2pcuSTWmsSgtIHXPYb1Le5DJmwtwk3cCkH/tskWHeHtQ8TI3/yMHV6OWE37EgAge00SaJJqViAUbR5LeaSS0vIZv6vO97qAPZmY/vQfJNCqZF+K/st45seTYAMyk7z8FmexQ1Vb+gaeo2 X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:28.7494 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1d9fedd-59e9-4d15-ea16-08dce880f1b7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F63.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6390 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241009_173939_339594_BD0C0477 X-CRM114-Status: GOOD ( 18.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jason Gunthorpe The SMMUv3 spec has a note that BYPASS and ATS don't work together under the STE EATS field definition. However there is another section "13.6.4 Full ATS skipping stage 1" that explains under certain conditions BYPASS and ATS do work together if the STE is using S1DSS to select BYPASS and the CD table has the possibility for a substream. When these comments were written the understanding was that all forms of BYPASS just didn't work and this was to be a future problem to solve. It turns out that ATS and IDENTITY will always work just fine: - If STE.Config = BYPASS then the PCI ATS is disabled - If a PASID domain is attached then S1DSS = BYPASS and ATS will be enabled. This meets the requirements of 13.6.4 to automatically generate 1:1 ATS replies on the RID. Update the comments to reflect this. Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 1cb4afe7a90a..236f930f9a97 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2745,9 +2745,14 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, * Translation Requests and Translated transactions are denied * as though ATS is disabled for the stream (STE.EATS == 0b00), * causing F_BAD_ATS_TREQ and F_TRANSL_FORBIDDEN events - * (IHI0070Ea 5.2 Stream Table Entry). Thus ATS can only be - * enabled if we have arm_smmu_domain, those always have page - * tables. + * (IHI0070Ea 5.2 Stream Table Entry). + * + * However, if we have installed a CD table and are using S1DSS + * then ATS will work in S1DSS bypass. See "13.6.4 Full ATS + * skipping stage 1". + * + * Disable ATS if we are going to create a normal 0b100 bypass + * STE. */ state->ats_enabled = !state->disable_ats && arm_smmu_ats_supported(master); @@ -3072,8 +3077,10 @@ static void arm_smmu_attach_dev_ste(struct iommu_domain *domain, if (arm_smmu_ssids_in_use(&master->cd_table)) { /* * If a CD table has to be present then we need to run with ATS - * on even though the RID will fail ATS queries with UR. This is - * because we have no idea what the PASID's need. + * on because we have to assume a PASID is using ATS. For + * IDENTITY this will setup things so that S1DSS=bypass which + * follows the explanation in "13.6.4 Full ATS skipping stage 1" + * and allows for ATS on the RID to work. */ state.cd_needs_ats = true; arm_smmu_attach_prepare(&state, domain);