From patchwork Thu Oct 10 15:31:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiuxu Zhuo X-Patchwork-Id: 13830479 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A8BD77F1B; Thu, 10 Oct 2024 15:54:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575661; cv=none; b=IIENcNXDJJuR8TH4hZVbNbP5LBynHaFb0HZs7CQeO7/lhDXjJ469+o3amID9daUytOmnx+2gKJcJzsLbTzyGAH44wRh7NDTtlRdVcQlJHORYIIiGK1KC58wanj/D4mQ3kAFeeugiKN7hYDbzVuUXysebFdqA41YsewkESWMo1RA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575661; c=relaxed/simple; bh=1WynrAEJvNfnKoJ9G8ZFXV7mNdQCAvS6jbzSEf4O3A4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=Uxx9b3qw+Q+b8yRpbyWzwSS6XlJulzhpgfiVIqX2ayqx55z5m1eB/7UnsUtVZ+ex6oUF/AQd+PvO924EgJWjEwUO2j1Gx2B3b3TiKSxAbIPuv2AevZ5EVcTMF8zcobEgpxY9/AhdCW38CKHk8qarp+CsczYeqqKjxqm9BDD+Zl0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cDDOJUvL; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cDDOJUvL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728575661; x=1760111661; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=1WynrAEJvNfnKoJ9G8ZFXV7mNdQCAvS6jbzSEf4O3A4=; b=cDDOJUvLN3EJBUt1FkIZf1+sMz23wJLKch72VGKmXMrsBvWhTYC3BRKC KtBBOvrh+ukPO96N1AtBUCZkJFYwGf+6jR0XhFZsXtCBM3y2bxst3CHj+ DCJjPJNiH8r3wJd1IxHiS9IxC9A4hYFEuwu1FFdWEU4ZyS64Nlf3IY2Un yQLMzx9Tyvcc/Ya40BLvU3Cl+eV6dI5b/r0KE1EM7VwpAqowb+sRXirb5 Mzt6EXaPPKHi41HCySu+XkW/fgM6yucpAB49m0XO1C8lXK+GgJMZJ1f98 T0GmIgCoabCrKfMc+YGAr3CHizron4ELyzKqOeKFyZZscd6P3lpFuBHGu A==; X-CSE-ConnectionGUID: oXxcA21iQ7OqcuTqUvN+FQ== X-CSE-MsgGUID: dvdZclTkQeKNpveUggwZdw== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="31643511" X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="31643511" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:54:20 -0700 X-CSE-ConnectionGUID: X3871bsAQyq+IdW4xEcZGw== X-CSE-MsgGUID: F/4SHDI7ToOi6hTJ8EQwSg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="81221751" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:54:17 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH 01/10] x86/mce/dev-mcelog: Use xchg() to get and clear the flags Date: Thu, 10 Oct 2024 23:31:53 +0800 Message-Id: <20241010153202.30876-2-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241010153202.30876-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Using xchg() to atomically get and clear the MCE log buffer flags, streamlines the code and reduces the text size by 20 bytes. $ size dev-mcelog.o.* text data bss dec hex filename 3013 360 160 3533 dcd dev-mcelog.o.old 2993 360 160 3513 db9 dev-mcelog.o.new No functional changes intended. Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/dev-mcelog.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/dev-mcelog.c b/arch/x86/kernel/cpu/mce/dev-mcelog.c index af44fd5dbd7c..8d023239ce18 100644 --- a/arch/x86/kernel/cpu/mce/dev-mcelog.c +++ b/arch/x86/kernel/cpu/mce/dev-mcelog.c @@ -264,15 +264,8 @@ static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, return put_user(sizeof(struct mce), p); case MCE_GET_LOG_LEN: return put_user(mcelog->len, p); - case MCE_GETCLEAR_FLAGS: { - unsigned flags; - - do { - flags = mcelog->flags; - } while (cmpxchg(&mcelog->flags, flags, 0) != flags); - - return put_user(flags, p); - } + case MCE_GETCLEAR_FLAGS: + return put_user(xchg(&mcelog->flags, 0), p); default: return -ENOTTY; } From patchwork Thu Oct 10 15:31:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiuxu Zhuo X-Patchwork-Id: 13830485 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BA301C7B68; Thu, 10 Oct 2024 15:55:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575724; cv=none; b=P3ik2SFiuqJT5yZk5OuqBQbf7Q6kKm7XzuW9k4NvEYKkua6hqD3imH9LaUIahiwmYBfQS7v5c4IcmHTy0E69D9CGR3MMJCqDK/Uaiw4sX5OxiANVR7iLRdNxVWCXovKqtqWglUnFv9sE6ctKrAyOcw1/AUCre1W9RbHyx2eVl/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575724; c=relaxed/simple; bh=BMNK5iWgnrtok45sdEr4evWdiRWQlKExtRudo8k9bE4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=t9EOuPcag699LJuQO19DYCJDDFkEH8mqNb016vU0ms7yyJ9KzKRb9rmN1dOLGYIRsM3TvaQBrfcijS24LIwXonkT1p1M1e/q3vDGgAGQa/BpM52HEVp9r1aXt6Lha8urX8VPVHsmp5RpGdg/MCs7Ih+ip+mcrbNSg6xOEgFYeFM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YFU/h6r/; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YFU/h6r/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728575723; x=1760111723; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=BMNK5iWgnrtok45sdEr4evWdiRWQlKExtRudo8k9bE4=; b=YFU/h6r/R/cO/Wlq++p5lofmHvnXCP9tX4IDEktkkW+RpDcrvLlMiUdp VK/Uk8ZTIroeJDABZ/lBJfsEAW4FD/iB9WL/izQVEdcvAD5mXgQz0AV4l ybvfj80LTILdGgs7/JvAicpMGtQP6ZPkv3FQpCqeWmbK9CogNNY998oYE nkJsyOr82b0fBQRJmeYrP6zH+n0WG0u9dTYxJS1cZ8d3S1PxAOaeAQq6m VxPsTdn5m9yfeeXTIi9r5xSMhz/bjxEJ0wXKfaTRolKgPmQl1x0YDE22g +zBwbJsIocOcz00ezZ25pYhK4s3dOF6SYPCFWAD/+G8fpHcliZNNVz6oI w==; X-CSE-ConnectionGUID: y0wmHGQ8TBG5DSIS3QMyvw== X-CSE-MsgGUID: tvt/UzDrQ1CzSJRP16Vh3Q== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="31643871" X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="31643871" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:55:23 -0700 X-CSE-ConnectionGUID: NqibyQLaTPywmMm5dsawOg== X-CSE-MsgGUID: B25iujqmRiy1uqt4FB5BCg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="81222178" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:54:54 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH 02/10] x86/mce/intel: Use MCG_BANKCNT_MASK instead of 0xff Date: Thu, 10 Oct 2024 23:31:54 +0800 Message-Id: <20241010153202.30876-3-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241010153202.30876-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Use the predefined MCG_BANKCNT_MASK macro instead of the hardcoded 0xff to mask the bank number bits. No functional changes intended. Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index f6103e6bf69a..b3cd2c61b11d 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -94,7 +94,7 @@ static int cmci_supported(int *banks) if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) return 0; rdmsrl(MSR_IA32_MCG_CAP, cap); - *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff); + *banks = min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK); return !!(cap & MCG_CMCI_P); } From patchwork Thu Oct 10 15:31:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiuxu Zhuo X-Patchwork-Id: 13830486 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23BEE1CCEDD; Thu, 10 Oct 2024 15:55:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575729; cv=none; b=JLlhSuloxSY+Ps9B2QdD7wMYoMeEvt+tLpWwdA+TeHWXAHF3tajHxXzE/4Zm543KJ2SgMFHwwXoP4GARK0AoeajD9fH60W3mOIY4PHP5X6+z2nqSYx6LH7YwqHgawHADirl5DXzIjT/0bnmLiNtPQsTibsbmc/zexGGUkxDT/nE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575729; c=relaxed/simple; bh=CvZXfLJAf7BGy5eQuHrDIWH61gpASHNC05/Rr3RlMRk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=PcMHeVBK9zGHhO7mCnRNJsLD4EgY1HbvAHi8AWUhla3nxTFr61QdxthlMT/NFRfNclr5SwalIQmP8OOJC419TX0fdG4T/HxEHq2Y/hLXhNpcXY9fBkS99nv5yGHtBQZyyi4g38SkB9ZWKW8oPxrc/aJrnCtVPWq7RjLCDCo08qY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=neK71bl1; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="neK71bl1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728575729; x=1760111729; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=CvZXfLJAf7BGy5eQuHrDIWH61gpASHNC05/Rr3RlMRk=; b=neK71bl1Y5vcT2qInHiVRbjDKCC/AqXqLIbV38wo77OowWMnB1Hmih94 eZJc2p2GW6+8FDxBZLnFDTJMUPXLI6kN6btnrRi9a34QvJaA3f3X2ZcLe 0Xh1cp3gJWtIkhbvj8Bgm+jq1nl2qBrN87005zlNxMNlYtMSmqXw/UCg1 hybI+8X/URUYjB9+/XCX3wEgUcYIS3n7VJo88QhBVO0tQ90JgjNsHaNwU rUHhcJyPjfTfKoK11FgdmmvsB1NCi/nFmakKpU3kELJYkTO3NY1MLq1ng YVNAgkYnRPZGiG+ExF16Y1SgTSHI2SmICsuHkriNGhZzCzdG3qChT+C9r Q==; X-CSE-ConnectionGUID: Ic92tegmTsqp+jpt7iRDWA== X-CSE-MsgGUID: 8h6STSTkTxWBJzUB/U848A== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="31643880" X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="31643880" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:55:29 -0700 X-CSE-ConnectionGUID: +hxkOhdLQpqbxdA099oIBw== X-CSE-MsgGUID: 65XL/DhaTzmPmLXuWPwjyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="81222259" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:55:17 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH 03/10] x86/mce: Make several functions return bool Date: Thu, 10 Oct 2024 23:31:55 +0800 Message-Id: <20241010153202.30876-4-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241010153202.30876-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Make several functions that return 0 or 1 return a boolean value for better readability. No functional changes are intended. Signed-off-by: Qiuxu Zhuo --- arch/x86/include/asm/mce.h | 4 ++-- arch/x86/kernel/cpu/mce/amd.c | 10 +++++----- arch/x86/kernel/cpu/mce/core.c | 22 +++++++++++----------- arch/x86/kernel/cpu/mce/intel.c | 9 +++++---- 4 files changed, 23 insertions(+), 22 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 3b9970117a0f..7a01bb5b19d3 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -244,7 +244,7 @@ static inline void cmci_rediscover(void) {} static inline void cmci_recheck(void) {} #endif -int mce_available(struct cpuinfo_x86 *c); +bool mce_available(struct cpuinfo_x86 *c); bool mce_is_memory_error(struct mce *m); bool mce_is_correctable(struct mce *m); bool mce_usable_address(struct mce *m); @@ -264,7 +264,7 @@ enum mcp_flags { void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); -int mce_notify_irq(void); +bool mce_notify_irq(void); DECLARE_PER_CPU(struct mce, injectm); diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 14bf8c232e45..4dae9841ee38 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -381,7 +381,7 @@ static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) return msr_high_bits & BIT(28); } -static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) +static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) { int msr = (hi & MASK_LVTOFF_HI) >> 20; @@ -389,7 +389,7 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, b->bank, b->block, b->address, hi, lo); - return 0; + return false; } if (apic != msr) { @@ -399,15 +399,15 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) * was set is reserved. Return early here: */ if (mce_flags.smca) - return 0; + return false; pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, apic, b->bank, b->block, b->address, hi, lo); - return 0; + return false; } - return 1; + return true; }; /* Reprogram MCx_MISC MSR behind this threshold bank. */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 2a938f429c4d..725c1d6fb1e5 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -479,10 +479,10 @@ static noinstr void mce_gather_info(struct mce *m, struct pt_regs *regs) } } -int mce_available(struct cpuinfo_x86 *c) +bool mce_available(struct cpuinfo_x86 *c) { if (mca_cfg.disabled) - return 0; + return false; return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); } @@ -1748,7 +1748,7 @@ static void mce_timer_delete_all(void) * Can be called from interrupt context, but not from machine check/NMI * context. */ -int mce_notify_irq(void) +bool mce_notify_irq(void) { /* Not more than two messages every minute */ static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); @@ -1759,9 +1759,9 @@ int mce_notify_irq(void) if (__ratelimit(&ratelimit)) pr_info(HW_ERR "Machine check events logged\n"); - return 1; + return true; } - return 0; + return false; } EXPORT_SYMBOL_GPL(mce_notify_irq); @@ -1985,25 +1985,25 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) return 0; } -static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) +static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) { if (c->x86 != 5) - return 0; + return false; switch (c->x86_vendor) { case X86_VENDOR_INTEL: intel_p5_mcheck_init(c); mce_flags.p5 = 1; - return 1; + return true; case X86_VENDOR_CENTAUR: winchip_mcheck_init(c); mce_flags.winchip = 1; - return 1; + return true; default: - return 0; + return false; } - return 0; + return false; } /* diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index b3cd2c61b11d..f863df0ff42c 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -75,12 +75,12 @@ static u16 cmci_threshold[MAX_NR_BANKS]; */ #define CMCI_STORM_THRESHOLD 32749 -static int cmci_supported(int *banks) +static bool cmci_supported(int *banks) { u64 cap; if (mca_cfg.cmci_disabled || mca_cfg.ignore_ce) - return 0; + return false; /* * Vendor check is not strictly needed, but the initial @@ -89,10 +89,11 @@ static int cmci_supported(int *banks) */ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) - return 0; + return false; if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) - return 0; + return false; + rdmsrl(MSR_IA32_MCG_CAP, cap); *banks = min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK); return !!(cap & MCG_CMCI_P); From patchwork Thu Oct 10 15:31:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiuxu Zhuo X-Patchwork-Id: 13830487 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F2B51CDA3C; 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a="31643892" X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="31643892" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:55:33 -0700 X-CSE-ConnectionGUID: Jv5HjXJQQhWF/3nfbbrS5g== X-CSE-MsgGUID: eyumMmWaTfymXh2k4oWDtA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="81222337" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:55:29 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH 04/10] x86/mce/threshold: Remove the redundant this_cpu_dec_return() Date: Thu, 10 Oct 2024 23:31:56 +0800 Message-Id: <20241010153202.30876-5-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241010153202.30876-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The 'storm' variable points to this_cpu_ptr(&storm_desc). Access the 'stormy_bank_count' field through the 'storm' to avoid calling this_cpu_*() on the same per-CPU variable twice. This minor optimization reduces the text size by 16 bytes. $ size threshold.o.* text data bss dec hex filename 1395 1664 0 3059 bf3 threshold.o.old 1379 1664 0 3043 be3 threshold.o.new No functional changes intended. Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/threshold.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/threshold.c b/arch/x86/kernel/cpu/mce/threshold.c index 89e31e1e5c9c..f4a007616468 100644 --- a/arch/x86/kernel/cpu/mce/threshold.c +++ b/arch/x86/kernel/cpu/mce/threshold.c @@ -90,7 +90,7 @@ void cmci_storm_end(unsigned int bank) storm->banks[bank].in_storm_mode = false; /* If no banks left in storm mode, stop polling. */ - if (!this_cpu_dec_return(storm_desc.stormy_bank_count)) + if (!--storm->stormy_bank_count) mce_timer_kick(false); } From patchwork Thu Oct 10 15:31:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiuxu Zhuo X-Patchwork-Id: 13830488 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 628CB77F1B; Thu, 10 Oct 2024 15:55:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575745; cv=none; b=VpX3lJmpRpUEZSdqDSzUGG2JkFt1s7b7LYng/ToivPuATrJUij2NVc+qX08lbL4HsJ9niwLmFkC+C4ecCxYeZAKRx1wPicenezaLaw0aGkb2wP9w1I9cAhv4l8wqJ+RRFUPYggTaIm2HfeapAGj/aomy6flDWNRakpBhwMO7Zdk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575745; c=relaxed/simple; bh=Pp2wyt/ptr6Ycpfb65KUc+cKW7kGR88mHN8sOECc6TA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=MSiQ+t+a36PHOBAOPXCT4knjhEaoHqvK/ZC57WGOBCUqnFp3PIxCODIdL+avS05+z3gJ6SB5NdtMGVdeT+9TbPYLZDSiuUgfGIs+9bNddxHiOB24LasdOL/4qwE0q2oC9Qs8Dfmofz0Ugcer41yzdjcaIrqMRIteiVM/PoopzHw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LApmEdBN; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LApmEdBN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728575745; x=1760111745; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Pp2wyt/ptr6Ycpfb65KUc+cKW7kGR88mHN8sOECc6TA=; b=LApmEdBN6VE8O24AqBpp8u5US5b7c0bxfy3zEj6m2cscawZfuHJ6oo0V 5QqEVDY8M0wDMk1WxVp2bYw22f5b8DG6cWEcovLhJA5A20DFOsu0g5FNi jeRn+An6i8oTscPO7ptzUKWTEYwsqqmiN1bRelWm+hhHQ2nGiX5uSWqMo C+99cpKZy96JwP7PH0R9lW3gr7W2f71hP3vJSt/2kD5F5cYm4OwQKz+QW bNn9EzSCufUEW7MRUMl0e9XDPkrAEAXmCYYLTVv9RtxSGCo7qB4AtwjHT Mcl9O8V6fYcr8fogivLthA5JkrQCSbRZVoYVj0rPLqTFIVJS1PU8afqKU w==; X-CSE-ConnectionGUID: cvCCBa/+TxCv+njKgoc7xw== X-CSE-MsgGUID: s4IdR0DWQmec+OTAE4taNA== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="31643903" X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="31643903" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:55:44 -0700 X-CSE-ConnectionGUID: FbdVvS/VRLqcxNJECJ3OtQ== X-CSE-MsgGUID: JNwyS6ScRlmJLlZicBkzgQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="81222472" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:55:41 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH 05/10] x86/mce/genpool: Make mce_gen_pool_create() return explicit error codes Date: Thu, 10 Oct 2024 23:31:57 +0800 Message-Id: <20241010153202.30876-6-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241010153202.30876-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Make mce_gen_pool_create() return explicit error codes for better readability. No functional changes intended. Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/genpool.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/genpool.c b/arch/x86/kernel/cpu/mce/genpool.c index 4284749ec803..ffa28769dea6 100644 --- a/arch/x86/kernel/cpu/mce/genpool.c +++ b/arch/x86/kernel/cpu/mce/genpool.c @@ -120,20 +120,20 @@ static int mce_gen_pool_create(void) { int mce_numrecords, mce_poolsz, order; struct gen_pool *gpool; - int ret = -ENOMEM; void *mce_pool; + int ret; order = order_base_2(sizeof(struct mce_evt_llist)); gpool = gen_pool_create(order, -1); if (!gpool) - return ret; + return -ENOMEM; mce_numrecords = max(MCE_MIN_ENTRIES, num_possible_cpus() * MCE_PER_CPU); mce_poolsz = mce_numrecords * (1 << order); mce_pool = kmalloc(mce_poolsz, GFP_KERNEL); if (!mce_pool) { gen_pool_destroy(gpool); - return ret; + return -ENOMEM; } ret = gen_pool_add(gpool, (unsigned long)mce_pool, mce_poolsz, -1); if (ret) { @@ -144,7 +144,7 @@ static int mce_gen_pool_create(void) mce_evt_pool = gpool; - return ret; + return 0; } int mce_gen_pool_init(void) From patchwork Thu Oct 10 15:31:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiuxu Zhuo X-Patchwork-Id: 13830489 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17B2A77F1B; Thu, 10 Oct 2024 15:55:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575754; cv=none; b=r54RTNoO2fWZyNEYiMxNe02Ofz2qxmKj+JSbmJwuuF6TGXV2o+CpxA7M5csuHh8viPutczFIfp/6Ig2Mgzg82iOrkCqr5i+cxi+06MTQG+JcB2U6moeympXazSzQppJdscFU1gKs4gQzLfQlwQXfm51vx16dkpR1kAWbl8KF7+k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575754; c=relaxed/simple; bh=W62PbZYRv8kc3IiXZFBqVqA0JdM2rYr+xbg62nvROiE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=ZJWJTFmJZkV1Cfm5vPYCT2BirQQw4GQZxq/njYZyj8qJem+epTblpmLPtuKUrEV83xKUUtGZXxkeZPLZTZnOgn5MswwfhF+ExVwJ8fqS993CmLMm4QtLHNKTjwAvY8u6Ww4MJCFdVMtS5oH3gWISP5aqd+0IKeMcEnwzltt7M3k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=J2LBTCow; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="J2LBTCow" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728575754; x=1760111754; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=W62PbZYRv8kc3IiXZFBqVqA0JdM2rYr+xbg62nvROiE=; b=J2LBTCowS6Ws9U2NNfcJa+pmY0EpvdiEybIfLiA6zR79IjzFfb+QbKNg 3kwWUPRt5DoAOkItOsmtKRbSf/eaXdREtncyrm1x0peDDioznW5U9i8GY oQ++oQcJGxcVrzsH96hyUFIT00JOEWhMRLfnGX4qUNnL1AkO4I2B8C43R 6wocxMyFkgQ3xVE5HJvjZdlMI6wl4MdEkraxVFz2n6AUqYUpxYt/PzBkp jd2VYdRPl/X6XIx/ofyJosV4VDOIdQBkZO5+ZRasGXX1MLZ1baBoDtbn+ /kiLA2zg7i5rnDO4v/yGk91SpoSYuGBEwoICxIX0fsqgzS/S3XBw642FU Q==; X-CSE-ConnectionGUID: r46lKNp/Qh6ymvHngmMl4A== X-CSE-MsgGUID: Eqwn3XF2Shub44hH8qGN7w== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="31643959" X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="31643959" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:55:53 -0700 X-CSE-ConnectionGUID: XyG7ypn2S4icAU14QHtyeg== X-CSE-MsgGUID: zMsrbkgSR4+G4llZ1A/YgA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="81222580" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:55:50 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH 06/10] x86/mce: Convert multiple if () statements into a switch() statement Date: Thu, 10 Oct 2024 23:31:58 +0800 Message-Id: <20241010153202.30876-7-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241010153202.30876-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Convert the multiple if() statements used for vendor differentiation into a switch() statement for better readability. As a bonus, the size of new generated text is reduced by 16 bytes. $ size core.o.* text data bss dec hex filename 21364 4181 3776 29321 7289 core.o.old 21348 4181 3776 29305 7279 core.o.new No functional changes intended. Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/core.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 725c1d6fb1e5..40672fe0991a 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1892,7 +1892,8 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) } /* This should be disabled by the BIOS, but isn't always */ - if (c->x86_vendor == X86_VENDOR_AMD) { + switch (c->x86_vendor) { + case X86_VENDOR_AMD: if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { /* * disable GART TBL walk error reporting, which @@ -1925,9 +1926,9 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) if (c->x86 >= 0x17 && c->x86 <= 0x1A) mce_flags.zen_ifu_quirk = 1; - } + break; - if (c->x86_vendor == X86_VENDOR_INTEL) { + case X86_VENDOR_INTEL: /* * SDM documents that on family 6 bank 0 should not be written * because it aliases to another special BIOS controlled @@ -1964,9 +1965,10 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) */ if (c->x86_vfm == INTEL_SKYLAKE_X) mce_flags.skx_repmov_quirk = 1; - } - if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { + break; + + case X86_VENDOR_ZHAOXIN: /* * All newer Zhaoxin CPUs support MCE broadcasting. Enable * synchronization with a one second timeout. @@ -1975,6 +1977,8 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) if (cfg->monarch_timeout < 0) cfg->monarch_timeout = USEC_PER_SEC; } + + break; } if (cfg->monarch_timeout < 0) From patchwork Thu Oct 10 15:31:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiuxu Zhuo X-Patchwork-Id: 13830490 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 174911CEE97; Thu, 10 Oct 2024 15:56:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575765; cv=none; b=Ipu2BjGBOkJiSkjv0BFT+k9Raozfp7+aF7lfIbLE9aPldvzCKIRg/vqmixbwi9AirpuklUi0SWKn2XvwNkKQccZSvSfxTIaCnRUxRHEMOlRD8vr5qbvrqdikLy7zHs3bvukG+UVwJdn2t+pwHLpUgWF9EXBMQ0+N5lykJTVb5MY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575765; c=relaxed/simple; bh=WjIJysxc0a7IXs7+dCgPg2xAxrCZA2nBFfYdAYMs99k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=ZANBxpncgC9xAE9PIxvlTQ4puYjCk+wzoOUtODTr6WDTUojEPixv1I+hsp4tLo/aZKDDfnC4/Ps0aw1bvR2keXHVNjvhlLpwzq85aEHOXyQI23CwGchx8F//WDfiSteOC6j3XSWxIUqD0wlSlrCmV3p6oOFS5M5mLgrh5Jm2bfw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RhrZDpeZ; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RhrZDpeZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728575764; x=1760111764; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=WjIJysxc0a7IXs7+dCgPg2xAxrCZA2nBFfYdAYMs99k=; b=RhrZDpeZ4p6Zl6wImI7fToQSiKJKYZpBwNEE4QNGCx2uhmk0caXyTZ5c a8TLmMSKj3noN586Ok1m7MPvI1UET7hzzOginZ6balswGx8nXYQr8NO7c ChRCNqO9Fi0zLnJm+6SwyrJMUUuuCkrbXPJZFs1a+F7BTw2I7oZ/rqQi3 YLHJRPjdTfDkn6OfHrJf3W+FCCVqUz83WgAdEz+/AU1q2yzoASc17pVXh z09cPR717MVqnvxuz38XWZYjfFNrhhTfTYHaDW2rwwFoQ+D+hseill261 Ff5g+HI2CYKCn6r+Gh/W/K76Hp360v3SyygTid71cqdU125repzIuv85i A==; X-CSE-ConnectionGUID: Mg1OON4ORXaJV5C5pzCHcA== X-CSE-MsgGUID: AxJ+ueBzQ7aSfLiQxMMGuQ== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="45423225" X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="45423225" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:56:04 -0700 X-CSE-ConnectionGUID: 3dzK/nIHT7i0ZJScdxjaSQ== X-CSE-MsgGUID: f1oiLAG4T5qfcKXIy4uueA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="81222665" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:56:01 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH 07/10] x86/mce: Remove the unnecessary {} Date: Thu, 10 Oct 2024 23:31:59 +0800 Message-Id: <20241010153202.30876-8-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241010153202.30876-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Remove the unnecessary {} from the case statement. Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 40672fe0991a..e718b9bbe8e5 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -2073,10 +2073,9 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) mce_intel_feature_init(c); break; - case X86_VENDOR_AMD: { + case X86_VENDOR_AMD: mce_amd_feature_init(c); break; - } case X86_VENDOR_HYGON: mce_hygon_feature_init(c); From patchwork Thu Oct 10 15:32:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiuxu Zhuo X-Patchwork-Id: 13830491 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 040261CDFA4; Thu, 10 Oct 2024 15:56:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575774; cv=none; b=G10cOudoMT8fqUb9iDymaYJeOdjYP4B9WCw7lDWT5chkMIeJ6ydBPZ6gR6LB22z+0uF3GQWxFtvBtidZTxZRT6pGucywcIQh17Dbe176J2EiBTktrbja1zxdHrz1qSJFJRYmtWHLsrx0H6tbUCTW+ipLfI1o2tWQ86Lj4dNkTyM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575774; c=relaxed/simple; bh=DS90dg2NbbEoGW7kXq2baDYlEThrWrVLN673//15/1Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=lKl5xz7B//bQCkgytwkuzz84oiFFLrgFWNcNR3Vpug+qpuKdR9EIotF4JvP4ICjEmg1VhpSZQwfLuqYSKmQq87WtNFw1Gc+WtZs3FhK8W5jUYHwpnp/n6GsB7F36iBbYyQxyM61VuDzKiLv1mnpsMKfmTmSBnp5C7avl4hNrsUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cgzygADS; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cgzygADS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728575770; x=1760111770; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=DS90dg2NbbEoGW7kXq2baDYlEThrWrVLN673//15/1Y=; b=cgzygADSEUE9uFfsIex1iO2gUflhXIjVx1lXTlHKMt+WjSl4PbHyzDYP pTCJCnEnKeDQwHTjbTv1tS54ds61ewvPp08Dc21kEWjO3BW4Xv0AvjE2c T92RtA1hog537IX/WMA8bAbOMmLEIml/LD8VtVvUPn0wCwvicVXoGGfPm fbibtHpgAmiGd1un7HVWMY+Rd77KZ5DmGVIUYczsnjOgEwgcrXmzquvFe IkrBsDKqpc34u6moebfLDj/7Ve5t90L3kGNRQyS5OesJzBFNtGk0ppbwm V9QcYCMzEol3Vl1l+UXXODy/cYiX5EuuTAnCxYliXY4zZgxD6aZxwsvig A==; X-CSE-ConnectionGUID: pUuu0t/BQtOSzSOIQ8EYhg== X-CSE-MsgGUID: c5dpKi4/QsyhSjg+wBhNKQ== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="45423261" X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="45423261" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:56:10 -0700 X-CSE-ConnectionGUID: k0kd+4lPRqeD1wLYe5TELg== X-CSE-MsgGUID: SNn/hWwUQy6xP2cmzV+hPQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="81222754" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:56:07 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH 08/10] x86/mce: Remove the redundant zeroing assignments Date: Thu, 10 Oct 2024 23:32:00 +0800 Message-Id: <20241010153202.30876-9-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241010153202.30876-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: As the entire mce structure is initialized to zero using memset(0) within mce_gather_info(), remove the redundant zeroing assignments to mce->misc and mce->addr. This results in a reduction of 64 bytes in the text size. $ size core.o.* text data bss dec hex filename 21348 4181 3776 29305 7279 core.o.old 21284 4181 3776 29241 7239 core.o.new Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/core.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index e718b9bbe8e5..844a6f8d6f39 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -706,8 +706,6 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) if (!mce_banks[i].ctl || !test_bit(i, *b)) continue; - m.misc = 0; - m.addr = 0; m.bank = i; barrier(); @@ -1284,8 +1282,6 @@ __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final, if (!mce_banks[i].ctl) continue; - m->misc = 0; - m->addr = 0; m->bank = i; m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); From patchwork Thu Oct 10 15:32:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiuxu Zhuo X-Patchwork-Id: 13830492 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40B901CDFA4; Thu, 10 Oct 2024 15:56:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575780; cv=none; b=TIR9Va2gDECv/7L45O3fp6HEXLta6+DLiM4LVuNKvPVSNSS3AGLy6kxidvRHH6zliE6lQq3FcFCHWeUKnqQ7Itk0d3ckmzdORibRdqaOVGByNXmbxqsWoMkFmNSVA2Buyou66xyTf/5tTgPjT+0SQdMZKb/6thmh/h6U6LPqa3o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728575780; c=relaxed/simple; bh=7+X6jaeieNzTyu8ssogMovOtcKGNTvrNvXl2BzPVSqs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=kh7GP7zhSIeA9W2AhPf78k+eohKE5sPpWiW/hc/RIRcOA5HO9T1iNhejjSDB3Nc4dlcJWBUvty+ybecv0PZGhk1XEDJ9AeLnnIr1VsSbrcsaVEdzUX0eaQi36IIPp6w8UTIx1hiCl/va1Ck0WWneQjzbQ4kyWdf9yOZAFM9qHt0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FwjrL2vP; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FwjrL2vP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728575779; x=1760111779; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=7+X6jaeieNzTyu8ssogMovOtcKGNTvrNvXl2BzPVSqs=; b=FwjrL2vPCqvsIu9RWz3ddv0Gwe1SLOs7ezjVPApvi+2djnT9p7Hdq7eX uoUncKTdEC7U8369A304CRYe/a/AkydtdRvf76f/jrIFDYMdzIdwfpeYv 3eIYU1G43i8ebBO6ZGBM6JEdnzy9k5sTjLZEgUo080g8c67HJmyFs1r+e UhPWYaIvF8H4HDwJoNND5ehbiXI9bcrkfcwkZOPsMWr0L+t5JNwRt6FlV CrBDhmb5/CuoSNFWYOH9zW3uQaQLNB8DHC3TO2R8RofZTDCGlBiR+/WCJ D302m7DoNhtpUW5BuPGB3U1m9ooCE5JWWKh5OZgP5O0AjadyWnXUDpIKo A==; X-CSE-ConnectionGUID: UdDcMylnR6OdT2H9Hkpi/w== X-CSE-MsgGUID: bPbiJd95Q5m5DF3rMknvBQ== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="45423288" X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="45423288" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:56:19 -0700 X-CSE-ConnectionGUID: kNmUVqeyTga0uGYteAwvtw== X-CSE-MsgGUID: 9xnY+BeNRmKpwfsOH9h9Vw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="81222842" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:56:16 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH 09/10] x86/mce/amd: Remove unnecessary NULL pointer initializations Date: Thu, 10 Oct 2024 23:32:01 +0800 Message-Id: <20241010153202.30876-10-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241010153202.30876-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: As 'pos' and 'tmp' are initialized prior to their use in list_for_each_entry_safe(), remove the unnecessary NULL pointer initializations. Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/amd.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 4dae9841ee38..aecea842dac2 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -917,8 +917,8 @@ static void log_and_reset_block(struct threshold_block *block) */ static void amd_threshold_interrupt(void) { - struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; struct threshold_bank **bp = this_cpu_read(threshold_banks); + struct threshold_block *first_block, *block, *tmp; unsigned int bank, cpu = smp_processor_id(); /* @@ -1197,8 +1197,7 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb static int __threshold_add_blocks(struct threshold_bank *b) { struct list_head *head = &b->blocks->miscj; - struct threshold_block *pos = NULL; - struct threshold_block *tmp = NULL; + struct threshold_block *pos, *tmp; int err = 0; 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10 Oct 2024 08:56:28 -0700 X-CSE-ConnectionGUID: 3wczDe8CRMWPkkN578YmDQ== X-CSE-MsgGUID: ux5466TKS3q0sDXKScWsZA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,193,1725346800"; d="scan'208";a="81222905" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2024 08:56:26 -0700 From: Qiuxu Zhuo To: tony.luck@intel.com, bp@alien8.de Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH 10/10] x86/mce: Fix typos in comments Date: Thu, 10 Oct 2024 23:32:02 +0800 Message-Id: <20241010153202.30876-11-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241010153202.30876-1-qiuxu.zhuo@intel.com> References: <20241010153202.30876-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Fix the following typos in comments: s/callin/calling/ s/TBL/TLB/ Signed-off-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 844a6f8d6f39..19e6730e7c22 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1118,7 +1118,7 @@ static noinstr int mce_start(int *no_way_out) } else { /* * Subject: Now start the scanning loop one by one in - * the original callin order. + * the original calling order. * This way when there are any shared banks it will be * only seen by one CPU before cleared, avoiding duplicates. */ @@ -1892,7 +1892,7 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) case X86_VENDOR_AMD: if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { /* - * disable GART TBL walk error reporting, which + * disable GART TLB walk error reporting, which * trips off incorrectly with the IOMMU & 3ware * & Cerberus: */