From patchwork Thu Oct 10 19:03:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13830889 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BE90CFC5F7 for ; Thu, 10 Oct 2024 19:05:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1syyRz-00060B-Hf; Thu, 10 Oct 2024 15:03:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1syyRx-0005zu-Ts for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:03:49 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1syyRw-0004iA-92 for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:03:49 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-71dfccba177so1968351b3a.0 for ; Thu, 10 Oct 2024 12:03:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1728587026; x=1729191826; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kYV54R/BWSeQo+PImwTWN+iYLjqQw2lOGsyCKuolLjM=; b=ZwieFGyBcHpShKoQUhpViIWdC0qkpDiNOT5ha4swRTBhWUbus3XCpIoX/DEX1UF5zR BeNkf2CrBLgPTPeRprm+yw3TqYu2gnbokdDbMW9WRQHXSJWtSGKHqOP5hbWBn6hAnIGB 8Xxx8JUs/yQuaxOAoakKzBWtjllLdVq96SKU+AqXbS7LnvRV6hysmqtdLghrBbYcQZe2 XpR2nA01JVtl+qNnM63FDJMemgAsB95sBHlMGjD111iPWmHMNeRgKM63oVCfhWhGEPIF ZGocB75rIaTzGNbtwT4cFhtWgh64bEJwCiv4Df2G8TT5a1wx/lhRIQL4cjcr+ozUmtIb DiUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728587026; x=1729191826; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kYV54R/BWSeQo+PImwTWN+iYLjqQw2lOGsyCKuolLjM=; b=uoa9vvlQh0nk45PceJ5o6RJ9wRtL16Kcd91Qon45YyFAQGzhkTbypGJUZYfwHI/8EX HnyHXPKuUUO399rWyeizhTjpeqzsCxrrd9zFMzK6tqFfhdgNYBphDFjFHghewYRNpWD/ +Ol81Na2Bo6B8YLSuBInhIxE7CxRl8PcYeni4aJMVI5HoAxm5GqniHRiNgBniBxCyAkI n2u8ujJZ0kXejjdU+ta2UKQCD9x9+TxL7keeR0fabirJHvcGpKz+CmIHkOsOek6iTD8+ 0Xda4pwiSWzj5patf4N+sqpk0CTwySginkl42aCxO4rHbxihghMZ+PRb63RpEy8ylbnH cPgQ== X-Gm-Message-State: AOJu0YzXYhQZXu0iv2PSP8i7Dckzk3I67R2//OvEKqRCwjYOamZwh+6e ESpy9uoX5t/eG4yqlBJDZZUkLtDa2MM8A+YEnGEyArEHeccfWv+BBNpmaljvXvzduJcv2HdO+B3 9 X-Google-Smtp-Source: AGHT+IFe7kEQ6lQo3H3809DUzKA3DTiH1uv/PA+/BII/GunzoKdUuLo8qg210ZqyIQ2RjL/j0mNHSw== X-Received: by 2002:a05:6a21:1796:b0:1d2:fad2:a537 with SMTP id adf61e73a8af0-1d8bc95b4b0mr202164637.18.1728587026341; Thu, 10 Oct 2024 12:03:46 -0700 (PDT) Received: from grind.. (201-68-240-198.dsl.telesp.net.br. [201.68.240.198]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e2a9f5263sm1354532b3a.62.2024.10.10.12.03.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 12:03:46 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH 1/8] hw/intc/riscv_aplic: rename is_kvm_aia() Date: Thu, 10 Oct 2024 16:03:30 -0300 Message-ID: <20241010190337.376987-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241010190337.376987-1-dbarboza@ventanamicro.com> References: <20241010190337.376987-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The helper is_kvm_aia() is checking not only for AIA, but for aplic-imsic (i.e. "aia=aplic-imsic" in 'virt' RISC-V machine) with an in-kernel chip present. Rename it to be a bit clear what the helper is doing since we'll add more AIA helpers in the next patches. Make the helper public because the 'virt' machine will use it as well. Signed-off-by: Daniel Henrique Barboza --- hw/intc/riscv_aplic.c | 8 ++++---- include/hw/intc/riscv_aplic.h | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 4a262c82f0..20de8c63a2 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -154,7 +154,7 @@ * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want to use * APLIC Wired. */ -static bool is_kvm_aia(bool msimode) +bool riscv_is_kvm_aia_aplic_imsic(bool msimode) { return kvm_irqchip_in_kernel() && msimode; } @@ -853,7 +853,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp) uint32_t i; RISCVAPLICState *aplic = RISCV_APLIC(dev); - if (!is_kvm_aia(aplic->msimode)) { + if (!riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) { aplic->bitfield_words = (aplic->num_irqs + 31) >> 5; aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs); aplic->state = g_new0(uint32_t, aplic->num_irqs); @@ -877,7 +877,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp) * have IRQ lines delegated by their parent APLIC. */ if (!aplic->parent) { - if (kvm_enabled() && is_kvm_aia(aplic->msimode)) { + if (kvm_enabled() && riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) { qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs); } else { qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); @@ -1021,7 +1021,7 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - if (!is_kvm_aia(msimode)) { + if (!riscv_is_kvm_aia_aplic_imsic(msimode)) { sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); } diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h index de8532fbc3..fd0e6427d9 100644 --- a/include/hw/intc/riscv_aplic.h +++ b/include/hw/intc/riscv_aplic.h @@ -71,6 +71,7 @@ struct RISCVAPLICState { }; void riscv_aplic_add_child(DeviceState *parent, DeviceState *child); +bool riscv_is_kvm_aia_aplic_imsic(bool msimode); DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, From patchwork Thu Oct 10 19:03:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13830891 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20A6FCFC5F9 for ; Thu, 10 Oct 2024 19:05:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1syyS2-00061s-Q3; Thu, 10 Oct 2024 15:03:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1syyS0-00060t-Nv for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:03:52 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1syyRz-0004id-79 for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:03:52 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-71df04d3cd1so1137927b3a.2 for ; Thu, 10 Oct 2024 12:03:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1728587029; x=1729191829; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ufMG5AryEKYzOO3Km5eLPU0tnyg9cuTgKk08ESQiSrk=; b=dbcDyVhy51ognIYL1+mpRXFe54BAEni2A9776QGpItlXPnuCSxy7qvwxLZiW0nh7Ab 1I/23RlsgHIQTIwrMEyiiFXF6mJ4oWUNNpocIS/4BS17/YJZ4Arml7TaBAifkL8pbsCP D8kFYbkxTu4VXDTS93TKNho1atG8iS2akTygdbB6Vqb/3nQL0OC+1nOFd94Wo1Tq3ex+ T05TFzhEgSVRp7Hnm585lTfGaILbNPFJnhHO+eitOpxbAmQEKlF6ygqPb+8NxpFEqxJe RUaMZZTrVv56xWSZ612PWlT7qgVnM/Hv+p2F5FOxicCH6d9fMoY2v0FF4RWTJej3JXI2 wz2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728587029; x=1729191829; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ufMG5AryEKYzOO3Km5eLPU0tnyg9cuTgKk08ESQiSrk=; b=Q+yyKcM+kDdHfwdeEk4bJcC6WEr059iVqDAfbZWqWpfSxmlmpImpCHq8pFA0HP9wMN NAcgAgDwf360g5Cwssucblpb+BJ1fU9whz9pPU42JqCdBtL4sMmnEVzDNoxy+Dm7n9y9 SpwKwGWxbUwb+MffdAovoJhKwM7KdNmtrIaUIsp/6dLBTuz7NZoGQEow7MzbqG8m1MCQ Im35C1G823r435n0F7zolTtJEdam1d/vZAHVJfmFBMeakHX0+tOan79VGYFoX6WHtDIy 5tMCs6CKPbnuKfTNnTTtKmbJPZArHWd2Qt/Q+hNlgD0DjtPag2U6eN9GtbIMUyzE33sH IkBQ== X-Gm-Message-State: AOJu0Yxo0dYJbokKFjEhWJSqtcPBgz9c1WUf0MiOxl8zSeg20/ZOg+nd KM/aHKnRzJ9viQsnK6zYiE50AtM7uoSImBhVP5RiojYnfBApXLv+nLSGHFKvXm4neAU/KoGUAuu s X-Google-Smtp-Source: AGHT+IFhGyQ9W9YcSmlCXMp3KuCr7lrYcg387ctaAmgKstqQNyVIcHZR59AmI90Ta0RAGTsH3Qhbmw== X-Received: by 2002:a05:6a00:2da7:b0:71d:f0dc:ce94 with SMTP id d2e1a72fcca58-71e37f5e498mr75416b3a.20.1728587029407; Thu, 10 Oct 2024 12:03:49 -0700 (PDT) Received: from grind.. (201-68-240-198.dsl.telesp.net.br. [201.68.240.198]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e2a9f5263sm1354532b3a.62.2024.10.10.12.03.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 12:03:49 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH 2/8] hw/riscv/virt.c: reduce virt_use_kvm_aia() usage Date: Thu, 10 Oct 2024 16:03:31 -0300 Message-ID: <20241010190337.376987-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241010190337.376987-1-dbarboza@ventanamicro.com> References: <20241010190337.376987-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In create_fdt_sockets() we have the following pattern: if (kvm_enabled() && virt_use_kvm_aia(s)) { (... do stuff ...) } else { (... do other stuff ...) } if (kvm_enabled() && virt_use_kvm_aia(s)) { (... do more stuff ...) } else { (... do more other stuff) } Do everything in a single if/else clause to reduce the usage of virt_use_kvm_aia() helper and to make the code a bit less repetitive. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ee3129f3b3..b5bdbb34e0 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -780,6 +780,10 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, msi_m_phandle, msi_s_phandle, phandle, &intc_phandles[0], xplic_phandles, ms->smp.cpus); + + *irq_mmio_phandle = xplic_phandles[0]; + *irq_virtio_phandle = xplic_phandles[0]; + *irq_pcie_phandle = xplic_phandles[0]; } else { phandle_pos = ms->smp.cpus; for (socket = (socket_count - 1); socket >= 0; socket--) { @@ -797,13 +801,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, s->soc[socket].num_harts); } } - } - if (kvm_enabled() && virt_use_kvm_aia(s)) { - *irq_mmio_phandle = xplic_phandles[0]; - *irq_virtio_phandle = xplic_phandles[0]; - *irq_pcie_phandle = xplic_phandles[0]; - } else { for (socket = 0; socket < socket_count; socket++) { if (socket == 0) { *irq_mmio_phandle = xplic_phandles[socket]; From patchwork Thu Oct 10 19:03:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13830892 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 027C9CFC5FA for ; Thu, 10 Oct 2024 19:05:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1syyS6-00063W-RG; Thu, 10 Oct 2024 15:03:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1syyS4-00062o-V2 for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:03:56 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1syyS2-0004j2-7K for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:03:56 -0400 Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-7db1f13b14aso1071396a12.1 for ; Thu, 10 Oct 2024 12:03:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1728587032; x=1729191832; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GPrzIa4nG4f+V6JITUP+rCk9SaYCtpeZ5a6iOcrm8J4=; b=D7/K7meimqsm/J68pPk8g5p8mibRQE6vbwofzEZuNTpaJBemgy7PXHG0zqVnAJZGu3 +hCfixR/7yKfH0zCOYpNcmX7fFYIxIg8p/3jKP3akjFsNClj2mEOj8SGzC6iWtPpkkAc cjqPVXjK4FpOw/CjrttrB2EhLp6rv3CjtzZwac4CXE4xciX8R8Xq88tonQ+VzqxGy1YE 94nj5OWAA7MyhZaXpv0uuwJu2upFqsXgH8vlAaY6S16btCrpiHc5AH57ow2qT9u6P5i4 lLUFPkIBdqo5BhxnodABhZZzLRNm76+bhD2VXs6Xw8h2jyP+MvmO7s1NT83YY2N2dEg/ RLVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728587032; x=1729191832; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GPrzIa4nG4f+V6JITUP+rCk9SaYCtpeZ5a6iOcrm8J4=; b=dJjmra/gV2IT29rX3oqzC+Vv3FCQu7l7tdOW3XfI5iiYtv63GLer1Vvfn05dsE5DmP gZm5tJT1lA/aacX8lzF6WZr/dQNnv+Vi1flaZDSZRwOSOori1cnXV+MLYC68eZfikCkS sAbUo/kbXDyUuHKrR2YZAmZMm+UWC9wZAm2EwRSbyVrPNJT9lKzJNNQBqzuYJ+i5tpIk 0i+Xwrx5K7L4nCWw/w53AbEPhdzznGqyPY+F8qz7Id5URvmswSTJ35KYeSiZHuejE6Ls ZeEQF8dJoYMCB771sbHKtEF74ntyYVb/JMZ2rzVIGJ/zqxThQobp0LBzrOzSvR2SjJHx xILQ== X-Gm-Message-State: AOJu0Yz8rvVsR8/SJCF0cjI8uLc84XlRrR4DWMTkfn1nYYJbo2ruaSyQ VRhXqWIQ7ikaJlnt53nZ75J3oSXJoJRl3mp5L/W+pXwH+YRi1IqgPoQeffJ9iZaS2PxELAZRtnx F X-Google-Smtp-Source: AGHT+IFzONBhwFvPP2XjphuuwdTbYOp0vQX1CQzxBPTu/J+Pt4eK8dna3JP6075OmmzDVVTIOc9PhA== X-Received: by 2002:a05:6a20:e18a:b0:1d3:b30:44a2 with SMTP id adf61e73a8af0-1d8bcefa643mr28802637.7.1728587032575; Thu, 10 Oct 2024 12:03:52 -0700 (PDT) Received: from grind.. (201-68-240-198.dsl.telesp.net.br. [201.68.240.198]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e2a9f5263sm1354532b3a.62.2024.10.10.12.03.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 12:03:52 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH 3/8] hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic() Date: Thu, 10 Oct 2024 16:03:32 -0300 Message-ID: <20241010190337.376987-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241010190337.376987-1-dbarboza@ventanamicro.com> References: <20241010190337.376987-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Similar to the riscv_is_kvm_aia_aplic_imsic() helper from riscv_aplic.c, the existing virt_use_kvm_aia() is testing for KVM aia=aplic-imsic with in-kernel irqchip enabled. It is not checking for a generic AIA support. Rename the helper to virt_use_kvm_aia_aplic_imsic() to reflect what the helper is doing, and use the existing riscv_is_kvm_aia_aplic_imsic() to obscure details such as the presence of the in-kernel irqchip. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index b5bdbb34e0..f1bdc1c535 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -57,9 +57,11 @@ #include "hw/virtio/virtio-iommu.h" /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ -static bool virt_use_kvm_aia(RISCVVirtState *s) +static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type) { - return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; + bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; + + return riscv_is_kvm_aia_aplic_imsic(msimode); } static bool virt_aclint_allowed(void) @@ -774,8 +776,8 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, *msi_pcie_phandle = msi_s_phandle; } - /* KVM AIA only has one APLIC instance */ - if (kvm_enabled() && virt_use_kvm_aia(s)) { + /* KVM AIA aplic-imsic only has one APLIC instance */ + if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) { create_fdt_socket_aplic(s, memmap, 0, msi_m_phandle, msi_s_phandle, phandle, &intc_phandles[0], xplic_phandles, @@ -1540,7 +1542,7 @@ static void virt_machine_init(MachineState *machine) } } - if (kvm_enabled() && virt_use_kvm_aia(s)) { + if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) { kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, memmap[VIRT_APLIC_S].base, From patchwork Thu Oct 10 19:03:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13830893 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9B37CFC5F7 for ; Thu, 10 Oct 2024 19:05:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1syySC-00065Q-1o; Thu, 10 Oct 2024 15:04:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1syyS6-00063a-SO for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:03:58 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1syyS5-0004jO-9u for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:03:58 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-71df4620966so1205180b3a.0 for ; Thu, 10 Oct 2024 12:03:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1728587036; x=1729191836; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pHs6BVOnj+BBK5pRrpEWmqd66QRch8McjjRjElv9XFw=; b=jfg09fap2F2QRN1rbW3u8fHDeMwh2pfJuu8DYhuNbDB/ARVp7kCDy8sxXbq0W0gDjt q1Zux0r7dGgxUWjNZM+ZWbrpO46pLs9DSFWtdKwafsqKls+DS+3cDFUC6+a5NyUMe0Gz LESoya/DqzwXjrpYb9POcNeDy5pkiT0FxMdCi34Ve8XBRaP0nghbUyLIL9IHc7yyrh+R kmvletrDubCkTWLFTPYT6k8ezcgoWRthxpBWV/O7xIRjLQWx8vKo2fc6ZMMlfyZhO3hy 7d9DiNlQ8EvYKUgapv4hTKAs+NFv8CO4GosYA/B+q8ydEsU075ityKNlHVJB6fVb1MaD y+fA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728587036; x=1729191836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pHs6BVOnj+BBK5pRrpEWmqd66QRch8McjjRjElv9XFw=; b=KTwDDrFPl2+hIJKiGEJrlc9WfHpwa5cX6o/9GSkcxaCyLtTND9CtDItRBysKylX6vV eroN5MjBgU3d4QY/b5GRxNAJNSs5/l5f8O20wYtlXt/LzL03Q9VMdyW7djJhPS1HPKLq h4ZEI/LwnugBByfoMql3/KseYUijjVDVk47nA64QBbpZkvkVVxASmqyQY9EBOYuh/LtZ gJI6zz9e0/rQFJIWtkPxTXKGf+EKiMzvJNuXH3a0sOAZf3+or2YEhO0Rp7PEUrB9Zc5p 1I+1e4XOS7idAkPcHZD6NThcnnLdNWmRmZl5gQq1LPmUMJm7B21JPpbP8ys7O2MGag4P lk8A== X-Gm-Message-State: AOJu0YxiHAeOn/ggCi11+YjHyRyCuq3favz29xPxRa/N8HZIXrYE9hBu QZshxGzlfXig8tkjTxm65WSM+nemVF67g+c6tMQXZB4BaxYNe7E2gwqmuLocNhMr8OP2cXRvFue S X-Google-Smtp-Source: AGHT+IFe3jApTiLPDOcbhJA8fxJb0b29wQph7TvBOs0pZSODuWvlneFMpI4agag4hlOuKMWc3q0ZdQ== X-Received: by 2002:a05:6a21:790:b0:1d7:5a8:379d with SMTP id adf61e73a8af0-1d8bcf124cdmr20657637.15.1728587035810; Thu, 10 Oct 2024 12:03:55 -0700 (PDT) Received: from grind.. (201-68-240-198.dsl.telesp.net.br. [201.68.240.198]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e2a9f5263sm1354532b3a.62.2024.10.10.12.03.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 12:03:55 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH 4/8] target/riscv/kvm: consider irqchip_split() in aia_create() Date: Thu, 10 Oct 2024 16:03:33 -0300 Message-ID: <20241010190337.376987-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241010190337.376987-1-dbarboza@ventanamicro.com> References: <20241010190337.376987-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Before adding support to kernel-irqchip=split when using KVM AIA we need to change how we create the in-kernel AIA device. In the use case we have so far, i.e. in-kernel irqchip without split mode, both the s-mode APLIC and IMSIC controllers are provided by the irqchip. In irqchip_split() mode we'll emulate the s-mode APLIC controller, which will send MSIs to the in-kernel IMSIC controller. To do that we need to change kvm_riscv_aia_create() to not create the in-kernel s-mode APLIC controller. In the kernel source arch/riscv/kvm/aia_aplic.c, function kvm_riscv_aia_aplic_init(), we verify that the APLIC controller won't be instantiated by KVM if we do not set 'nr_sources', which is set via KVM_DEV_RISCV_AIA_CONFIG_SRCS. For QEMU this means that we should not set 'aia_irq_num' during kvm_riscv_aia_create() in irqchip_split() mode. In this same condition, skip KVM_DEV_RISCV_AIA_ADDR_APLIC as well since it is used to set the base address for the in-kernel APLIC controller. Signed-off-by: Daniel Henrique Barboza --- target/riscv/kvm/kvm-cpu.c | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 8233a32102..a92a46694a 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1725,12 +1725,28 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, kvm_aia_mode_str(aia_mode)); } - ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, - KVM_DEV_RISCV_AIA_CONFIG_SRCS, - &aia_irq_num, true, NULL); - if (ret < 0) { - error_report("KVM AIA: failed to set number of input irq lines"); - exit(1); + /* + * Skip APLIC creation in KVM if we're running split mode. + * This is done by leaving KVM_DEV_RISCV_AIA_CONFIG_SRCS + * unset. We can also skip KVM_DEV_RISCV_AIA_ADDR_APLIC + * since KVM won't be using it. + */ + if (!kvm_kernel_irqchip_split()) { + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_SRCS, + &aia_irq_num, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set number of input irq lines"); + exit(1); + } + + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, + KVM_DEV_RISCV_AIA_ADDR_APLIC, + &aplic_base, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set the base address of APLIC"); + exit(1); + } } ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, @@ -1772,14 +1788,6 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, exit(1); } - ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, - KVM_DEV_RISCV_AIA_ADDR_APLIC, - &aplic_base, true, NULL); - if (ret < 0) { - error_report("KVM AIA: failed to set the base address of APLIC"); - exit(1); - } - for (socket = 0; socket < socket_count; socket++) { socket_imsic_base = imsic_base + socket * (1U << group_shift); hart_count = riscv_socket_hart_count(machine, socket); From patchwork Thu Oct 10 19:03:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13830890 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6394CFC5F8 for ; Thu, 10 Oct 2024 19:05:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1syySF-00067y-0C; Thu, 10 Oct 2024 15:04:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1syySA-00065M-IQ for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:04:02 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1syyS8-0004jn-W0 for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:04:02 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-71dfe07489dso1088341b3a.3 for ; Thu, 10 Oct 2024 12:04:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1728587039; x=1729191839; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1oJigOA3pUwrJKDXI/ZEnIGISLXhzd47ZD58adw0TrQ=; b=Wi5XB0aOPgjCnVAecnFmakABOsdmgNgsWIlKdmO0awu211kcPWZPKxl0QKd7AtJrMK g2RvCmMmCKoNAx49dF7Y/wXNeFiysdIgJ4fed3Cv6rVcCygYDLlzWUTkRnvGNbLrtfAt yb2T2KKouZtATAQmbkT8m4IVskwHPJObIk6gugG5ZK098djKi+kTPHEdB31vbGKB/7q2 qQiosS5QC3LKiMGOo8ZqIqvwus2Bvsdq4CQ6pHHazKkekOVHhfJy7DjoXJP/0heAQFxi iZS7x3fsl1C90H7uBdJscTMhALKycfx+oDxo3AK7C9a+dVDAjRDJM9ot0V9gHrXkaGgP L9lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728587039; x=1729191839; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1oJigOA3pUwrJKDXI/ZEnIGISLXhzd47ZD58adw0TrQ=; b=Tfs/Z2eV9LmZE0Tzd5yn/0mS5CtoXmZlS6H1kEp4ZaUPLgoE8O0ZkOhMFW3PG8daWY q6pWQLPNjZG9rQwGrB4p7IkK80zz+S2t/MYobYDzpSNtBx3RXGqWEGgotC1RuknKi9hE dkRjS5h6FNNXwQhk+/rs0LGjb009seoOqzPt7LYKbbkl4PefGz88UvTL3Q3QfTshQW6Q XB9yDoHuvZ95AMbhuOk4ek46hE1SaYgIQl7lm3D51my9ZLDq967t9jvel9t3TRemgWBD 4nzyY/tYbSRuySINB3Znzbr9hwcmMABbZ5eZpT5X1E5kCKKiW0UuUEE6vn7PK0zu7RKO pyow== X-Gm-Message-State: AOJu0YzVXXAllZv86PjzNjWjj1gdmkYGh9/V9VjIlUXMIAvXISTgJU0d 7LZn/GjbGOMxn2JMM7dBJ6sPkZY0TPc47XDllDj6N6a4+aIA3d8kurgeNKrx5pHkwcn9CawuQ/U y X-Google-Smtp-Source: AGHT+IFaDjFT1RnxUpKKLlSvKLUUl/IyfpdfHC8Oe5CZB8ExWqKPHz6sNY6MaHq3kyjcDaRAHP443A== X-Received: by 2002:a05:6a00:14c3:b0:70d:2a88:a483 with SMTP id d2e1a72fcca58-71e37c78e82mr178815b3a.0.1728587039229; Thu, 10 Oct 2024 12:03:59 -0700 (PDT) Received: from grind.. (201-68-240-198.dsl.telesp.net.br. [201.68.240.198]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e2a9f5263sm1354532b3a.62.2024.10.10.12.03.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 12:03:58 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH 5/8] hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers Date: Thu, 10 Oct 2024 16:03:34 -0300 Message-ID: <20241010190337.376987-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241010190337.376987-1-dbarboza@ventanamicro.com> References: <20241010190337.376987-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The current logic to determine if we don't need an emulated APLIC controller, i.e. KVM will provide for us, is to determine if we're running KVM, with in-kernel irqchip support, and running aia=aplic-imsic. This is modelled by riscv_is_kvm_aia_aplic_imsic() and virt_use_kvm_aia_aplic_imsic(). This won't suffice to support irqchip_split() mode: it will match exactly the same conditions as the one above, but setting the irqchip to 'split' mode will now require us to emulate an APLIC s-mode controller, like we're doing with 'aia=aplic'. Create a new riscv_use_emulated_aplic() helper that will encapsulate this logic. Replace the uses of "riscv_is_kvm_aia_aplic_imsic()" with this helper every time we're taking a decision on emulate an APLIC controller or not. Do the same in virt.c with virt_use_emulated_aplic(). Signed-off-by: Daniel Henrique Barboza --- hw/intc/riscv_aplic.c | 24 +++++++++++++++++++++--- hw/riscv/virt.c | 14 ++++++++++++-- include/hw/intc/riscv_aplic.h | 1 + 3 files changed, 34 insertions(+), 5 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 20de8c63a2..0696e20ddf 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -32,6 +32,7 @@ #include "target/riscv/cpu.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "kvm/kvm_riscv.h" #include "migration/vmstate.h" @@ -159,6 +160,23 @@ bool riscv_is_kvm_aia_aplic_imsic(bool msimode) return kvm_irqchip_in_kernel() && msimode; } +bool riscv_use_emulated_aplic(bool msimode) +{ +#ifdef CONFIG_KVM + if (tcg_enabled()) { + return true; + } + + if (!riscv_is_kvm_aia_aplic_imsic(msimode)) { + return true; + } + + return kvm_kernel_irqchip_split(); +#else + return true; +#endif +} + static bool riscv_aplic_irq_rectified_val(RISCVAPLICState *aplic, uint32_t irq) { @@ -853,7 +871,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp) uint32_t i; RISCVAPLICState *aplic = RISCV_APLIC(dev); - if (!riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) { + if (riscv_use_emulated_aplic(aplic->msimode)) { aplic->bitfield_words = (aplic->num_irqs + 31) >> 5; aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs); aplic->state = g_new0(uint32_t, aplic->num_irqs); @@ -877,7 +895,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp) * have IRQ lines delegated by their parent APLIC. */ if (!aplic->parent) { - if (kvm_enabled() && riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) { + if (kvm_enabled() && !riscv_use_emulated_aplic(aplic->msimode)) { qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs); } else { qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); @@ -1021,7 +1039,7 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - if (!riscv_is_kvm_aia_aplic_imsic(msimode)) { + if (riscv_use_emulated_aplic(msimode)) { sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); } diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f1bdc1c535..39fd9b7c3e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -64,6 +64,13 @@ static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type) return riscv_is_kvm_aia_aplic_imsic(msimode); } +static bool virt_use_emulated_aplic(RISCVVirtAIAType aia_type) +{ + bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; + + return riscv_use_emulated_aplic(msimode); +} + static bool virt_aclint_allowed(void) { return tcg_enabled() || qtest_enabled(); @@ -776,8 +783,11 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, *msi_pcie_phandle = msi_s_phandle; } - /* KVM AIA aplic-imsic only has one APLIC instance */ - if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) { + /* + * With KVM AIA aplic-imsic, using an irqchip without split + * mode, we'll use only one APLIC instance. + */ + if (!virt_use_emulated_aplic(s->aia_type)) { create_fdt_socket_aplic(s, memmap, 0, msi_m_phandle, msi_s_phandle, phandle, &intc_phandles[0], xplic_phandles, diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h index fd0e6427d9..74ae5d87b5 100644 --- a/include/hw/intc/riscv_aplic.h +++ b/include/hw/intc/riscv_aplic.h @@ -72,6 +72,7 @@ struct RISCVAPLICState { void riscv_aplic_add_child(DeviceState *parent, DeviceState *child); bool riscv_is_kvm_aia_aplic_imsic(bool msimode); +bool riscv_use_emulated_aplic(bool msimode); DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, From patchwork Thu Oct 10 19:03:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13830894 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF8D0CFC5F7 for ; Thu, 10 Oct 2024 19:05:41 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1syySl-0006Hp-Bs; Thu, 10 Oct 2024 15:04:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1syySF-00068w-Ur for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:04:10 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1syySC-0004k6-2l for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:04:06 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-71e038f3835so1244031b3a.0 for ; Thu, 10 Oct 2024 12:04:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1728587042; x=1729191842; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oQgfMRoHrEvO7AH0VAHbJzsjsujnQzHjKLEkbNFxcL0=; b=RkMyDLV+LGLQNRwmAbp7RuSPOt5a4m1aZhY1+uklAXhS7RGTecZl3XUNisQiTwpb9u xhGf/HJUIqzYe/jBm/e/5dKTf7RkgzTUQtgS7UYTPvX/N1WLwxrLsfWnF7CI9us4JVAt VsdZ7CuMq5qllU2vLIW5Rdpnlpqg9YYTLDr1D28+EDR1HEtABbRQp85DxM5+w3OpI2I4 KvNODDh5AiQ3OBO8VMMndGbwbk8CuVf7pUNWYfsyVk0cGByO9iQ5bTq8QJnibH8BeUzF Q37+T4UVJQ4ujsCoSqMXEWDSWPh4O4Hdfy8y92y/gtpajjOEyZjgRpITYStx0Mb9k6DI 3H6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728587042; x=1729191842; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oQgfMRoHrEvO7AH0VAHbJzsjsujnQzHjKLEkbNFxcL0=; b=txuwRMdOZxrqoag1Pz55GS+dCvcMS8Yh1aDQvQyVHW1clA9cG4VOFohIB3uR9hfMOR J9MKQ+zFjowqr8nCWNyx/WAwmqpF7jWEpE/upVc5W0ajjz7uVRWOFR7XOQgiO1Ahctk9 AEPfapqzQn5xw1ukKDbWJRW7qTpJe66lYnA2e9qyjJJoV73HbLCY2283QMYEFxLWFOes J5LKdptR25OyKzvTDfaSvvEoGjpo5F1LIJDNQ6m0Oz8kGQxxfq0HzfDiJywIgXACbi33 ogfDkof4diykny/lhzaw8I0SFBiMaNZ0q8pt4fuzmbMhnAGj7DnCbyrcSwwMdvW/cxpU fTOQ== X-Gm-Message-State: AOJu0YwWEdSch0U2nB2vjTPLJpt2Pke/rXfzvrKw1GTf7QcHuq2oFgFf JVkNukMNDaKxnGWVdY2nHPtN7VZBkhDetq6rIMG+PKydA3DtGVnDKTrhI7HvwNQrgmRS7oY8q5Q o X-Google-Smtp-Source: AGHT+IEA9idLpTHiam3GdRScYAW8M32ja0xSHc47413h/ABH4V9I0cXwzgrgcVpca4nwHp3FI2aI1Q== X-Received: by 2002:a05:6a00:a1f:b0:71d:fb29:9edc with SMTP id d2e1a72fcca58-71e37e2c282mr102576b3a.3.1728587042466; Thu, 10 Oct 2024 12:04:02 -0700 (PDT) Received: from grind.. (201-68-240-198.dsl.telesp.net.br. [201.68.240.198]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e2a9f5263sm1354532b3a.62.2024.10.10.12.03.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 12:04:02 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH 6/8] hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic Date: Thu, 10 Oct 2024 16:03:35 -0300 Message-ID: <20241010190337.376987-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241010190337.376987-1-dbarboza@ventanamicro.com> References: <20241010190337.376987-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The last step to enable KVM AIA aplic-imsic with irqchip in split mode is to deal with how MSIs are going to be sent. In our current design we don't allow an APLIC controller to send MSIs unless it's on m-mode. And we also do not allow Supervisor MSI address configuration via the 'smsiaddrcfg' and 'smsiaddrcfgh' registers unless it's also a m-mode APLIC controller. Add a new RISCVACPLICState attribute called 'kvm_msicfgaddr'. This attribute represents the base configuration address for MSIs, in our case the base addr of the IMSIC controller. This attribute is being set only when running irqchip_split() mode with aia=aplic-imsic. During riscv_aplic_msi_send() we'll check if the attribute was set to skip the check for a m-mode APLIC controller and to change the resulting MSI addr by adding kvm_msicfgaddr right before address_space_stl_le(). Signed-off-by: Daniel Henrique Barboza --- hw/intc/riscv_aplic.c | 42 +++++++++++++++++++++++++++-------- hw/riscv/virt.c | 6 ++++- include/hw/intc/riscv_aplic.h | 6 +++++ 3 files changed, 44 insertions(+), 10 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 0696e20ddf..4de458e395 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -177,6 +177,16 @@ bool riscv_use_emulated_aplic(bool msimode) #endif } +void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr) +{ +#ifdef CONFIG_KVM + if (riscv_use_emulated_aplic(aplic->msimode)) { + aplic->kvm_msicfgaddr = extract64(addr, 0, 32); + aplic->kvm_msicfgaddrH = extract64(addr, 32, 32); + } +#endif +} + static bool riscv_aplic_irq_rectified_val(RISCVAPLICState *aplic, uint32_t irq) { @@ -377,13 +387,16 @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic, uint32_t lhxs, lhxw, hhxs, hhxw, group_idx, msicfgaddr, msicfgaddrH; aplic_m = aplic; - while (aplic_m && !aplic_m->mmode) { - aplic_m = aplic_m->parent; - } - if (!aplic_m) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n", - __func__); - return; + + if (!aplic->kvm_splitmode) { + while (aplic_m && !aplic_m->mmode) { + aplic_m = aplic_m->parent; + } + if (!aplic_m) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n", + __func__); + return; + } } if (aplic->mmode) { @@ -415,6 +428,11 @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic, addr |= (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs)); addr <<= APLIC_xMSICFGADDR_PPN_SHIFT; + if (aplic->kvm_splitmode) { + addr |= aplic->kvm_msicfgaddr; + addr |= ((uint64_t)aplic->kvm_msicfgaddrH << 32); + } + address_space_stl_le(&address_space_memory, addr, eiid, MEMTXATTRS_UNSPECIFIED, &result); if (result != MEMTX_OK) { @@ -888,6 +906,10 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp) memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, aplic, TYPE_RISCV_APLIC, aplic->aperture_size); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); + + if (kvm_enabled()) { + aplic->kvm_splitmode = true; + } } /* @@ -935,8 +957,8 @@ static Property riscv_aplic_properties[] = { static const VMStateDescription vmstate_riscv_aplic = { .name = "riscv_aplic", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (const VMStateField[]) { VMSTATE_UINT32(domaincfg, RISCVAPLICState), VMSTATE_UINT32(mmsicfgaddr, RISCVAPLICState), @@ -944,6 +966,8 @@ static const VMStateDescription vmstate_riscv_aplic = { VMSTATE_UINT32(smsicfgaddr, RISCVAPLICState), VMSTATE_UINT32(smsicfgaddrH, RISCVAPLICState), VMSTATE_UINT32(genmsi, RISCVAPLICState), + VMSTATE_UINT32(kvm_msicfgaddr, RISCVAPLICState), + VMSTATE_UINT32(kvm_msicfgaddrH, RISCVAPLICState), VMSTATE_VARRAY_UINT32(sourcecfg, RISCVAPLICState, num_irqs, 0, vmstate_info_uint32, uint32_t), diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 39fd9b7c3e..e5202bad10 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1221,7 +1221,7 @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, int base_hartid, int hart_count) { int i; - hwaddr addr; + hwaddr addr = 0; uint32_t guest_bits; DeviceState *aplic_s = NULL; DeviceState *aplic_m = NULL; @@ -1271,6 +1271,10 @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, VIRT_IRQCHIP_NUM_PRIO_BITS, msimode, false, aplic_m); + if (kvm_enabled() && msimode) { + riscv_aplic_set_kvm_msicfgaddr(RISCV_APLIC(aplic_s), addr); + } + return kvm_enabled() ? aplic_s : aplic_m; } diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h index 74ae5d87b5..489b9133c2 100644 --- a/include/hw/intc/riscv_aplic.h +++ b/include/hw/intc/riscv_aplic.h @@ -68,11 +68,17 @@ struct RISCVAPLICState { uint32_t num_irqs; bool msimode; bool mmode; + + /* To support KVM aia=aplic-imsic with irqchip split mode */ + bool kvm_splitmode; + uint32_t kvm_msicfgaddr; + uint32_t kvm_msicfgaddrH; }; void riscv_aplic_add_child(DeviceState *parent, DeviceState *child); bool riscv_is_kvm_aia_aplic_imsic(bool msimode); bool riscv_use_emulated_aplic(bool msimode); +void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr); DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, From patchwork Thu Oct 10 19:03:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13830895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97AFACFC5F7 for ; Thu, 10 Oct 2024 19:05:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1syySl-0006Hf-Bl; Thu, 10 Oct 2024 15:04:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1syySH-00068z-1g for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:04:12 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1syySF-0004kP-NJ for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:04:08 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-71df2b0a2f7so1179773b3a.3 for ; Thu, 10 Oct 2024 12:04:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1728587045; x=1729191845; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uMbhqBUI4BThm42iYqRzGr0189fZkGi1HZ2Ne6+spLA=; b=YGFzpzhRim7P++/zlLCQmD59WTgJ3l47IWUVGMpjNC7u81egx4vgqimV7i4uu9o8Ej N/zU0yeFNPgTF4aVQv/coxhx/8fVjIdamqfwK7owex2uj7FJ8mL/GvBRdqwl8Rgef2hk wCx1E0A3YxCnbmYyB8EvxegmfqjCULGENtNntezg7vdsrlOCUGmm+X3yfoVL97zOZu7z 6q1+LZbDyfdjKg+N72FtlIfowSPptUiZXrUWd1E3dNO/XqDgu4WpYc0YSsYM0iy0lDBo AtiljjW7I4y4rpH0hEwg5IA/szcFAicsnFqXdMHkqcLDkuDNAMA+3a/RAVhvIw8292sJ f2Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728587045; x=1729191845; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uMbhqBUI4BThm42iYqRzGr0189fZkGi1HZ2Ne6+spLA=; b=HjsR8+vfBY6dE1bjdCZoPGsqL2KmHzoaMS/Bbn6sorp48aF/IQNXRrAXTaYtmCdIOb w9YPP9FM3M5sM9S6J01GZtz8sXCx4EtnaThX+NGOHE5pRQwRORL1up2b3Y6WcBWLD8Gh 4FqgreIjRqIbq8G3Z74Vig2cCjPMaQmN4Bc5wsqcjBAMLMg3FT5HXSY+8Rci77szZc33 MLVdUsop6884RAQPJ6Y58wTFAAL0RTDJ0mc7O4GDYzT2i0c9KfoQcpJkQfBLtSm8UuLq od3THXQJkz/J1EpohNc1Hxw5oIsmX8veOTg7bj5ZzvymHyd932PCNBvjmraPv7d5qqoC zRWA== X-Gm-Message-State: AOJu0Yw7zmUL0KGw30ScwCvnOBx1kxE7diZyLdoN3C6Lr1GPbLlUnnl9 Yrbu9ODGSaKAx6T6zQueHyKfFJ4lzR8ZWdVluUMNxf+ja+A/MU0i66vNCRKPfgP7PYE34tW1hkW R X-Google-Smtp-Source: AGHT+IHbp1uGkw0ilcVCTKLbhAM/6+cZ3JOvqmiQKpmc1GXspro/ZT0rUyFxTKe/EdmOHWIleXur5A== X-Received: by 2002:a05:6a00:2349:b0:714:3a4b:f78f with SMTP id d2e1a72fcca58-71e37f577aemr87636b3a.20.1728587045587; Thu, 10 Oct 2024 12:04:05 -0700 (PDT) Received: from grind.. (201-68-240-198.dsl.telesp.net.br. [201.68.240.198]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e2a9f5263sm1354532b3a.62.2024.10.10.12.04.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 12:04:05 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH 7/8] target/riscv/kvm: remove irqchip_split() restriction Date: Thu, 10 Oct 2024 16:03:36 -0300 Message-ID: <20241010190337.376987-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241010190337.376987-1-dbarboza@ventanamicro.com> References: <20241010190337.376987-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Remove the 'irqchip_split()' restriction in kvm_arch_init() now that we have support for "-accel kvm,kernel-irqchip=split". Signed-off-by: Daniel Henrique Barboza --- target/riscv/kvm/kvm-cpu.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index a92a46694a..3d0584277c 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1401,11 +1401,6 @@ int kvm_arch_init(MachineState *ms, KVMState *s) int kvm_arch_irqchip_create(KVMState *s) { - if (kvm_kernel_irqchip_split()) { - error_report("-machine kernel_irqchip=split is not supported on RISC-V."); - exit(1); - } - /* * We can create the VAIA using the newer device control API. */ From patchwork Thu Oct 10 19:03:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13830896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74212CFC5F7 for ; Thu, 10 Oct 2024 19:05:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1syySy-0006XB-37; Thu, 10 Oct 2024 15:04:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1syySL-0006A1-Rb for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:04:18 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1syySK-0004kz-9Y for qemu-devel@nongnu.org; Thu, 10 Oct 2024 15:04:13 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-71df4620966so1205400b3a.0 for ; Thu, 10 Oct 2024 12:04:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1728587049; x=1729191849; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PUee2NQrvjsGKbH1dpkkylkOYkQbKE2imhmGuff3t2o=; b=OEf2wg2VBusX/nstOBrYk19Zh9FCv8ZNsXn3w1PA01iCQPmTDc3P+LObB/YhtOW4vu jXymc/EwUACslIiLjCnH3z4wjiR6+0gCGl5EiKbjV9TcZATkoCuP3dqMIjDDBLRAZewr sALDjGl5kp94WjqPZH2BnTzUxS4ColU41wO0WZH82La8k1mLVfQSKcqSLg+qJXnlpAFQ eu9JlsV8aPvV5Bb2ap0Qbu0im6cH1t7+gyzVyH5n6UcYwBK3bvMjKoKIPrFR6ogVolM7 ImDh/C5XazUf5nDiqv0Zw4tdTVOi6GGf52mGNrX4y+/8T1TPkgCkHJPEQuR5n2PqoqTX 7fOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728587049; x=1729191849; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PUee2NQrvjsGKbH1dpkkylkOYkQbKE2imhmGuff3t2o=; b=AZdgYk+b+PF4OAtPMQF3Z/3Zc0d+fLzI5IT3gQQaZ7glmZRN3lQmx8+DlgFE3KtdnK sByN50w0GwSfuL1g3UQQPz7WR7gfyRuoBEzwrVMZtRZpgQ1TEZ9+PQe0fYCBZxOVH1/C FhKkhpojfdlCDF8hwIuNWliwPij3KC6STnxl7gjZHlLtRVTHnjixA54i2Wv8CSTxRyxt myBlB0Cs++GgTzcWT0ayThHYVR9LTowhBeA+mr4ZBDVbCe5sSrSJ2sUnpXzIS92ml3tl 57qlfThwnPY1gDvaO3LKn5CJsR56hTPKbPXwLbT6kUQ4f/BeOpZ5o+9SGv96KINIcqTY Mx0g== X-Gm-Message-State: AOJu0YynswaPXflpwKnmXMnjJLgEZbYPg3IgqY85lK7wo6Ekoc9bPxTx 1xLIkAKdbm6vX2SrcDD6d7jfEYLT/3szL08N9rzdZ4iZeaHAwg9HdbOvfi9T6srXUXsUrlL0ijU n X-Google-Smtp-Source: AGHT+IF4Xei35zUQ8hRY/TdCvyvNusWYc9A56aQqDUKJ0WFf+/iEbc04bycPwJj13+5mzuCCiG2+/Q== X-Received: by 2002:a05:6a00:2d9b:b0:714:1ca1:7134 with SMTP id d2e1a72fcca58-71e37f4eefdmr74136b3a.18.1728587048971; Thu, 10 Oct 2024 12:04:08 -0700 (PDT) Received: from grind.. (201-68-240-198.dsl.telesp.net.br. [201.68.240.198]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e2a9f5263sm1354532b3a.62.2024.10.10.12.04.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 12:04:08 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH 8/8] docs: update riscv/virt.rst with kernel-irqchip=split support Date: Thu, 10 Oct 2024 16:03:37 -0300 Message-ID: <20241010190337.376987-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241010190337.376987-1-dbarboza@ventanamicro.com> References: <20241010190337.376987-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Also add a new page, docs/specs/riscv-aia.rst, where we're documenting the state of AIA support in QEMU w.r.t the controllers being emulated or not depending on the AIA and accelerator settings. Signed-off-by: Daniel Henrique Barboza --- docs/specs/index.rst | 1 + docs/specs/riscv-aia.rst | 83 ++++++++++++++++++++++++++++++++++++++ docs/system/riscv/virt.rst | 7 ++++ 3 files changed, 91 insertions(+) create mode 100644 docs/specs/riscv-aia.rst diff --git a/docs/specs/index.rst b/docs/specs/index.rst index 6495ed5ed9..9a7d61161f 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -36,3 +36,4 @@ guest hardware that is specific to QEMU. vmgenid rapl-msr rocker + riscv-aia diff --git a/docs/specs/riscv-aia.rst b/docs/specs/riscv-aia.rst new file mode 100644 index 0000000000..8097e2f897 --- /dev/null +++ b/docs/specs/riscv-aia.rst @@ -0,0 +1,83 @@ +.. _riscv-aia: + +RISC-V AIA support for RISC-V machines +====================================== + +AIA (Advanced Interrupt Architecture) support is implemented in the ``virt`` +RISC-V machine for TCG and KVM accelerators. + +The support consists of two main modes: + +- "aia=aplic": adds one or more APLIC (Advanced Platform Level Interrupt Controller) + devices +- "aia=aplic-imsic": adds one or more APLIC device and an IMSIC (Incoming MSI + Controller) device for each CPU + +From an user standpoint, these modes will behave the same regardless of the accelerator +used. From a developer standpoint the accelerator settings will change what it being +emulated in userspace versus what is being emulated by an in-kernel irqchip. + +When running TCG, all controllers are emulated in userspace, including machine mode +(m-mode) APLIC and IMSIC (when applicable). + +When running KVM: + +- no m-mode is provided, so there is no m-mode APLIC or IMSIC emulation regardless of + the AIA mode chosen +- with "aia=aplic", s-mode APLIC will be emulated by userspace +- with "aia=aplic-imsic" there are two possibilities. If no additional KVM option + is provided there will be no APLIC or IMSIC emulation in userspace, and the virtual + machine will use the provided in-kernel APLIC and IMSIC controllers. If the user + chooses to use the irqchip in split mode via "-accel kvm,kernel-irqchip=split", + s-mode APLIC will be emulated while using the s-mode IMSIC from the irqchip + +The following table summarizes how the AIA and accelerator options defines what +we will emulate in userspace: + + +.. list-table:: How AIA and accel options changes controller emulation + :widths: 25 25 25 25 25 25 25 + :header-rows: 1 + + * - Accel + - Accel props + - AIA type + - APLIC m-mode + - IMSIC m-mode + - APLIC s-mode + - IMSIC s-mode + * - tcg + - --- + - aplic + - emul + - n/a + - emul + - n/a + * - tcg + - --- + - aplic-imsic + - emul + - emul + - emul + - emul + * - kvm + - --- + - aplic + - n/a + - n/a + - emul + - n/a + * - kvm + - none + - aplic-imsic + - n/a + - n/a + - in-kernel + - in-kernel + * - kvm + - irqchip=split + - aplic-imsic + - n/a + - n/a + - emul + - in-kernel diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index 9a06f95a34..8cbedf73ef 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -110,6 +110,13 @@ The following machine-specific options are supported: MSIs. When not specified, this option is assumed to be "none" which selects SiFive PLIC to handle wired interrupts. + This option also interacts with '-accel kvm'. When using "aia=aplic-imsic" + with KVM, it is possible to set the use of the kernel irqchip in split mode + by using "-accel kvm,kernel-irqchip=split". In this case the ``virt`` machine + will emulate the APLIC controller instead of using the APLIC controller from + the irqchip. See :ref:`riscv-aia` for more details on all available AIA + modes. + - aia-guests=nnn The number of per-HART VS-level AIA IMSIC pages to be emulated for a guest