From patchwork Fri Oct 11 02:37:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13831963 Received: from mail-qk1-f175.google.com (mail-qk1-f175.google.com [209.85.222.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFAE417BA9; Fri, 11 Oct 2024 02:37:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728614258; cv=none; b=ijvkMyZXBsICCPzje4Sut+xzXNPeZKhcRpvk6JmV0D2WgSUf51KlN0rFRRcM1YPR0xPRQj5rqtsXxK4Z5tN4kzOWJ/Wkoqf9bHxvc6IxO/rB/KFJKPLgWNu3yO8QU/vJy0xHPXDB0pdH8j3f81HrILPU00lxxZDFvV/ZZphRQqM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728614258; c=relaxed/simple; bh=8lhdgPeFNdRxMQJrkBrFIQe368g3nhGpuoXWa83pmbU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WcyR8ovZdHxk1kxyTX40TDsmsHwCBmtZhvZzIuVtdSNJw9IOTqwWJBXEHlFMmlnszk3FoopdR2spZ3NmF0dInO2sMQnWX/d1kmoGHcfqUxWf6TJYl13QsI2QkREWpdp/MZBzCVyCpVaH3pfolOOak3coA6PvBJJssvqOKU8DvcA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kS6f70Gc; arc=none smtp.client-ip=209.85.222.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kS6f70Gc" Received: by mail-qk1-f175.google.com with SMTP id af79cd13be357-7b111e086e0so92669685a.0; Thu, 10 Oct 2024 19:37:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1728614256; x=1729219056; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8SnnfKSH45WcECyzTIA3ELBtlq8aYQBuQ/JJ9N0zNs8=; b=kS6f70GcBMuwwag77DsYJwt05RgKZUxKs2/i+kOdX2Dpx6B/JXFspCvcFAXC0c8g+h 5XpiwGXZJwYgFHdNesDBaoYpRjmRNTUWZMktcIM9h0e/6CiFoSaMy856UEFWm0lxTeuJ v2Q8UD48gLVgb1MJUxkRiKmARrUDneCIC7Vl+dkhR0zCnXU63Ro9Iw3esM7m2IBWeW06 YqhrjyaNCZotk928sUD2QKBmyvl+IQsEY3D/Jf0RAX2NvVo70X+H/sLffgR8e9W/h8i5 E8sI6qomS84UsUdd7r37bdQkhkl7DzTVDkA2qfDQ+jUx2L6iNjoBL6zYa73ol1A3IsGd Hdbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728614256; x=1729219056; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8SnnfKSH45WcECyzTIA3ELBtlq8aYQBuQ/JJ9N0zNs8=; b=cvkjZ8JrrUyRhyMUr4ylm3ssX4rqeZG9cSRfFXX1ePqUXNXBare6STLWpivLi3R9cP Fw0NliNld+yDGu5f8nHyEoItFD7Lz74X5NWKhM3awFmB4U2N/0IJmnpIz98TloW/OTJa L3VZoLzy2L+XFltOZQC7KimisSADNnoXaUCwDjvtt/WvJoy9cWpw2D9Cj51cbC9TKUk8 5UfmRgvbAaLnSsR8RvaAAKMIFfgU5+d0qJe4jq4GAAl0GuovtCp7o1vi0S70QGn+QON1 1+QEVEYm26Sb03xqkuY9HnEBzOWVYHH5uPsWaaugid+RHA65kcEyMGiPrlOR2pSFS8Oa j2cg== X-Forwarded-Encrypted: i=1; AJvYcCUp2obrW2lhJwrFKapoBPTsAGoeL0g90sadYY6zdO+9PkUCr6Oz8phorUn8Y7UZa1FzGf3Rt/kOJpqtpLY=@vger.kernel.org, AJvYcCVVcollY6WaGpyscetNiCicY7rANsuOEZ/j9HAgGlg5EfC9vwl2uSUGANcb1ZGzY2oFhHKdTokiGrIU@vger.kernel.org, AJvYcCXEFjRniIuGxuMndS2Ld5jo64I8891hrkqxr6OZSAQM8r01WytHJBdxHEz2kGIhxnlqK4SjFPhA52wg@vger.kernel.org, AJvYcCXOlwZvuejHrESsg90GWkOJXQahC5ro19X3yVRitW65bmN9ilzMxTyRNonG9pW2HxR7oD036Yi0D+zEEiIp9A==@vger.kernel.org X-Gm-Message-State: AOJu0YxBxOu2M/didEgzLtdFHQoX9U3G5Gm0YkmtXu0UcfL8ImldTE7G ktegFJVh6pHjQCD51h7nhDgfTZtIog3HuTLQMho812mDbsARmjn7 X-Google-Smtp-Source: AGHT+IHrB6vjI/VIow+HKTzPmrIMhSj9Rpje1pcp6jRjboLQSbgWOBAtmj/TFU4pugx4K6xyy0ud4w== X-Received: by 2002:a05:6214:4687:b0:6cb:c8ef:3353 with SMTP id 6a1803df08f44-6cbeff74b80mr17312306d6.2.1728614255711; Thu, 10 Oct 2024 19:37:35 -0700 (PDT) Received: from localhost ([2607:fea8:52a3:d200::786d]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6cbe8679a7csm11320106d6.135.2024.10.10.19.37.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 19:37:34 -0700 (PDT) From: Richard Acayan To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , "Bryan O'Donoghue" , Mauro Carvalho Chehab , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-media@vger.kernel.org Cc: Vladimir Zapolskiy , Richard Acayan Subject: [PATCH v6 1/5] dt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatible Date: Thu, 10 Oct 2024 22:37:26 -0400 Message-ID: <20241011023724.614584-8-mailingradian@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241011023724.614584-7-mailingradian@gmail.com> References: <20241011023724.614584-7-mailingradian@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The camera clocks on SDM670 and SDM845 have no significant differences that would require a change in the clock controller driver. The only difference is the clock frequency at each level of the power domains, which is not specified in the clock driver. There should still be a compatible specific to the SoC, so add the compatible for SDM670 with the SDM845 compatible as fallback. Link: https://android.googlesource.com/kernel/msm/+/d4dc50c0a9291bd99895d4844f973421c047d267/drivers/clk/qcom/camcc-sdm845.c#2048 Suggested-by: Vladimir Zapolskiy Suggested-by: Konrad Dybcio Link: https://lore.kernel.org/linux-arm-msm/7d26a62b-b898-4737-bd53-f49821e3b471@linaro.org Signed-off-by: Richard Acayan Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/qcom,sdm845-camcc.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml index 810b852ae371..fa95c3a1ba3a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml @@ -20,7 +20,11 @@ allOf: properties: compatible: - const: qcom,sdm845-camcc + oneOf: + - items: + - const: qcom,sdm670-camcc + - const: qcom,sdm845-camcc + - const: qcom,sdm845-camcc clocks: items: From patchwork Fri Oct 11 02:37:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13831964 Received: from mail-qk1-f170.google.com (mail-qk1-f170.google.com [209.85.222.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF40A1F4737; Fri, 11 Oct 2024 02:37:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728614262; cv=none; b=eVgxs5H4ge0p1lnPeMt4Ntr3iszKk6q7ykpk/kLMTRixtk49ocVAmjcX0fubvHTfa8H0ocyb5I1KSM0706TbDDX2x4t5O+w4qNWQS5nzbhIWU3o+fL+dgAaxbUxKRauBMHBo8c3uO1OI0IOSClwVGptfpcr4uc+eBGFqQNFH9ak= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728614262; c=relaxed/simple; bh=XWzQVx+ZPbKyT7z7RzFveXK/YpRNZFjsz73AFunAuUA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Lw7J0Xz29Dxv6rR170WA86FLXvluTSmYQl4L6lHhsYvELKjcl8eJM9vEXe1dTlRrGHabp30qP3smDV/zoUjSeP++iNUGW1qGHXoPkbLbV7cjND/X2jEuADOlb4rjpsMzchqGWLeCEh7qZPlsliqd9HOYKgHaYogaZnNq9kkfAnk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kAWJgtXy; arc=none smtp.client-ip=209.85.222.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kAWJgtXy" Received: by mail-qk1-f170.google.com with SMTP id af79cd13be357-7ae3e3db294so77701785a.2; Thu, 10 Oct 2024 19:37:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1728614259; x=1729219059; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QvlaSJjrx7WxFR3R/ISTFeU1vJcVcOi9I16YDSomeh8=; b=kAWJgtXyaRno1xfCLTnyN+T9ZjrZ6iVXjg1aYaTw4uGFVpQhi3tci1+/YL6pQFEjkY dX+wr6axBVb5RsskRl+tOqohvJdRxnuZMI26gD90dqSa2qdiB/XaHSNTQ5IvFriR9cV5 7M61M7Wm1NkfT5457qcMmmcUZ5qTMNmPRMlmN5SCRfuwtQNRoaLtPggPk8/BIwm96iBV o8PCy5/OCzB8csZJttDpemo5f0RtDRmat+4TZkDo1SklAfh1cntJI0JAUFvLkKJxacgi hawimZIvvkvxZ6TYHGwbCfHAR+iy+3pEehIG2sn4rx9VDjVJXJwA2FlDQQagMYF2KGiQ Bhcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728614259; x=1729219059; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QvlaSJjrx7WxFR3R/ISTFeU1vJcVcOi9I16YDSomeh8=; b=nLgLKXQtBHBko6fHyVdzBNzE3rHRwCBB2D7TQP9GQu1GGd3Ob4dL++FBg+U7BR6dVd OLCG3BOIWknemqTDGDO4Z8EsNusWVSJYbpwFVyrIMebkYrstPaBv9tRcmlcdTqAuTZa6 7ZsaRSosNhd/IcoapJg39aLCHoLjrhifazKNt0aDYI276OkWoCz5xZ8GQbdsDeINJRuL irxN6K0vp+Hyt8zt8Q8Sj/W+EJAN70Xtg0ocyT4E+6/QIStOmmSbxQHp+KAkRkov7eyW HecLv2xVy2CZ0i8LNp+uu7KNvgHXvkHOdOPl0jcxsWdXE528u7rgYOMnxuSAjn/GQpUG geJg== X-Forwarded-Encrypted: i=1; AJvYcCVWiUA6gIBFNYAD+bCkUosaiE1kaQ5ChvRufJcFlNJCR2KR/c7Op9SgwWwlEOPbISbe6BXp6tCkwBjcKc+UTQ==@vger.kernel.org, AJvYcCVqan+CDD0tEnJO+SXXuni+ByKKeR/LuILdkI4VXeBxVhHjTkIe4X0/RNezCvWBXb8lkf1/iRKYi3jnyOk=@vger.kernel.org, AJvYcCVuPKGFo6b/VlkT+ckgvBXBEgPIF4/U/nX1Bc0riEnEg1WTKyM7lZD3ySkH3Tc8J96t5JUNQsvNP3a+@vger.kernel.org, AJvYcCWRM0cbulPSUPpmE9kM1ttqTMjKyBLAfp/mekmpVwB4+mo0wpOmxhKCmpYYHte4hX2cGEVBnnmDc7R7@vger.kernel.org X-Gm-Message-State: AOJu0YyKDvRuEK6rDudb9LvY83GY/EwXkyFphV2NagCTi3iTwplC4Hyp qpWetGy/L0ufzOptpCHo6gq2ebw7Q/3hSA/Rnol99w2arThCTpdW X-Google-Smtp-Source: AGHT+IEUAaRz4eKzRY7XjXTOmoswI1fwrJotGKxcEIO6Cxd9uaoGuPF+2VGlQ2tCHvdv0qP4tBHPyw== X-Received: by 2002:a05:620a:1929:b0:7a1:c40c:fc66 with SMTP id af79cd13be357-7b11a3b83c1mr179605785a.56.1728614259463; Thu, 10 Oct 2024 19:37:39 -0700 (PDT) Received: from localhost ([2607:fea8:52a3:d200::786d]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7b1148dc6fcsm96695585a.38.2024.10.10.19.37.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 19:37:38 -0700 (PDT) From: Richard Acayan To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , "Bryan O'Donoghue" , Mauro Carvalho Chehab , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-media@vger.kernel.org Cc: Vladimir Zapolskiy , Richard Acayan Subject: [PATCH v6 2/5] dt-bindings: media: camss: Add qcom,sdm670-camss Date: Thu, 10 Oct 2024 22:37:27 -0400 Message-ID: <20241011023724.614584-9-mailingradian@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241011023724.614584-7-mailingradian@gmail.com> References: <20241011023724.614584-7-mailingradian@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 As found in the Pixel 3a, the Snapdragon 670 has a camera subsystem with 3 CSIDs and 3 VFEs (including 1 VFE lite). Add this camera subsystem to the bindings. Adapted from SC8280XP camera subsystem. Signed-off-by: Richard Acayan --- .../bindings/media/qcom,sdm670-camss.yaml | 318 ++++++++++++++++++ 1 file changed, 318 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml diff --git a/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml new file mode 100644 index 000000000000..670502532d28 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sdm670-camss.yaml @@ -0,0 +1,318 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sdm670-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM670 Camera Subsystem (CAMSS) + +maintainers: + - Richard Acayan + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sdm670-camss + + reg: + maxItems: 9 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite + + clocks: + maxItems: 22 + + clock-names: + items: + - const: gcc_camera_ahb + - const: gcc_camera_axi + - const: soc_ahb + - const: camnoc_axi + - const: cpas_ahb + - const: csi0 + - const: csi1 + - const: csi2 + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: vfe0_axi + - const: vfe0 + - const: vfe0_cphy_rx + - const: vfe1_axi + - const: vfe1 + - const: vfe1_cphy_rx + - const: vfe_lite + - const: vfe_lite_cphy_rx + + interrupts: + maxItems: 9 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite + + iommus: + maxItems: 4 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: top + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY0. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY1. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY2. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + +required: + - reg + - reg-names + - clock-names + - clocks + - compatible + - interrupts + - interrupt-names + - iommus + - power-domains + - power-domain-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss@ac65000 { + compatible = "qcom,sdm670-camss"; + + reg = <0 0x0acb3000 0 0x1000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0ac65000 0 0x1000>, + <0 0x0ac66000 0 0x1000>, + <0 0x0ac67000 0 0x1000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acc4000 0 0x4000>; + reg-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite"; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite"; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>; + clock-names = "gcc_camera_ahb", + "gcc_camera_axi", + "soc_ahb", + "camnoc_axi", + "cpas_ahb", + "csi0", + "csi1", + "csi2", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe_lite", + "vfe_lite_cphy_rx"; + + iommus = <&apps_smmu 0x808 0x0>, + <&apps_smmu 0x810 0x8>, + <&apps_smmu 0xc08 0x0>, + <&apps_smmu 0xc10 0x8>; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "top"; + + vdda-phy-supply = <&vreg_l1a_1p225>; + vdda-pll-supply = <&vreg_l8a_1p8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy_ep0: endpoint { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&front_sensor_ep>; + }; + }; + }; + }; + }; From patchwork Fri Oct 11 02:37:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13831965 Received: from mail-qv1-f45.google.com (mail-qv1-f45.google.com [209.85.219.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32F041F4705; Fri, 11 Oct 2024 02:37:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728614265; cv=none; b=gs6tajRpcclrsZJRmIvcDV11ogUUWBymc3ZAKfVx3ZYS4A+P2xQX1kFfrzGvm6vOsNmN+4DZP5apXlRqtVow1Uj3a6+5LAwCDyrSsLZ20Av1OCEDRDU2cf5aM1Fi+jSPdS5mLtAw94UknzjW8gmHJRJZq+2AK/pJJuQKIvXV6uk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728614265; c=relaxed/simple; bh=QN4MBFEZOLzvPC2Qyq1NvXhktKWw+B7Ivl/4rFoVMh4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lbwVPY5pzpEyDzVDtbsXQ/9YF/vr1FwF+76vG/nAl3/Ztf7fZX6nzprVR4w7097HBR7pAspGNgXn5a54l/CYR5OZAXf7tUWcs6+dd7VKQ7ZCQaoYQpMjmU3I7MwcScp8RgXT8VjyFvoUndCT/tyKOwVouCHxohR8ImFicJl5KBA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=UQ2FuDv3; arc=none smtp.client-ip=209.85.219.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UQ2FuDv3" Received: by mail-qv1-f45.google.com with SMTP id 6a1803df08f44-6cbceb48613so10259476d6.2; Thu, 10 Oct 2024 19:37:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1728614263; x=1729219063; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VXMm/arYkHMi5r3l8Xx2ZjY/5qj1z8qRgxCdBYIJydI=; b=UQ2FuDv3m/tx5y+j+D//vuLn55KBvq7Wh5iXjpFbn2DZcbDiaM6Nq62segxmBFZkt1 SS62kr2zdfYkTNdDpXyLrI+kLO30daiAWl1X2WdEWwpVjxTcmgfUySnDD2J60jwyoWy+ 2L3WLOCPwd4tDDmR5tAwO/VTZ0HyVl1DY0kb1roVrDxoP0RJfC06/eb62J0m+Lj/XmxR DHIYKUINDboqv5AJhtDkB2n9UIQC2VJjV2PqFU7RVqBfeGJftvk28nzIoyvPwgjBbLZh DRtgzih1oRXNJxNU7OGzSOTLZPrZaNCN/d1D0dKUnX3wCFgKiT2LV6/PJeZFTjfnajkl ARQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728614263; x=1729219063; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VXMm/arYkHMi5r3l8Xx2ZjY/5qj1z8qRgxCdBYIJydI=; b=gJZN27sJnsE7DSK9gCQOmSqo5CD0MGvn8IhsPPA55RKwnU0bTXMYuy5DVQEiw7gsQW JAkJ62nymoqCIFlBkgq3s8qJN7YUwL/Y7f1y9oP+HqufnjDTXAFHVk7IO2htE9qAiUBq N4rKuwjMAnRuRj0X3abZgsVmYz38CKLMUvhw+8LGkSWI/bKe+avpJst0pBbjnb+k3CKc IxfvLD6+6b7e5M4ex5RextuQcYSCrL9LXjDPQ+8Jla7dlXGtRo3qQNt2EoByDxHhe32H SYgAIM5MD98KuxQB9GzsjPHyfz1iHYtAUm5YjNRk4gUTperKAQF2RGomD+zFl+7TV0vm djBg== X-Forwarded-Encrypted: i=1; AJvYcCUKcExFJNxlb60/C48GDRe0yqJO9CI1tV8rDJrVl7sG8IDnGWlW8X99kpruR/lrp4+zgG2mK3TFA01fkR0=@vger.kernel.org, AJvYcCUzkN3YRAzk2PMJDBHG3mNfDUydPt7vlewdFNK0ZV76osCeolQaF+kWBmcgPjbMRbPh/vt/p+VyglnKMmzxoA==@vger.kernel.org, AJvYcCVk8OX1+g77QPA7ncwYXu/3umeEO/vykgG8OBjVgStpVuOEzFOInkIGuAFfRAkfApukmapCjE/17pd6@vger.kernel.org, AJvYcCVwkEvhQqj4QedIjkFotROkOmpLX2k7+4/7t6Am8/wZtjFzQ7XC1EZX+jXmVr1x1aYTJL9XIfVOoNK6@vger.kernel.org X-Gm-Message-State: AOJu0YysyrvBh6Ls9GUv9dJ759TDrrlownoReAp9LQQ38PqE7LKo+zir UBIk+K/yyoK4a0V2x56oL2eHpFL5EJtD7JgRKdZFydkVa3xVzL1j X-Google-Smtp-Source: AGHT+IFrNIErB5b1t6Av6dnkmWH+LuSQTiSFLZtp26/V8QdRh2AbmVwG+KQIonx/PPYaAj4gJnqynw== X-Received: by 2002:a05:6214:3a05:b0:6cb:c83e:3f98 with SMTP id 6a1803df08f44-6cbf0100329mr14263896d6.43.1728614263109; Thu, 10 Oct 2024 19:37:43 -0700 (PDT) Received: from localhost ([2607:fea8:52a3:d200::786d]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6cbe85a5b8asm11572486d6.14.2024.10.10.19.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 19:37:41 -0700 (PDT) From: Richard Acayan To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , "Bryan O'Donoghue" , Mauro Carvalho Chehab , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-media@vger.kernel.org Cc: Vladimir Zapolskiy , Richard Acayan Subject: [PATCH v6 3/5] media: qcom: camss: add support for SDM670 camss Date: Thu, 10 Oct 2024 22:37:28 -0400 Message-ID: <20241011023724.614584-10-mailingradian@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241011023724.614584-7-mailingradian@gmail.com> References: <20241011023724.614584-7-mailingradian@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The camera subsystem for the SDM670 the same as on SDM845 except with 3 CSIPHY ports instead of 4. Add support for the SDM670 camera subsystem. Signed-off-by: Richard Acayan Reviewed-by: Bryan O'Donoghue Acked-by: Bryan O'Donoghue Reviewed-by: Vladimir Zapolskiy --- drivers/media/platform/qcom/camss/camss.c | 191 ++++++++++++++++++++++ 1 file changed, 191 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index d64985ca6e88..4694f5219654 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -584,6 +584,185 @@ static const struct camss_subdev_resources vfe_res_660[] = { } }; +static const struct camss_subdev_resources csiphy_res_670[] = { + /* CSIPHY0 */ + { + .regulators = {}, + .clock = { "soc_ahb", "cpas_ahb", + "csiphy0", "csiphy0_timer" }, + .clock_rate = { { 0 }, + { 0 }, + { 0 }, + { 19200000, 240000000, 269333333 } }, + .reg = { "csiphy0" }, + .interrupt = { "csiphy0" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + + /* CSIPHY1 */ + { + .regulators = {}, + .clock = { "soc_ahb", "cpas_ahb", + "csiphy1", "csiphy1_timer" }, + .clock_rate = { { 0 }, + { 0 }, + { 0 }, + { 19200000, 240000000, 269333333 } }, + .reg = { "csiphy1" }, + .interrupt = { "csiphy1" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + + /* CSIPHY2 */ + { + .regulators = {}, + .clock = { "soc_ahb", "cpas_ahb", + "csiphy2", "csiphy2_timer" }, + .clock_rate = { { 0 }, + { 0 }, + { 0 }, + { 19200000, 240000000, 269333333 } }, + .reg = { "csiphy2" }, + .interrupt = { "csiphy2" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + } +}; + +static const struct camss_subdev_resources csid_res_670[] = { + /* CSID0 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "cpas_ahb", "soc_ahb", "vfe0", + "vfe0_cphy_rx", "csi0" }, + .clock_rate = { { 0 }, + { 0 }, + { 100000000, 320000000, 404000000, 480000000, 600000000 }, + { 384000000 }, + { 19200000, 75000000, 384000000, 538666667 } }, + .reg = { "csid0" }, + .interrupt = { "csid0" }, + .csid = { + .hw_ops = &csid_ops_gen2, + .parent_dev_ops = &vfe_parent_dev_ops, + .formats = &csid_formats_gen2 + } + }, + + /* CSID1 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "cpas_ahb", "soc_ahb", "vfe1", + "vfe1_cphy_rx", "csi1" }, + .clock_rate = { { 0 }, + { 0 }, + { 100000000, 320000000, 404000000, 480000000, 600000000 }, + { 384000000 }, + { 19200000, 75000000, 384000000, 538666667 } }, + .reg = { "csid1" }, + .interrupt = { "csid1" }, + .csid = { + .hw_ops = &csid_ops_gen2, + .parent_dev_ops = &vfe_parent_dev_ops, + .formats = &csid_formats_gen2 + } + }, + + /* CSID2 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "cpas_ahb", "soc_ahb", "vfe_lite", + "vfe_lite_cphy_rx", "csi2" }, + .clock_rate = { { 0 }, + { 0 }, + { 100000000, 320000000, 404000000, 480000000, 600000000 }, + { 384000000 }, + { 19200000, 75000000, 384000000, 538666667 } }, + .reg = { "csid2" }, + .interrupt = { "csid2" }, + .csid = { + .is_lite = true, + .hw_ops = &csid_ops_gen2, + .parent_dev_ops = &vfe_parent_dev_ops, + .formats = &csid_formats_gen2 + } + } +}; + +static const struct camss_subdev_resources vfe_res_670[] = { + /* VFE0 */ + { + .regulators = {}, + .clock = { "camnoc_axi", "cpas_ahb", "soc_ahb", + "vfe0", "vfe0_axi" }, + .clock_rate = { { 0 }, + { 0 }, + { 0 }, + { 100000000, 320000000, 404000000, 480000000, 600000000 }, + { 0 } }, + .reg = { "vfe0" }, + .interrupt = { "vfe0" }, + .vfe = { + .line_num = 4, + .has_pd = true, + .pd_name = "ife0", + .hw_ops = &vfe_ops_170, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + + /* VFE1 */ + { + .regulators = {}, + .clock = { "camnoc_axi", "cpas_ahb", "soc_ahb", + "vfe1", "vfe1_axi" }, + .clock_rate = { { 0 }, + { 0 }, + { 0 }, + { 100000000, 320000000, 404000000, 480000000, 600000000 }, + { 0 } }, + .reg = { "vfe1" }, + .interrupt = { "vfe1" }, + .vfe = { + .line_num = 4, + .has_pd = true, + .pd_name = "ife1", + .hw_ops = &vfe_ops_170, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + + /* VFE-lite */ + { + .regulators = {}, + .clock = { "camnoc_axi", "cpas_ahb", "soc_ahb", + "vfe_lite" }, + .clock_rate = { { 0 }, + { 0 }, + { 0 }, + { 100000000, 320000000, 404000000, 480000000, 600000000 } }, + .reg = { "vfe_lite" }, + .interrupt = { "vfe_lite" }, + .vfe = { + .is_lite = true, + .line_num = 4, + .hw_ops = &vfe_ops_170, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + } +}; + static const struct camss_subdev_resources csiphy_res_845[] = { /* CSIPHY0 */ { @@ -2404,6 +2583,17 @@ static const struct camss_resources sdm660_resources = { .link_entities = camss_link_entities }; +static const struct camss_resources sdm670_resources = { + .version = CAMSS_845, + .csiphy_res = csiphy_res_670, + .csid_res = csid_res_670, + .vfe_res = vfe_res_670, + .csiphy_num = ARRAY_SIZE(csiphy_res_670), + .csid_num = ARRAY_SIZE(csid_res_670), + .vfe_num = ARRAY_SIZE(vfe_res_670), + .link_entities = camss_link_entities +}; + static const struct camss_resources sdm845_resources = { .version = CAMSS_845, .csiphy_res = csiphy_res_845, @@ -2448,6 +2638,7 @@ static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources }, { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources }, + { .compatible = "qcom,sdm670-camss", .data = &sdm670_resources }, { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources }, { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, From patchwork Fri Oct 11 02:37:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13831966 Received: from mail-qt1-f175.google.com (mail-qt1-f175.google.com [209.85.160.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31F1D1F4711; Fri, 11 Oct 2024 02:37:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728614269; cv=none; b=nEI/c2AC78wJqsHyR2bCbbqnYo3ihNZf2TUnY8UQOuaLl3MI4uKgXIYdcxwtQTcPu8kZqA7W2ZFGW+SoYHbZjU1QOKqOZu4AyeR2gTxnHenUnrn3KBCnZx++9yJCtQ0YTHwDOrRuL09CjiP/sXmj5V7UN54TT/ykgSs4ecb4itg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728614269; c=relaxed/simple; bh=iNlwMXgz1Zvrwnb4TkSSScgraViaSX1xVBcR45JKUVc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kNkq7X7dBscnW5QmQULVqUNhVOkAq7Vp0HIsMp3lIZMe8FYs8L8EofYsjP4J/mtRjuAtdxWalw2N3xXwJVBc5H7u+9jygGuNwt33JU+g9zfpr45FYkuIXRsLHS81xFLXkqr6ymqzNuE15Jrh6EMTqwoc38Ee7K+Ccw42ixdWXmM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=OBdYW4gE; arc=none smtp.client-ip=209.85.160.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OBdYW4gE" Received: by mail-qt1-f175.google.com with SMTP id d75a77b69052e-4604bd15be0so3782051cf.2; Thu, 10 Oct 2024 19:37:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1728614267; x=1729219067; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T2tZPFFU12WsBefqXT52afAbPfKPX7iOAYmOLQqEmqg=; b=OBdYW4gEZ9p7ii9WKxkDZU2h81NNsBHrpIpMCjWcukGppdOoSUou2YfO4TYM9ut17G /KotS8mKQ+GpLOEFsIU2xyKkLE0tG+rjditSSdBtlXjCp0/plLY9oiGnipyYBUeujBih jvY7606+7/9p07WeoyQSAWlV9cbq77ed6wgJqvVjAzhXAeUPjDU2vpDs6qmm95Uz+XmY dg+yusV0Fl2o0crmpNaIgb3sEDNf0LuryLnOTYU5XIiNIqwefYrLKIBKE8RsY4fTtiGD zl5wYJqOlSq0wjx7uhsnjSJmSZ1qjg6P4bvZE4DhVDzg0+Mx9zUSiW1/GkZcMU8Yw11b ifEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728614267; x=1729219067; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T2tZPFFU12WsBefqXT52afAbPfKPX7iOAYmOLQqEmqg=; b=qQGpW8RDd7rqmPkqJd7xf/S5332ZwMxz6LkZ5d0VPCSCRqLXzopJQrO4dWxSUkzUkz EZTzm2hj6orGyb8WtI/47P7yWoxb7xwJqmSJ4fdWZCnv6sYR44TIXBSZS87CMf6C25pS nbkk/Qni1IzskoiI1qzYPcIfMfBH+NsbYVVzRGAs2GixWALXRJVC1Kck1gha/7KtY4Ku dceuit7QAaTlCLUG0NAi2p6K7mCGRAHWxCYjgrvpC7KZQGKGoMti2Rr4N8L8wqt8HXRi mxmihu6uMTJjTaiAO81dX2UoiLnf6pREpX8s/KcPO+Q4w8Y8G1yI45VLHx31ZC41skDQ vgHQ== X-Forwarded-Encrypted: i=1; AJvYcCU+gsuCV1W6/YIDlBHM6fbXGSzzmsCQBniLHtP35FA3TS9AbvbACBevF6oNmRr0vEYHeLTjwaJxSjOzV30=@vger.kernel.org, AJvYcCWwcZYTAIb7got7J+lr1oBjOUHYGqLk8ld6Wu7L00MtjIXEvCnk43L1SBZEDmbAk5qu0mz2gG0FnBsN@vger.kernel.org, AJvYcCXEfq6x9eKJcfyGa6WONPsAYdXCeeTlEpwFG8EkAEl0KJ6Pn52/buSuH70sFEmOdP6qC+7V/fosRARxU0cuEA==@vger.kernel.org, AJvYcCXTcpHIrZx4KmfP9cADH0Ay4lsSvut5Z62VO+YJAoH8AVe/XgDZFtGVGKAwSte2U360kHboMKhcpbg4@vger.kernel.org X-Gm-Message-State: AOJu0YwecIse7ACf25et8CyUVx8VE9MZiIhD5aHmdQxGkrA/8UrhvDj9 N0ff6LmyGcT+TSnC0rOTajJIrqMEzb04J1vqrZp4f9qiQeXRObiV X-Google-Smtp-Source: AGHT+IEmt7dBkYdNAHIqbSi4n1ChVUetWqJRtoP96mCtNaFYz2/Ge0wJDd1t4Ed7f3Fop0Vv+NRX2A== X-Received: by 2002:a05:622a:1a82:b0:458:232d:db63 with SMTP id d75a77b69052e-4604bbbf450mr17540751cf.21.1728614267151; Thu, 10 Oct 2024 19:37:47 -0700 (PDT) Received: from localhost ([2607:fea8:52a3:d200::786d]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-46042802f65sm11295941cf.41.2024.10.10.19.37.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 19:37:46 -0700 (PDT) From: Richard Acayan To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , "Bryan O'Donoghue" , Mauro Carvalho Chehab , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-media@vger.kernel.org Cc: Vladimir Zapolskiy , Richard Acayan Subject: [PATCH v6 4/5] arm64: dts: qcom: sdm670: add camcc Date: Thu, 10 Oct 2024 22:37:29 -0400 Message-ID: <20241011023724.614584-11-mailingradian@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241011023724.614584-7-mailingradian@gmail.com> References: <20241011023724.614584-7-mailingradian@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The camera clock controller on SDM670 controls the clocks that drive the camera subsystem. The clocks are the same as on SDM845. Add the camera clock controller for SDM670. Reviewed-by: Bryan O'Donoghue Signed-off-by: Richard Acayan --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 187c6698835d..02f87200690a 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1400,6 +1400,16 @@ spmi_bus: spmi@c440000 { #interrupt-cells = <4>; }; + camcc: clock-controller@ad00000 { + compatible = "qcom,sdm670-camcc", "qcom,sdm845-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,sdm670-mdss"; reg = <0 0x0ae00000 0 0x1000>; From patchwork Fri Oct 11 02:37:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Acayan X-Patchwork-Id: 13831967 Received: from mail-qt1-f171.google.com (mail-qt1-f171.google.com [209.85.160.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 926D21EF940; Fri, 11 Oct 2024 02:37:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728614274; cv=none; b=gn4qC4cXwRnU49Qbp95C7O6igcp8vK+SsFAFbU6soRCCpNXrsKASfXH41M53tpNjhseNgRdHzBYuDSaqVRkBay+Q9j4mM/G60eiOH7dhP2SGzX91f6HtG3J5G6zlgIicbyZbR3h6dmOJrB6AkeR9HmCqNNevANqjnV8bgK5gHdQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728614274; c=relaxed/simple; bh=FjTX3XDsZpHBupi3816W2od1/AGtgYSbkC2JLrZVGvU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TXnEG+szLNW1PtOQfnVlJq/w6WHHK2PJs3wmCFO9ylUk88LWJp6GbovvYbrY+/wxddI5wneZJHoQiCpgRNSOx02xkWRQWWg6+uA5SM2+Om55026L6lmeATt4S5N+u3ZedeGLlkl4JWM5qDxemUaSpnpTrnHQML++Q6iugfe514o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=MzaBRCfX; arc=none smtp.client-ip=209.85.160.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MzaBRCfX" Received: by mail-qt1-f171.google.com with SMTP id d75a77b69052e-46041d86566so8348861cf.3; Thu, 10 Oct 2024 19:37:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1728614271; x=1729219071; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DRPUb8dk8eranWDUoNRWB5sVzMnuxcxe71W05Xb2xMM=; b=MzaBRCfXKtOTcM7dZHQJKuoPvOd2e6LFjNiMBkLdESjjl+9HWigc25iaa36LaibU8x 7ITXJ37fXeHmRtfttopJEZ1M/rBt9pPXiZHFl6TwwNbheI7S+b8FcszUXS6VvACQZ/XV xU5Ju7Au5ID2k5JIKxhvZm24nt6NHxWM5d+o5uTjGl3vHqLgzZbCiZc0TMCaePFgwdSN Fi1U99w/+ZmBRRHZ81c0OCa8xTKjSwvxo37AoZKx2eEiC55wBZbcC36AmsJpZ4Xbmow3 6uR7AtfLKdnL60I08p5Kkgf1YVXUlh+kTigts33jATbcQSyjWoOYaeWX+raPbSAeKdyJ 5u8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728614271; x=1729219071; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DRPUb8dk8eranWDUoNRWB5sVzMnuxcxe71W05Xb2xMM=; b=oX+uD0kCxJ/VUhO1IVS6H9SMuRad69338gSOJTUMDMtfuM0OgMkW8/djnFvYwWzpBI 1IsxLjCVRvHVCdZxoG/+ZCrQPtY7nHaAzByVkyz+MWK+YXrwr93iT1Sh2jlcTat+Rn3j UIWwaZRACrchhygL3e0z4ODEdiI70RMcs+oCVxXphFgVTAvPcSFikrXMt3qq0J9zEnOQ XR9dzAvKAwPANJrUZXX72nG+roIpvnRR0ej6IYpnaj5JhfGfunHRbiPRspvnf3PWTXiN SHPYyA8+KdyzeZuyQLl0SIYoCCnLjkmPtPfEwK2cinl03Fxu1FN3QIfiepcnojApr/C9 3KSw== X-Forwarded-Encrypted: i=1; AJvYcCVAE3oF5Bu6+WCBk3ax6jCUbLGEQTecdIaODcpeOA1aq3UrLMVXVxs3Ke4h87F3aWR1JxRKIqwOu04V@vger.kernel.org, AJvYcCVw4qWMH8rz/2KMwwm44u4A8N88iGnfb/YgnZ1sTwJFj01bm+YtsttOSQLj6SgjR1f6O0cVRq2bMExPqqnUaA==@vger.kernel.org, AJvYcCWT4kbI0jqmu0VbmdSN07ud3laerBCSAbdM+NiTabKwnCgedjTsiJFqxjMUBeSAQGZq1Lolz4L7+C1Mm8c=@vger.kernel.org, AJvYcCWWM59hD2nemvqEDi6E3/HZ86xJ0DJywvDQjTBNk68WG0XUJXm7kfKFhIumrEgNgPNEef69eq8oIVHZ@vger.kernel.org X-Gm-Message-State: AOJu0YxXzIFDxZSqHu3UQctImbvcVzBlQeQY6RpLXofzrxAhD3MmFEtR QpFMp7ANcBASAuc1cpAxsCvpNEwioQTogjgYO1QQSFVIXXzf8gty X-Google-Smtp-Source: AGHT+IFy+didwRP6RtchQAcwd71MpnhBpwSrQI/VBkjSGGGu+1tFA4FD0vLaNQRaNUqfDR1xDDqFBQ== X-Received: by 2002:ac8:7c48:0:b0:458:4224:c367 with SMTP id d75a77b69052e-4604bc53c68mr16821501cf.49.1728614271312; Thu, 10 Oct 2024 19:37:51 -0700 (PDT) Received: from localhost ([2607:fea8:52a3:d200::786d]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-460427d53bfsm11258731cf.29.2024.10.10.19.37.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 19:37:50 -0700 (PDT) From: Richard Acayan To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , "Bryan O'Donoghue" , Mauro Carvalho Chehab , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-media@vger.kernel.org Cc: Vladimir Zapolskiy , Richard Acayan Subject: [PATCH v6 5/5] arm64: dts: qcom: sdm670: add camss and cci Date: Thu, 10 Oct 2024 22:37:30 -0400 Message-ID: <20241011023724.614584-12-mailingradian@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241011023724.614584-7-mailingradian@gmail.com> References: <20241011023724.614584-7-mailingradian@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the camera subsystem and CCI used to interface with cameras on the Snapdragon 670. Signed-off-by: Richard Acayan Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 185 +++++++++++++++++++++++++++ 1 file changed, 185 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 02f87200690a..229d1c4eb246 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -6,6 +6,7 @@ * Copyright (c) 2022, Richard Acayan. All rights reserved. */ +#include #include #include #include @@ -1168,6 +1169,34 @@ tlmm: pinctrl@3400000 { gpio-ranges = <&tlmm 0 0 151>; wakeup-parent = <&pdc>; + cci0_default: cci0-default-state { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_sleep: cci0-sleep-state { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_default: cci1-default-state { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_sleep: cci1-sleep-state { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + qup_i2c0_default: qup-i2c0-default-state { pins = "gpio0", "gpio1"; function = "qup0"; @@ -1400,6 +1429,162 @@ spmi_bus: spmi@c440000 { #interrupt-cells = <4>; }; + cci: cci@ac4a000 { + compatible = "qcom,sdm670-cci", "qcom,msm8996-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4a000 0 0x4000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_CLK>; + clock-names = "camnoc_axi", + "soc_ahb", + "cpas_ahb", + "cci"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + camss: camera-controller@ac65000 { + compatible = "qcom,sdm670-camss"; + reg = <0 0x0acb3000 0 0x1000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0ac65000 0 0x1000>, + <0 0x0ac66000 0 0x1000>, + <0 0x0ac67000 0 0x1000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acc4000 0 0x4000>; + reg-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite"; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite"; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>; + clock-names = "gcc_camera_ahb", + "gcc_camera_axi", + "soc_ahb", + "camnoc_axi", + "cpas_ahb", + "csi0", + "csi1", + "csi2", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe_lite", + "vfe_lite_cphy_rx"; + + iommus = <&apps_smmu 0x808 0x0>, + <&apps_smmu 0x810 0x8>, + <&apps_smmu 0xc08 0x0>, + <&apps_smmu 0xc10 0x8>; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + camss_port0: port@0 { + reg = <0>; + }; + + camss_port1: port@1 { + reg = <1>; + }; + + camss_port2: port@2 { + reg = <2>; + }; + }; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sdm670-camcc", "qcom,sdm845-camcc"; reg = <0 0x0ad00000 0 0x10000>;