From patchwork Wed Oct 16 07:22:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nemesa Garg X-Patchwork-Id: 13837823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 632AAD206A5 for ; Wed, 16 Oct 2024 07:21:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 553D010E07A; Wed, 16 Oct 2024 07:21:23 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="TYLnyMWc"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 13B8710E07A for ; Wed, 16 Oct 2024 07:21:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729063281; x=1760599281; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XZ2wsoTDkX45falAqSMfHlV5+RTSS9JVybZQ3y0aggE=; b=TYLnyMWcrH5zHnFiouPQGkSh7r7q4FM+bD96HRNGwK2xQVjAaVs8okY9 UIs+t0BjsU42p628g4czqwKCzv+Pxm2Oq9o3Jk0eNo+RqTGPsT+9MQKdw /V2NZxmaWgirvJcpVl5onq3MvicJxgTTYU0OJiNDDTvA1z3d6mgc3lMyw Wn4CCD2cdi1mjZ69dwVsXuuiSKSjiHF5V0yL4jpJ3F/65+sjRU2Zv6ePM LRKoPZpz7bM4jyD0zC1kLjzmj0q4lGSQV8dJb6yXW0tk4uWvpGQj5iUdu 2aR5yIRUUSLLxoinErBjTcm4c6ry6UCy1UmaTh+gqIkcK4UlernbBtCtm Q==; X-CSE-ConnectionGUID: 0WzhrAbxQXGzSzPY/qNt/g== X-CSE-MsgGUID: P+JUi54IQpWE5OAZwQ9sDg== X-IronPort-AV: E=McAfee;i="6700,10204,11225"; a="28626418" X-IronPort-AV: E=Sophos;i="6.11,207,1725346800"; d="scan'208";a="28626418" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2024 00:21:20 -0700 X-CSE-ConnectionGUID: 5hahFd3HRF+tnpe7ydiLRg== X-CSE-MsgGUID: wL9zTP9ETJqS7rT69vrnuA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,207,1725346800"; d="scan'208";a="82921238" Received: from nemesa.iind.intel.com ([10.190.239.22]) by orviesa005.jf.intel.com with ESMTP; 16 Oct 2024 00:21:20 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH] drm/i915/display: Workaround for odd panning for planar yuv Date: Wed, 16 Oct 2024 12:52:06 +0530 Message-Id: <20241016072206.261279-1-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240930112343.2673244-1-nemesa.garg@intel.com> References: <20240930112343.2673244-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Disable the support for odd x pan for even xsize for NV12 format as underrun issue is seen. WA: 16024459452 v2: Replace HSD with WA in commit message [Suraj] Modified the condition for handling odd panning v3: Simplified the condition for checking hsub Using older framework for wa as rev1[Jani] v4: Modify the condition for hsub [Sai Teja] Initialize hsub in else path [Dan] v5: Replace IS_LUNARLAKE with display version. Resolve nitpicks[Jani] v6: Replace -EINVAL with hsub [Suraj] Remove src_w check as not required Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index e979786aa5cf..2d7ca6e62926 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -1031,6 +1031,11 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) */ hsub = 1; vsub = 1; + + /* Wa_16023981245 */ + if (DISPLAY_VER(i915) == 20 && fb->format->format == DRM_FORMAT_NV12 && + src_x % 2 != 0) + hsub = 2; } else { hsub = fb->format->hsub; vsub = fb->format->vsub;