From patchwork Wed Oct 16 12:39:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amelie Delaunay X-Patchwork-Id: 13838422 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAEA5208D7B; Wed, 16 Oct 2024 12:43:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729082597; cv=none; b=kICuf7n0Br3OjIEeInVnTzdEjgwcbrzdoF3+iwScNwWJW+bFwRt0pAOEUsEk42zi6neK3/oDb1ZEvXNvNilo/frPpxMXMAW4/m6kQHOrCORx+lnTyfjOlr8VMwq40p1GDM9/QB2S9j/AANfeXFpY1jse4UgSTjbKF+QGa6Zlkno= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729082597; c=relaxed/simple; bh=dJQWkcrhwk0Vkj1AihIMxNRLDfQsHXxazUmkVVKOLlY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=FZcO5UwC+pz/axmv0VSJO+lG5KQWQUgF42g/ZD75scrx1fnizBAsw6Smdt6ME2K9SQIpOKSHpNLhxeelPSbuYAY4x64i10I1i2F9cnoAsVqsML81tlyIOgt4n3Tce+hcsLyJCdtBBMuQ5UbtAUNNjIqEdA1Oc7y6/070/mg02yw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=ZBvnHLQO; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="ZBvnHLQO" Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49G8rQLD011450; Wed, 16 Oct 2024 14:42:52 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= 1FmGrSANQn07iSNnWCRz9WCfIaMI09hSsfRbqu2gnOU=; b=ZBvnHLQOdIBA/1cO +xTlxzQr++yJVmlpcQI4iIXtMxaBSRmxPM3B7Zqn/C78swAWLsCCQofpcp9sB62j KHoCxAulsrtOyMuQgDsOImRW6wKLCOZQt6lLF2ECBRG00U5y+fSvAvUgHXvlNxCt wqJGmAY+o0pWGT/iTQ90ADJyVYmU4vMmKaRhSA6C3iVvZj6qc5CpAe+eqRrGWPzh X2UbWHi++yTJdbm9uBT6P99PXaWtqk9FkwveJkRxMUnm7YKkFbhJAu5ZibRHvmux K0dDfKwMKxfo8UqoEQp/3qA3wYlqkG/MilGQ3ZHQRel03LQ33NXSxYm05QVDChFl 4BIFKw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 429qybdjc0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 16 Oct 2024 14:42:52 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 36BCF4004C; Wed, 16 Oct 2024 14:41:23 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id F1429239965; Wed, 16 Oct 2024 14:40:20 +0200 (CEST) Received: from localhost (10.252.17.239) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 16 Oct 2024 14:40:20 +0200 From: Amelie Delaunay Date: Wed, 16 Oct 2024 14:39:53 +0200 Subject: [PATCH v3 1/9] dt-bindings: dma: stm32-dma3: prevent packing/unpacking mode Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241016-dma3-mp25-updates-v3-1-8311fe6f228d@foss.st.com> References: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> In-Reply-To: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , Amelie Delaunay X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 When source data width/burst and destination data width/burst are different, data are packed or unpacked in DMA3 channel FIFO. Data are pushed out from DMA3 channel FIFO when the destination burst length (= data width * burst) is reached. If the channel is stopped before the transfer end, and if some bytes are packed/unpacked in the DMA3 channel FIFO, these bytes are lost. Indeed, DMA3 channel FIFO has no flush capability, only reset. To avoid potential bytes lost, pack/unpack must be prevented by setting memory data width/burst equal to peripheral data width/burst. Memory accesses will be penalized. But it is the only way to avoid bytes lost. Some devices (e.g. cyclic RX like UART) need this, so add the possibility to prevent pack/unpack feature, by setting bit 16 of the 'DMA transfer requirements' bit mask. Acked-by: Rob Herring (Arm) Signed-off-by: Amelie Delaunay --- Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml b/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml index 7fdc44b2e6467928622a5bb25d9e0c74bb1790ae..5484848735f8ac3d2050104bbab1d986e82ba6a7 100644 --- a/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml +++ b/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml @@ -96,6 +96,9 @@ properties: including the update of the LLI if any 0x3: at channel level, the transfer complete event is generated at the end of the last LLI + -bit 16: Prevent packing/unpacking mode + 0x0: pack/unpack enabled when source data width/burst != destination data width/burst + 0x1: memory data width/burst forced to peripheral data width/burst to prevent pack/unpack required: - compatible From patchwork Wed Oct 16 12:39:54 2024 Content-Type: text/plain; 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Wed, 16 Oct 2024 14:40:21 +0200 (CEST) Received: from localhost (10.252.17.239) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 16 Oct 2024 14:40:21 +0200 From: Amelie Delaunay Date: Wed, 16 Oct 2024 14:39:54 +0200 Subject: [PATCH v3 2/9] dmaengine: stm32-dma3: prevent pack/unpack thanks to DT configuration Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241016-dma3-mp25-updates-v3-2-8311fe6f228d@foss.st.com> References: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> In-Reply-To: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , Amelie Delaunay X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 When source data width/burst and destination data width/burst are different, data are packed or unpacked in DMA3 channel FIFO, using CxTR1.PAM. Data are pushed out from DMA3 channel FIFO when the destination burst length (= data width * burst) is reached. If the transfer is stopped before CxBR1.BNDT = 0, and if some bytes are packed/unpacked in the DMA3 channel FIFO, these bytes are lost. Indeed, DMA3 channel FIFO has no flush capability, only reset. To avoid potential bytes lost, pack/unpack must be prevented by setting memory data width/burst equal to peripheral data width/burst. Memory accesses will be penalized. But it is the only way to avoid bytes lost. Prevent pack/unpack feature can be activated by setting bit 16 of DMA3 Transfer requirements bitfield (tr_conf) in device tree. Signed-off-by: Amelie Delaunay --- drivers/dma/stm32/stm32-dma3.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/dma/stm32/stm32-dma3.c b/drivers/dma/stm32/stm32-dma3.c index b9470f783f98940a99addaeef6d0a8bc07b5c54b..f793eecd2c27ca17cedd5cabbaa1b1beca202039 100644 --- a/drivers/dma/stm32/stm32-dma3.c +++ b/drivers/dma/stm32/stm32-dma3.c @@ -221,6 +221,7 @@ enum stm32_dma3_port_data_width { #define STM32_DMA3_DT_BREQ BIT(8) /* CTR2_BREQ */ #define STM32_DMA3_DT_PFREQ BIT(9) /* CTR2_PFREQ */ #define STM32_DMA3_DT_TCEM GENMASK(13, 12) /* CTR2_TCEM */ +#define STM32_DMA3_DT_NOPACK BIT(16) /* CTR1_PAM */ /* struct stm32_dma3_chan .config_set bitfield */ #define STM32_DMA3_CFG_SET_DT BIT(0) @@ -622,6 +623,10 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf /* Set source (memory) data width and burst */ sdw = stm32_dma3_get_max_dw(chan->max_burst, sap_max_dw, len, src_addr); sbl_max = stm32_dma3_get_max_burst(len, sdw, chan->max_burst); + if (!!FIELD_GET(STM32_DMA3_DT_NOPACK, tr_conf)) { + sdw = ddw; + sbl_max = dbl_max; + } _ctr1 |= FIELD_PREP(CTR1_SDW_LOG2, ilog2(sdw)); _ctr1 |= FIELD_PREP(CTR1_SBL_1, sbl_max - 1); @@ -652,6 +657,11 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf /* Set destination (memory) data width and burst */ ddw = stm32_dma3_get_max_dw(chan->max_burst, dap_max_dw, len, dst_addr); dbl_max = stm32_dma3_get_max_burst(len, ddw, chan->max_burst); + if (!!FIELD_GET(STM32_DMA3_DT_NOPACK, tr_conf) || + ((_ctr2 & CTR2_PFREQ) && ddw > sdw)) { /* Packing to wider ddw not supported */ + ddw = sdw; + dbl_max = sbl_max; + } _ctr1 |= FIELD_PREP(CTR1_SDW_LOG2, ilog2(sdw)); _ctr1 |= FIELD_PREP(CTR1_SBL_1, sbl_max - 1); From patchwork Wed Oct 16 12:39:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amelie Delaunay X-Patchwork-Id: 13838419 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93DF341C69; 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Wed, 16 Oct 2024 14:42:43 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 6A18040044; Wed, 16 Oct 2024 14:41:22 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9349123CB3E; Wed, 16 Oct 2024 14:40:22 +0200 (CEST) Received: from localhost (10.252.17.239) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 16 Oct 2024 14:40:22 +0200 From: Amelie Delaunay Date: Wed, 16 Oct 2024 14:39:55 +0200 Subject: [PATCH v3 3/9] dmaengine: stm32-dma3: refactor HW linked-list to optimize memory accesses Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241016-dma3-mp25-updates-v3-3-8311fe6f228d@foss.st.com> References: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> In-Reply-To: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , Amelie Delaunay X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Current behavior splits the buffer/sg in n * STM32_DMA3_MAX_BLOCK_SIZE + 1 for the remainder without optimization. New behavior splits the buffer/sg in n * STM32_DMA3_MAX_BLOCK_SIZE + 1 for (x * chan->max_burst) + 1 for the remainder. Depending on channel FIFO size, optimal double-word (word if only 8-byte FIFO size) bursts can be programmed before managing the very last remainder with lower data width. In case of _prep_slave_sg, and depending on the channel Transfer Complete event configuration, the user is warned about the refactored linked-list, not having the same items count than the initial sg_list. This warning is shown only if the configuration is successful. Signed-off-by: Amelie Delaunay --- drivers/dma/stm32/stm32-dma3.c | 40 +++++++++++++++++++++++++++++++++------- 1 file changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/dma/stm32/stm32-dma3.c b/drivers/dma/stm32/stm32-dma3.c index f793eecd2c27ca17cedd5cabbaa1b1beca202039..1d961f5935f935e3855467318cdcde6e6173e43c 100644 --- a/drivers/dma/stm32/stm32-dma3.c +++ b/drivers/dma/stm32/stm32-dma3.c @@ -1126,6 +1126,25 @@ static void stm32_dma3_free_chan_resources(struct dma_chan *c) chan->config_set = 0; } +static u32 stm32_dma3_get_ll_count(struct stm32_dma3_chan *chan, size_t len) +{ + u32 count; + + count = len / STM32_DMA3_MAX_BLOCK_SIZE; + len -= (len / STM32_DMA3_MAX_BLOCK_SIZE) * STM32_DMA3_MAX_BLOCK_SIZE; + + if (len >= chan->max_burst) { + count += 1; /* len < STM32_DMA3_MAX_BLOCK_SIZE here, so it fits in one item */ + len -= (len / chan->max_burst) * chan->max_burst; + } + + /* Unaligned remainder fits in one extra item */ + if (len > 0) + count += 1; + + return count; +} + static void stm32_dma3_init_chan_config_for_memcpy(struct stm32_dma3_chan *chan, dma_addr_t dst, dma_addr_t src) { @@ -1161,7 +1180,7 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_dma_memcpy(struct dma_cha size_t next_size, offset; u32 count, i, ctr1, ctr2; - count = DIV_ROUND_UP(len, STM32_DMA3_MAX_BLOCK_SIZE); + count = stm32_dma3_get_ll_count(chan, len); swdesc = stm32_dma3_chan_desc_alloc(chan, count); if (!swdesc) @@ -1177,6 +1196,9 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_dma_memcpy(struct dma_cha remaining = len - offset; next_size = min_t(size_t, remaining, STM32_DMA3_MAX_BLOCK_SIZE); + if (next_size < STM32_DMA3_MAX_BLOCK_SIZE && next_size >= chan->max_burst) + next_size = chan->max_burst * (remaining / chan->max_burst); + ret = stm32_dma3_chan_prep_hw(chan, DMA_MEM_TO_MEM, &swdesc->ccr, &ctr1, &ctr2, src + offset, dst + offset, next_size); if (ret) @@ -1215,12 +1237,9 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_slave_sg(struct dma_chan u32 i, j, count, ctr1, ctr2; int ret; - count = sg_len; - for_each_sg(sgl, sg, sg_len, i) { - len = sg_dma_len(sg); - if (len > STM32_DMA3_MAX_BLOCK_SIZE) - count += DIV_ROUND_UP(len, STM32_DMA3_MAX_BLOCK_SIZE) - 1; - } + count = 0; + for_each_sg(sgl, sg, sg_len, i) + count += stm32_dma3_get_ll_count(chan, sg_dma_len(sg)); swdesc = stm32_dma3_chan_desc_alloc(chan, count); if (!swdesc) @@ -1237,6 +1256,9 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_slave_sg(struct dma_chan do { size_t chunk = min_t(size_t, len, STM32_DMA3_MAX_BLOCK_SIZE); + if (chunk < STM32_DMA3_MAX_BLOCK_SIZE && chunk >= chan->max_burst) + chunk = chan->max_burst * (len / chan->max_burst); + if (dir == DMA_MEM_TO_DEV) { src = sg_addr; dst = dev_addr; @@ -1269,6 +1291,10 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_slave_sg(struct dma_chan } while (len); } + if (count != sg_len && chan->tcem != CTR2_TCEM_CHANNEL) + dev_warn(chan2dev(chan), "Linked-list refactored, %d items instead of %d\n", + count, sg_len); + /* Enable Error interrupts */ swdesc->ccr |= CCR_USEIE | CCR_ULEIE | CCR_DTEIE; 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Wed, 16 Oct 2024 14:41:24 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 572F123CB4E; Wed, 16 Oct 2024 14:40:23 +0200 (CEST) Received: from localhost (10.252.17.239) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 16 Oct 2024 14:40:23 +0200 From: Amelie Delaunay Date: Wed, 16 Oct 2024 14:39:56 +0200 Subject: [PATCH v3 4/9] dt-bindings: dma: stm32-dma3: prevent additional transfers Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241016-dma3-mp25-updates-v3-4-8311fe6f228d@foss.st.com> References: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> In-Reply-To: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , Amelie Delaunay X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Some devices require a single transfer. For example, reading FMC ECC status registers does not support multiple transfers. Add the possibility to prevent additional transfers, by setting bit 17 of the 'DMA transfer requirements' bit mask. Signed-off-by: Amelie Delaunay Reviewed-by: Rob Herring (Arm) --- Changes in v3: - Refine commit description as per Rob's suggestion. Changes in v2: - Reword commit title/message/content as per Rob's suggestion. --- Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml b/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml index 5484848735f8ac3d2050104bbab1d986e82ba6a7..36f9fe860eb990e6caccedd31460ee6993772a35 100644 --- a/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml +++ b/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml @@ -99,6 +99,9 @@ properties: -bit 16: Prevent packing/unpacking mode 0x0: pack/unpack enabled when source data width/burst != destination data width/burst 0x1: memory data width/burst forced to peripheral data width/burst to prevent pack/unpack + -bit 17: Prevent additional transfers due to linked-list refactoring + 0x0: don't prevent additional transfers for optimal performance + 0x1: prevent additional transfer to accommodate user constraints such as single transfer required: - compatible From patchwork Wed Oct 16 12:39:57 2024 Content-Type: text/plain; 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Wed, 16 Oct 2024 14:40:24 +0200 (CEST) Received: from localhost (10.252.17.239) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 16 Oct 2024 14:40:23 +0200 From: Amelie Delaunay Date: Wed, 16 Oct 2024 14:39:57 +0200 Subject: [PATCH v3 5/9] dmaengine: stm32-dma3: prevent LL refactoring thanks to DT configuration Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241016-dma3-mp25-updates-v3-5-8311fe6f228d@foss.st.com> References: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> In-Reply-To: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , Amelie Delaunay X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 stm32-dma3 driver refactors the linked-list in order to address the memory with the highest possible data width. It means that it can introduce up to 2 linked-list items. One with a transfer length multiple of channel maximum burst length and so with the highest possible data width. And an extra one with the latest bytes, with lower data width. Some devices (e.g. FMC ECC) don't support having several transfers instead of only one. So add the possibility to prevent linked-list refactoring, when bit 17 of the 'DMA transfer requirements' bit mask is set in device tree. When NOPACK feature is used (bit 16 pf the 'DMA transfer requirements' bit mask in device tree), linked-list refactoring can be avoided, since the memory data width and burst will be aligned with the device ones. Signed-off-by: Amelie Delaunay --- drivers/dma/stm32/stm32-dma3.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/dma/stm32/stm32-dma3.c b/drivers/dma/stm32/stm32-dma3.c index 1d961f5935f935e3855467318cdcde6e6173e43c..fc874fec729df733fd8a6b4362fe1a937e9443c7 100644 --- a/drivers/dma/stm32/stm32-dma3.c +++ b/drivers/dma/stm32/stm32-dma3.c @@ -222,6 +222,7 @@ enum stm32_dma3_port_data_width { #define STM32_DMA3_DT_PFREQ BIT(9) /* CTR2_PFREQ */ #define STM32_DMA3_DT_TCEM GENMASK(13, 12) /* CTR2_TCEM */ #define STM32_DMA3_DT_NOPACK BIT(16) /* CTR1_PAM */ +#define STM32_DMA3_DT_NOREFACT BIT(17) /* struct stm32_dma3_chan .config_set bitfield */ #define STM32_DMA3_CFG_SET_DT BIT(0) @@ -1126,10 +1127,13 @@ static void stm32_dma3_free_chan_resources(struct dma_chan *c) chan->config_set = 0; } -static u32 stm32_dma3_get_ll_count(struct stm32_dma3_chan *chan, size_t len) +static u32 stm32_dma3_get_ll_count(struct stm32_dma3_chan *chan, size_t len, bool prevent_refactor) { u32 count; + if (prevent_refactor) + return DIV_ROUND_UP(len, STM32_DMA3_MAX_BLOCK_SIZE); + count = len / STM32_DMA3_MAX_BLOCK_SIZE; len -= (len / STM32_DMA3_MAX_BLOCK_SIZE) * STM32_DMA3_MAX_BLOCK_SIZE; @@ -1179,8 +1183,10 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_dma_memcpy(struct dma_cha struct stm32_dma3_swdesc *swdesc; size_t next_size, offset; u32 count, i, ctr1, ctr2; + bool prevent_refactor = !!FIELD_GET(STM32_DMA3_DT_NOPACK, chan->dt_config.tr_conf) || + !!FIELD_GET(STM32_DMA3_DT_NOREFACT, chan->dt_config.tr_conf); - count = stm32_dma3_get_ll_count(chan, len); + count = stm32_dma3_get_ll_count(chan, len, prevent_refactor); swdesc = stm32_dma3_chan_desc_alloc(chan, count); if (!swdesc) @@ -1196,7 +1202,8 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_dma_memcpy(struct dma_cha remaining = len - offset; next_size = min_t(size_t, remaining, STM32_DMA3_MAX_BLOCK_SIZE); - if (next_size < STM32_DMA3_MAX_BLOCK_SIZE && next_size >= chan->max_burst) + if (!prevent_refactor && + (next_size < STM32_DMA3_MAX_BLOCK_SIZE && next_size >= chan->max_burst)) next_size = chan->max_burst * (remaining / chan->max_burst); ret = stm32_dma3_chan_prep_hw(chan, DMA_MEM_TO_MEM, &swdesc->ccr, &ctr1, &ctr2, @@ -1235,11 +1242,13 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_slave_sg(struct dma_chan size_t len; dma_addr_t sg_addr, dev_addr, src, dst; u32 i, j, count, ctr1, ctr2; + bool prevent_refactor = !!FIELD_GET(STM32_DMA3_DT_NOPACK, chan->dt_config.tr_conf) || + !!FIELD_GET(STM32_DMA3_DT_NOREFACT, chan->dt_config.tr_conf); int ret; count = 0; for_each_sg(sgl, sg, sg_len, i) - count += stm32_dma3_get_ll_count(chan, sg_dma_len(sg)); + count += stm32_dma3_get_ll_count(chan, sg_dma_len(sg), prevent_refactor); swdesc = stm32_dma3_chan_desc_alloc(chan, count); if (!swdesc) @@ -1256,7 +1265,8 @@ static struct dma_async_tx_descriptor *stm32_dma3_prep_slave_sg(struct dma_chan do { size_t chunk = min_t(size_t, len, STM32_DMA3_MAX_BLOCK_SIZE); - if (chunk < STM32_DMA3_MAX_BLOCK_SIZE && chunk >= chan->max_burst) + if (!prevent_refactor && + (chunk < STM32_DMA3_MAX_BLOCK_SIZE && chunk >= chan->max_burst)) chunk = chan->max_burst * (len / chan->max_burst); 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Wed, 16 Oct 2024 14:41:24 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id EAD9F23CB5B; Wed, 16 Oct 2024 14:40:24 +0200 (CEST) Received: from localhost (10.252.17.239) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 16 Oct 2024 14:40:24 +0200 From: Amelie Delaunay Date: Wed, 16 Oct 2024 14:39:58 +0200 Subject: [PATCH v3 6/9] dmaengine: stm32-dma3: clamp AXI burst using match data Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241016-dma3-mp25-updates-v3-6-8311fe6f228d@foss.st.com> References: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> In-Reply-To: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , Amelie Delaunay X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 STM32 DMA3 can be interconnected with AXI3 or AXI4 busses. In case it is interconnected with AXI3, the maximum burst length supported by AXI3 protocol is 16 beats, which is lower than the maximum burst length supported by STM32 DMA3. So the programmed burst has to be shortened when AXI port is used. Introduce struct stm32_dma3_pdata to specify the specific configurations (e.g. AXI maximum burst length) required by the SoC, so implied by the SoC specific compatible. Signed-off-by: Amelie Delaunay --- Changes in v2: - Rework AXI maximum burst length management using SoC specific compatible instead of st,axi-max-burst-len DT property, as pointed out by Rob. --- drivers/dma/stm32/stm32-dma3.c | 59 ++++++++++++++++++++++++++++++++---------- 1 file changed, 46 insertions(+), 13 deletions(-) diff --git a/drivers/dma/stm32/stm32-dma3.c b/drivers/dma/stm32/stm32-dma3.c index fc874fec729df733fd8a6b4362fe1a937e9443c7..0c6c4258b19561c94f1c68f26ade16b82660ebe6 100644 --- a/drivers/dma/stm32/stm32-dma3.c +++ b/drivers/dma/stm32/stm32-dma3.c @@ -230,6 +230,8 @@ enum stm32_dma3_port_data_width { #define STM32_DMA3_CFG_SET_BOTH (STM32_DMA3_CFG_SET_DT | STM32_DMA3_CFG_SET_DMA) #define STM32_DMA3_MAX_BLOCK_SIZE ALIGN_DOWN(CBR1_BNDT, 64) +#define STM32_DMA3_MAX_BURST_LEN (1 + min_t(u32, FIELD_MAX(CTR1_SBL_1), \ + FIELD_MAX(CTR1_DBL_1))) #define port_is_ahb(maxdw) ({ typeof(maxdw) (_maxdw) = (maxdw); \ ((_maxdw) != DW_INVALID) && ((_maxdw) == DW_32); }) #define port_is_axi(maxdw) ({ typeof(maxdw) (_maxdw) = (maxdw); \ @@ -295,6 +297,10 @@ struct stm32_dma3_chan { u32 dma_status; }; +struct stm32_dma3_pdata { + u32 axi_max_burst_len; +}; + struct stm32_dma3_ddata { struct dma_device dma_dev; void __iomem *base; @@ -303,6 +309,7 @@ struct stm32_dma3_ddata { u32 dma_channels; u32 dma_requests; enum stm32_dma3_port_data_width ports_max_dw[2]; + u32 axi_max_burst_len; }; static inline struct stm32_dma3_ddata *to_stm32_dma3_ddata(struct stm32_dma3_chan *chan) @@ -535,7 +542,8 @@ static enum dma_slave_buswidth stm32_dma3_get_max_dw(u32 chan_max_burst, return 1 << __ffs(len | addr | max_dw); } -static u32 stm32_dma3_get_max_burst(u32 len, enum dma_slave_buswidth dw, u32 chan_max_burst) +static u32 stm32_dma3_get_max_burst(u32 len, enum dma_slave_buswidth dw, + u32 chan_max_burst, u32 bus_max_burst) { u32 max_burst = chan_max_burst ? chan_max_burst / dw : 1; @@ -546,8 +554,9 @@ static u32 stm32_dma3_get_max_burst(u32 len, enum dma_slave_buswidth dw, u32 cha /* * HW doesn't modify the burst if burst size <= half of the fifo size. * If len is not a multiple of burst size, last burst is shortened by HW. + * Take care of maximum burst supported on interconnect bus. */ - return max_burst; + return min_t(u32, max_burst, bus_max_burst); } static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transfer_direction dir, @@ -556,6 +565,7 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf { struct stm32_dma3_ddata *ddata = to_stm32_dma3_ddata(chan); struct dma_device dma_device = ddata->dma_dev; + u32 src_max_burst = STM32_DMA3_MAX_BURST_LEN, dst_max_burst = STM32_DMA3_MAX_BURST_LEN; u32 sdw, ddw, sbl_max, dbl_max, tcem, init_dw, init_bl_max; u32 _ctr1 = 0, _ctr2 = 0; u32 ch_conf = chan->dt_config.ch_conf; @@ -596,10 +606,14 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf _ctr1 |= CTR1_SINC; if (sap) _ctr1 |= CTR1_SAP; + if (port_is_axi(sap_max_dw)) /* AXI - apply axi maximum burst limitation */ + src_max_burst = ddata->axi_max_burst_len; if (FIELD_GET(STM32_DMA3_DT_DINC, tr_conf)) _ctr1 |= CTR1_DINC; if (dap) _ctr1 |= CTR1_DAP; + if (port_is_axi(dap_max_dw)) /* AXI - apply axi maximum burst limitation */ + dst_max_burst = ddata->axi_max_burst_len; _ctr2 |= FIELD_PREP(CTR2_REQSEL, chan->dt_config.req_line) & ~CTR2_SWREQ; if (FIELD_GET(STM32_DMA3_DT_BREQ, tr_conf)) @@ -619,11 +633,12 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf /* Set destination (device) data width and burst */ ddw = min_t(u32, ddw, stm32_dma3_get_max_dw(chan->max_burst, dap_max_dw, len, dst_addr)); - dbl_max = min_t(u32, dbl_max, stm32_dma3_get_max_burst(len, ddw, chan->max_burst)); + dbl_max = min_t(u32, dbl_max, stm32_dma3_get_max_burst(len, ddw, chan->max_burst, + dst_max_burst)); /* Set source (memory) data width and burst */ sdw = stm32_dma3_get_max_dw(chan->max_burst, sap_max_dw, len, src_addr); - sbl_max = stm32_dma3_get_max_burst(len, sdw, chan->max_burst); + sbl_max = stm32_dma3_get_max_burst(len, sdw, chan->max_burst, src_max_burst); if (!!FIELD_GET(STM32_DMA3_DT_NOPACK, tr_conf)) { sdw = ddw; sbl_max = dbl_max; @@ -653,11 +668,12 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf /* Set source (device) data width and burst */ sdw = min_t(u32, sdw, stm32_dma3_get_max_dw(chan->max_burst, sap_max_dw, len, src_addr)); - sbl_max = min_t(u32, sbl_max, stm32_dma3_get_max_burst(len, sdw, chan->max_burst)); + sbl_max = min_t(u32, sbl_max, stm32_dma3_get_max_burst(len, sdw, chan->max_burst, + src_max_burst)); /* Set destination (memory) data width and burst */ ddw = stm32_dma3_get_max_dw(chan->max_burst, dap_max_dw, len, dst_addr); - dbl_max = stm32_dma3_get_max_burst(len, ddw, chan->max_burst); + dbl_max = stm32_dma3_get_max_burst(len, ddw, chan->max_burst, dst_max_burst); if (!!FIELD_GET(STM32_DMA3_DT_NOPACK, tr_conf) || ((_ctr2 & CTR2_PFREQ) && ddw > sdw)) { /* Packing to wider ddw not supported */ ddw = sdw; @@ -689,22 +705,24 @@ static int stm32_dma3_chan_prep_hw(struct stm32_dma3_chan *chan, enum dma_transf init_dw = sdw; init_bl_max = sbl_max; sdw = stm32_dma3_get_max_dw(chan->max_burst, sap_max_dw, len, src_addr); - sbl_max = stm32_dma3_get_max_burst(len, sdw, chan->max_burst); + sbl_max = stm32_dma3_get_max_burst(len, sdw, chan->max_burst, src_max_burst); if (chan->config_set & STM32_DMA3_CFG_SET_DMA) { sdw = min_t(u32, init_dw, sdw); - sbl_max = min_t(u32, init_bl_max, - stm32_dma3_get_max_burst(len, sdw, chan->max_burst)); + sbl_max = min_t(u32, init_bl_max, stm32_dma3_get_max_burst(len, sdw, + chan->max_burst, + src_max_burst)); } /* Set destination (memory) data width and burst */ init_dw = ddw; init_bl_max = dbl_max; ddw = stm32_dma3_get_max_dw(chan->max_burst, dap_max_dw, len, dst_addr); - dbl_max = stm32_dma3_get_max_burst(len, ddw, chan->max_burst); + dbl_max = stm32_dma3_get_max_burst(len, ddw, chan->max_burst, dst_max_burst); if (chan->config_set & STM32_DMA3_CFG_SET_DMA) { ddw = min_t(u32, init_dw, ddw); - dbl_max = min_t(u32, init_bl_max, - stm32_dma3_get_max_burst(len, ddw, chan->max_burst)); + dbl_max = min_t(u32, init_bl_max, stm32_dma3_get_max_burst(len, ddw, + chan->max_burst, + dst_max_burst)); } _ctr1 |= FIELD_PREP(CTR1_SDW_LOG2, ilog2(sdw)); @@ -1647,8 +1665,12 @@ static u32 stm32_dma3_check_rif(struct stm32_dma3_ddata *ddata) return chan_reserved; } +static struct stm32_dma3_pdata stm32mp25_pdata = { + .axi_max_burst_len = 16, +}; + static const struct of_device_id stm32_dma3_of_match[] = { - { .compatible = "st,stm32mp25-dma3", }, + { .compatible = "st,stm32mp25-dma3", .data = &stm32mp25_pdata, }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, stm32_dma3_of_match); @@ -1656,6 +1678,7 @@ MODULE_DEVICE_TABLE(of, stm32_dma3_of_match); static int stm32_dma3_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; + const struct stm32_dma3_pdata *pdata; struct stm32_dma3_ddata *ddata; struct reset_control *reset; struct stm32_dma3_chan *chan; @@ -1750,6 +1773,16 @@ static int stm32_dma3_probe(struct platform_device *pdev) else /* Dual master ports */ ddata->ports_max_dw[1] = FIELD_GET(G_M1_DATA_WIDTH_ENC, hwcfgr); + /* axi_max_burst_len is optional, if not defined, use STM32_DMA3_MAX_BURST_LEN */ + ddata->axi_max_burst_len = STM32_DMA3_MAX_BURST_LEN; + pdata = device_get_match_data(&pdev->dev); + if (pdata && pdata->axi_max_burst_len) { + ddata->axi_max_burst_len = min_t(u32, pdata->axi_max_burst_len, + STM32_DMA3_MAX_BURST_LEN); + dev_dbg(&pdev->dev, "Burst is limited to %u beats through AXI port\n", + ddata->axi_max_burst_len); + } + ddata->chans = devm_kcalloc(&pdev->dev, ddata->dma_channels, sizeof(*ddata->chans), GFP_KERNEL); if (!ddata->chans) { From patchwork Wed Oct 16 12:39:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amelie Delaunay X-Patchwork-Id: 13838427 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 113D620C03D; Wed, 16 Oct 2024 12:43:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729082599; cv=none; b=OdOovaaH6avIZHTAiBOmcntquAHO5I86RBnDnkLnxNj07n7xPjDgf3P3oxRjFiwC2Cu30llircpjtmeh4SCVkcbvxkS3slKyvVvY6PVfKHiUaAFXHALFysbBbi46i13q5gD21KuymynnAh+9ak8QrcSm8WecVv7b8xaG/zyas2c= ARC-Message-Signature: i=1; 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Wed, 16 Oct 2024 14:41:25 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B282723CEB3; Wed, 16 Oct 2024 14:40:25 +0200 (CEST) Received: from localhost (10.252.17.239) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 16 Oct 2024 14:40:25 +0200 From: Amelie Delaunay Date: Wed, 16 Oct 2024 14:39:59 +0200 Subject: [PATCH v3 7/9] arm64: dts: st: add DMA support on U(S)ART instances of stm32mp25 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241016-dma3-mp25-updates-v3-7-8311fe6f228d@foss.st.com> References: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> In-Reply-To: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , Amelie Delaunay X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Add dmas and dma-names properties in u(s)art nodes of stm32mp251.dtsi to enable DMA support. RX channel requires to prevent pack/unpack feature of DMA to avoid losing bytes when interrupting RX transfer, as it uses a cyclic buffer. Signed-off-by: Amelie Delaunay --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 27 +++++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 2 ++ 2 files changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 1167cf63d7e87aaa15c5c1ed70a9f6511fd818d4..9035fc7ba4857ca98a1a86246d7d0250196b2a13 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -266,6 +266,9 @@ usart2: serial@400e0000 { reg = <0x400e0000 0x400>; interrupts = ; clocks = <&rcc CK_KER_USART2>; + dmas = <&hpdma 11 0x20 0x10012>, + <&hpdma 12 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 32>; status = "disabled"; }; @@ -275,6 +278,9 @@ usart3: serial@400f0000 { reg = <0x400f0000 0x400>; interrupts = ; clocks = <&rcc CK_KER_USART3>; + dmas = <&hpdma 13 0x20 0x10012>, + <&hpdma 14 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 33>; status = "disabled"; }; @@ -284,6 +290,9 @@ uart4: serial@40100000 { reg = <0x40100000 0x400>; interrupts = ; clocks = <&rcc CK_KER_UART4>; + dmas = <&hpdma 15 0x20 0x10012>, + <&hpdma 16 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 34>; status = "disabled"; }; @@ -293,6 +302,9 @@ uart5: serial@40110000 { reg = <0x40110000 0x400>; interrupts = ; clocks = <&rcc CK_KER_UART5>; + dmas = <&hpdma 17 0x20 0x10012>, + <&hpdma 18 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 35>; status = "disabled"; }; @@ -393,6 +405,9 @@ usart6: serial@40220000 { reg = <0x40220000 0x400>; interrupts = ; clocks = <&rcc CK_KER_USART6>; + dmas = <&hpdma 19 0x20 0x10012>, + <&hpdma 20 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 36>; status = "disabled"; }; @@ -438,6 +453,9 @@ uart9: serial@402c0000 { reg = <0x402c0000 0x400>; interrupts = ; clocks = <&rcc CK_KER_UART9>; + dmas = <&hpdma 25 0x20 0x10012>, + <&hpdma 26 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 39>; status = "disabled"; }; @@ -447,6 +465,9 @@ usart1: serial@40330000 { reg = <0x40330000 0x400>; interrupts = ; clocks = <&rcc CK_KER_USART1>; + dmas = <&hpdma 9 0x20 0x10012>, + <&hpdma 10 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 31>; status = "disabled"; }; @@ -480,6 +501,9 @@ uart7: serial@40370000 { reg = <0x40370000 0x400>; interrupts = ; clocks = <&rcc CK_KER_UART7>; + dmas = <&hpdma 21 0x20 0x10012>, + <&hpdma 22 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 37>; status = "disabled"; }; @@ -489,6 +513,9 @@ uart8: serial@40380000 { reg = <0x40380000 0x400>; interrupts = ; clocks = <&rcc CK_KER_UART8>; + dmas = <&hpdma 23 0x20 0x10012>, + <&hpdma 24 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 38>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 214191a8322b81e7ae453503863b4465d9b625e0..d468dcbe849680de812a0ddd593f30cbf507f645 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -157,6 +157,8 @@ &usart2 { pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_idle_pins_a>; pinctrl-2 = <&usart2_sleep_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; From patchwork Wed Oct 16 12:40:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amelie Delaunay X-Patchwork-Id: 13838418 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93E5320821B; Wed, 16 Oct 2024 12:43:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729082596; cv=none; b=fK7ZgnlGVptIwHJTh8k4LrdF8A0NoOnJn7Mc0BLnUpYh9S8bvhgDvBCwjM5Umh2HNYwqDUSGNzudkj/ZuOGm/ygp3vY6fH1k2gcxqxRIcQSTFNQ3tKiGk6aCNuJpLmxqPPc50E/mWU2WGNFxOBND8oDCqwwIuzKqg73YK5B8a6E= ARC-Message-Signature: i=1; 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Signed-off-by: Amelie Delaunay --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 9035fc7ba4857ca98a1a86246d7d0250196b2a13..e166e2f1f1400faf7fb56ed07c5779c26cf80cdd 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -318,6 +318,9 @@ i2c1: i2c@40120000 { resets = <&rcc I2C1_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&hpdma 27 0x20 0x3012>, + <&hpdma 28 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 41>; status = "disabled"; }; @@ -331,6 +334,9 @@ i2c2: i2c@40130000 { resets = <&rcc I2C2_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&hpdma 30 0x20 0x3012>, + <&hpdma 31 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 42>; status = "disabled"; }; @@ -344,6 +350,9 @@ i2c3: i2c@40140000 { resets = <&rcc I2C3_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&hpdma 33 0x20 0x3012>, + <&hpdma 34 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 43>; status = "disabled"; }; @@ -357,6 +366,9 @@ i2c4: i2c@40150000 { resets = <&rcc I2C4_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&hpdma 36 0x20 0x3012>, + <&hpdma 37 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 44>; status = "disabled"; }; @@ -370,6 +382,9 @@ i2c5: i2c@40160000 { resets = <&rcc I2C5_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&hpdma 39 0x20 0x3012>, + <&hpdma 40 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 45>; status = "disabled"; }; @@ -383,6 +398,9 @@ i2c6: i2c@40170000 { resets = <&rcc I2C6_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&hpdma 42 0x20 0x3012>, + <&hpdma 43 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 46>; status = "disabled"; }; @@ -396,6 +414,9 @@ i2c7: i2c@40180000 { resets = <&rcc I2C7_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&hpdma 45 0x20 0x3012>, + <&hpdma 46 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 47>; status = "disabled"; }; @@ -541,6 +562,9 @@ i2c8: i2c@46040000 { resets = <&rcc I2C8_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&hpdma 168 0x20 0x3012>, + <&hpdma 169 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 48>; status = "disabled"; }; From patchwork Wed Oct 16 12:40:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amelie Delaunay X-Patchwork-Id: 13838423 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93EBA208D63; Wed, 16 Oct 2024 12:43:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; 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Wed, 16 Oct 2024 14:42:52 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 690A44004F; Wed, 16 Oct 2024 14:41:28 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4BC5323D403; Wed, 16 Oct 2024 14:40:27 +0200 (CEST) Received: from localhost (10.252.17.239) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Wed, 16 Oct 2024 14:40:27 +0200 From: Amelie Delaunay Date: Wed, 16 Oct 2024 14:40:01 +0200 Subject: [PATCH v3 9/9] arm64: dts: st: add DMA support on SPI instances of stm32mp25 Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241016-dma3-mp25-updates-v3-9-8311fe6f228d@foss.st.com> References: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> In-Reply-To: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , Amelie Delaunay X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Add dmas and dma-names properties in spi nodes of stm32mp251.dtsi to enable DMA support. Signed-off-by: Amelie Delaunay --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index e166e2f1f1400faf7fb56ed07c5779c26cf80cdd..ed1d778ab441be3ebf2e53dea9fef484d41ab31a 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -245,6 +245,9 @@ spi2: spi@400b0000 { interrupts = ; clocks = <&rcc CK_KER_SPI2>; resets = <&rcc SPI2_R>; + dmas = <&hpdma 51 0x20 0x3012>, + <&hpdma 52 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 23>; status = "disabled"; }; @@ -257,6 +260,9 @@ spi3: spi@400c0000 { interrupts = ; clocks = <&rcc CK_KER_SPI3>; resets = <&rcc SPI3_R>; + dmas = <&hpdma 53 0x20 0x3012>, + <&hpdma 54 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 24>; status = "disabled"; }; @@ -441,6 +447,9 @@ spi1: spi@40230000 { interrupts = ; clocks = <&rcc CK_KER_SPI1>; resets = <&rcc SPI1_R>; + dmas = <&hpdma 49 0x20 0x3012>, + <&hpdma 50 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 22>; status = "disabled"; }; @@ -453,6 +462,9 @@ spi4: spi@40240000 { interrupts = ; clocks = <&rcc CK_KER_SPI4>; resets = <&rcc SPI4_R>; + dmas = <&hpdma 55 0x20 0x3012>, + <&hpdma 56 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 25>; status = "disabled"; }; @@ -465,6 +477,9 @@ spi5: spi@40280000 { interrupts = ; clocks = <&rcc CK_KER_SPI5>; resets = <&rcc SPI5_R>; + dmas = <&hpdma 57 0x20 0x3012>, + <&hpdma 58 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 26>; status = "disabled"; }; @@ -501,6 +516,9 @@ spi6: spi@40350000 { interrupts = ; clocks = <&rcc CK_KER_SPI6>; resets = <&rcc SPI6_R>; + dmas = <&hpdma 59 0x20 0x3012>, + <&hpdma 60 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 27>; status = "disabled"; }; @@ -513,6 +531,9 @@ spi7: spi@40360000 { interrupts = ; clocks = <&rcc CK_KER_SPI7>; resets = <&rcc SPI7_R>; + dmas = <&hpdma 61 0x20 0x3012>, + <&hpdma 62 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 28>; status = "disabled"; }; @@ -549,6 +570,9 @@ spi8: spi@46020000 { interrupts = ; clocks = <&rcc CK_KER_SPI8>; resets = <&rcc SPI8_R>; + dmas = <&hpdma 171 0x20 0x3012>, + <&hpdma 172 0x20 0x3021>; + dma-names = "rx", "tx"; access-controllers = <&rifsc 29>; status = "disabled"; };