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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Tariq Toukan Subject: [PATCH net-next V3 01/15] net/mlx5: Refactor QoS group scheduling element creation Date: Wed, 16 Oct 2024 20:36:03 +0300 Message-ID: <20241016173617.217736-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004685:EE_|CH2PR12MB4199:EE_ X-MS-Office365-Filtering-Correlation-Id: 01af8ba3-4d9a-495c-ddba-08dcee09314b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: 0QrlJBHxv62I1IqXKNLewVYgBoQz3vDSYnlhCnPwnN00f1YQNA7mZIFs61qiSSAw4jwFtTdiJ2wbrLl4NNQKWz1RGAHv8z4/6LXEHOV1QCh/z6sDLIOzqrvlaopGV4jVdhJcZBEILttmJz2ZdWuhJ+u43nelPy5gvV0O1zc7YrBWP91/y0RE2aRKrep3bPnFrKH4BOpDTix3qgqBiQ3L7+RgQiz59MmmgHMtEfxRBmSizCJAP0aRVKHzbHoU+X6to1qiC7YG8iOJhwMMP9UfdaCgTiX+B6ey2ksPezWwJ6U+mk8VM30+DBx1C7mCKpBy3DEO8mTOK9jAySu4cn38e/1F8WT4uwkNRiTcnGOQ59JfmozMX100vf+9I230WN3RsJ9kycQf1ifUL3tgvpqmmEw4WCmAqwBihByW1SgbZ/VjKhmcSy6Iwes8xQEivY2Iky4YBQUDT6NkY5ErdY90JWytnnWNqYjOr/c2uf+LeAhT8d6wmcIhmXJa7nIpqUimVDnwdH21nClhe+ZM2NTF6rFPWDE4YpmgK0MnSAZ57qwlbssIQ12fUskoZsxY0zbPJ7A6Qct6KShJn6hSYyE0ppmXyF5m9+9IRriREjKSHNIMGhEtYp8BY15Bu2E4Uz5CNapfMNzIl8Y1vcDZjkWKGdA88SUZhiAsIYZ+KWBqQWzuwSZ+2/w3rKOt5PqhBH0hwTO5cL8FPR/Sy5340RTokotND17+5v/skYmoHe9yBwlloQm5kUqvKdDQtZsYRb0CN7kmasNeqQZSl73Z9P/zkHagsfhkNP68QED9w76el0ccGME6pvPiIC+6QTgmifj/SNUqo5fpGCo9vMrZZ8zKtPHqYSmE1UWHq0CTwQUSLSaZzQZecW9Bn7Lj8ip/SlPk2KMZUvMfH5+I4vxCuU7SJebDKdjeVhlWMN/bIVhkxAMKqZFA2kH6PzTFsYEtTdmZbK6t/ydHGijIW+T1u6TGTrSikYey31DtHpveC+PZPfGwYxA0at9DrQryMNlMYyaWi5Xip2GYKhe4LwCIiozxXJ5p1PV7xMCYhxOn83BJ9BzoYzkR5VU/aQZaq8EeGUSy64HGjWNbYWDh3Afa5XM+sXWpjNKJItg/hOcn8yDTMCDi74D3IBskkv05I3KH9EZ6Tn0xOqsxXj9VU4BvBIedAuAUJji/aXROImzaM4l74lNB4ffQlEsJJr5l/aDPCjGaQOYlCuy1qAe0i0toK/uo6cxsV4R+5OPcAZVLLN82hYRKM0+p3HsBNNhSeFMRhMvD1Cn0aqEHtgMu40h/2EwVD+IdKPpd/I+tDR1bagJN9AGXjx1sn2rd1XjDEJSXtRgX6+hNbgRX95SBEOpBvbNjKJ4OhAZRNylDNZVsO3lOQscnWYPU6NdoCN/1Ap5JJpkC X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:37:22.6908 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 01af8ba3-4d9a-495c-ddba-08dcee09314b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004685.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4199 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Introduce `esw_qos_create_group_sched_elem` to handle the creation of group scheduling elements for E-Switch QoS, Transmit Scheduling Arbiter (TSAR). This reduces duplication and simplifies code for TSAR setup. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Daniel Machon --- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 64 +++++++++---------- 1 file changed, 31 insertions(+), 33 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index ee6f76a6f0b5..7732f948e9c6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -371,6 +371,33 @@ static int esw_qos_set_group_max_rate(struct mlx5_esw_rate_group *group, return err; } +static int esw_qos_create_group_sched_elem(struct mlx5_core_dev *dev, u32 parent_element_id, + u32 *tsar_ix) +{ + u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {}; + void *attr; + + if (!mlx5_qos_element_type_supported(dev, + SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR, + SCHEDULING_HIERARCHY_E_SWITCH) || + !mlx5_qos_tsar_type_supported(dev, + TSAR_ELEMENT_TSAR_TYPE_DWRR, + SCHEDULING_HIERARCHY_E_SWITCH)) + return -EOPNOTSUPP; + + MLX5_SET(scheduling_context, tsar_ctx, element_type, + SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR); + MLX5_SET(scheduling_context, tsar_ctx, parent_element_id, + parent_element_id); + attr = MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes); + MLX5_SET(tsar_element, attr, tsar_type, TSAR_ELEMENT_TSAR_TYPE_DWRR); + + return mlx5_create_scheduling_element_cmd(dev, + SCHEDULING_HIERARCHY_E_SWITCH, + tsar_ctx, + tsar_ix); +} + static int esw_qos_vport_create_sched_element(struct mlx5_vport *vport, u32 max_rate, u32 bw_share) { @@ -496,21 +523,11 @@ static void __esw_qos_free_rate_group(struct mlx5_esw_rate_group *group) static struct mlx5_esw_rate_group * __esw_qos_create_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack) { - u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {}; struct mlx5_esw_rate_group *group; - int tsar_ix, err; - void *attr; + u32 tsar_ix; + int err; - MLX5_SET(scheduling_context, tsar_ctx, element_type, - SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR); - MLX5_SET(scheduling_context, tsar_ctx, parent_element_id, - esw->qos.root_tsar_ix); - attr = MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes); - MLX5_SET(tsar_element, attr, tsar_type, TSAR_ELEMENT_TSAR_TYPE_DWRR); - err = mlx5_create_scheduling_element_cmd(esw->dev, - SCHEDULING_HIERARCHY_E_SWITCH, - tsar_ctx, - &tsar_ix); + err = esw_qos_create_group_sched_elem(esw->dev, esw->qos.root_tsar_ix, &tsar_ix); if (err) { NL_SET_ERR_MSG_MOD(extack, "E-Switch create TSAR for group failed"); return ERR_PTR(err); @@ -591,32 +608,13 @@ static int __esw_qos_destroy_rate_group(struct mlx5_esw_rate_group *group, static int esw_qos_create(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack) { - u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {}; struct mlx5_core_dev *dev = esw->dev; - void *attr; int err; if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling)) return -EOPNOTSUPP; - if (!mlx5_qos_element_type_supported(dev, - SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR, - SCHEDULING_HIERARCHY_E_SWITCH) || - !mlx5_qos_tsar_type_supported(dev, - TSAR_ELEMENT_TSAR_TYPE_DWRR, - SCHEDULING_HIERARCHY_E_SWITCH)) - return -EOPNOTSUPP; - - MLX5_SET(scheduling_context, tsar_ctx, element_type, - SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR); - - attr = MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes); - MLX5_SET(tsar_element, attr, tsar_type, TSAR_ELEMENT_TSAR_TYPE_DWRR); - - err = mlx5_create_scheduling_element_cmd(dev, - SCHEDULING_HIERARCHY_E_SWITCH, - tsar_ctx, - &esw->qos.root_tsar_ix); + err = esw_qos_create_group_sched_elem(esw->dev, 0, &esw->qos.root_tsar_ix); if (err) { esw_warn(dev, "E-Switch create root TSAR failed (%d)\n", err); return err; From patchwork Wed Oct 16 17:36:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13838671 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2049.outbound.protection.outlook.com [40.107.223.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 704B018660A for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Tariq Toukan Subject: [PATCH net-next V3 02/15] net/mlx5: Introduce node type to rate group structure Date: Wed, 16 Oct 2024 20:36:04 +0300 Message-ID: <20241016173617.217736-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000203:EE_|CH3PR12MB9077:EE_ X-MS-Office365-Filtering-Correlation-Id: 5bc871f7-6715-42e6-b8f6-08dcee093036 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: NVMLj0tg5O2ZcqgSjaTDOqBPRdCG5JvOHumBCPUjN5xFPTZQPpWmsiyonjRA3gshFt+k/GYZpTc0ajx4dV81ns5ryvXY5cBc1xjC036ZQZ4l+ovjA/p7uR3dDETPCNEU3Ss+LTHwIZ0YbibOs73/Ani576A1VWQMxMgmtZHt0wN7mQH6xUxjaoj2kFAo/XnC9MLlPBnJV5jwkAslSv2PI4ZtxbKSOTBmdWrOC7Grvko0GRhKvC9TPTeGildI3b/7IUK4K/kbUBLbesej6Pw7Y3jEbUhYuJqHOnA/6jfFPHnnFxGahUm3S47NBqMNBZTTLjwLRY1ptf2TjN4UWeSvOzBh7eDV2TLWsT9hrUxwZC1DjRm531AT1aYkf+GNVXuBDQebQTILaiRtxO5rBSEcP2zvg18oTGV4btRX+dDdUrWAH3tLap2OKjSiLhLeI3sGwgJ21rroCgScs8ec7LGEtqmQSU+scKoMAtTQkkHXebbYb7Plr7nXqcCbuE62dk5AZIN1MF4/5H4jTYei5nbm3IcNUP5zsl2/palZbK8x3YNqvffb8OgjXfjyULgEYuYkbN8xK67kVcKF0W9hVegn62p2fxZ80PCQeKPqOF99pH7xc4Sx33VQLdOaRtW2F/SrkFChYtYNu3RJ4yPxa0YdzvZ2TI7VgH7uytgM1VIJjwIKkZhbkjGKFMRWjlZDuKiHaf56Jzy2nXA2jg5pQzHq88l+5YCiljcE1NlHWzamDCo0cX6YIP+Z8ShsA1RhH4jLoQJKmtEMy1fEg1UIbOMJ5Wy1AdRev2H0QigQ2fWneNQvqdc7L54OxbObJmv2w1Vpofby02JSc5kyuvGDzcGPuwl61P96It7EOiphCzUFIJtVZDVmfrq1oFNNg8yr29G2QetbSwnT0auoVSEjwcMyC6dvQkbJweSucPnRGNM5mH8mNmzvjvldC27K0azVGOIXOeMNF3MpcIzS/p3172ARN5KUT2NFn+O8LXkSDITGWteSuOWh//dEiZ8ulOuWJJd6S94gr6dZ1xVXsIrfZjUnDDcw7h5zatgj0zsSwUyRixmNr3BjX9DCNVwEKrKZyo21NCOLi5OvIJGUtoKGzvT8S0KFMIvOgv51kvuHCiRUJp/BAZzIzzv8qJDWkTa0Gwpa+jy2vOcFzGYGz9MjyRs7AZHdDK5xAzN3RVddcFZBK2w3gJIyytvheFUthmmYK4o/qRVckkKf8EZGW7sKuh0DzyBFmdN7887y4r0AUh/gKp+toOusqfsHjSVFxA5tCyddGbjZEISPn/OAbp6jxpgPSNa+6RsHGJTSOsmu8gMUnNtRe6i90+1APjeJvYtnZZnoFDHeLMGdKkgPAm622OoSoOZuZR1EkRoG5IQ0Yc4Drdje2shf6ZMUjZHuW6L/bt/s X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:37:21.0620 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5bc871f7-6715-42e6-b8f6-08dcee093036 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000203.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9077 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Introduce the `sched_node_type` enum to represent both the group and its members as scheduling nodes in the rate hierarchy. Add the `type` field to the rate group structure to specify the type of the node membership in the rate hierarchy. Generalize comments to reflect this flexibility within the rate group structure. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Daniel Machon --- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 28 ++++++++++++------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index 7732f948e9c6..b324a6b1b9ff 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -61,6 +61,10 @@ static void esw_qos_domain_release(struct mlx5_eswitch *esw) esw->qos.domain = NULL; } +enum sched_node_type { + SCHED_NODE_TYPE_VPORTS_TSAR, +}; + struct mlx5_esw_rate_group { u32 tsar_ix; /* Bandwidth parameters. */ @@ -68,11 +72,13 @@ struct mlx5_esw_rate_group { u32 min_rate; /* A computed value indicating relative min_rate between group members. */ u32 bw_share; - /* Membership in the qos domain 'groups' list. */ + /* Membership in the parent list. */ struct list_head parent_entry; + /* The type of this group node in the rate hierarchy. */ + enum sched_node_type type; /* The eswitch this group belongs to. */ struct mlx5_eswitch *esw; - /* Vport members of this group.*/ + /* Members of this group.*/ struct list_head members; }; @@ -499,7 +505,7 @@ static int esw_qos_vport_update_group(struct mlx5_vport *vport, } static struct mlx5_esw_rate_group * -__esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix) +__esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_node_type type) { struct mlx5_esw_rate_group *group; @@ -509,6 +515,7 @@ __esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix) group->esw = esw; group->tsar_ix = tsar_ix; + group->type = type; INIT_LIST_HEAD(&group->members); list_add_tail(&group->parent_entry, &esw->qos.domain->groups); return group; @@ -521,7 +528,7 @@ static void __esw_qos_free_rate_group(struct mlx5_esw_rate_group *group) } static struct mlx5_esw_rate_group * -__esw_qos_create_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack) +__esw_qos_create_vports_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack) { struct mlx5_esw_rate_group *group; u32 tsar_ix; @@ -533,7 +540,7 @@ __esw_qos_create_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *ex return ERR_PTR(err); } - group = __esw_qos_alloc_rate_group(esw, tsar_ix); + group = __esw_qos_alloc_rate_group(esw, tsar_ix, SCHED_NODE_TYPE_VPORTS_TSAR); if (!group) { NL_SET_ERR_MSG_MOD(extack, "E-Switch alloc group failed"); err = -ENOMEM; @@ -563,7 +570,7 @@ static int esw_qos_get(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack) static void esw_qos_put(struct mlx5_eswitch *esw); static struct mlx5_esw_rate_group * -esw_qos_create_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack) +esw_qos_create_vports_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack) { struct mlx5_esw_rate_group *group; int err; @@ -576,7 +583,7 @@ esw_qos_create_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *exta if (err) return ERR_PTR(err); - group = __esw_qos_create_rate_group(esw, extack); + group = __esw_qos_create_vports_rate_group(esw, extack); if (IS_ERR(group)) esw_qos_put(esw); @@ -621,12 +628,13 @@ static int esw_qos_create(struct mlx5_eswitch *esw, struct netlink_ext_ack *exta } if (MLX5_CAP_QOS(dev, log_esw_max_sched_depth)) { - esw->qos.group0 = __esw_qos_create_rate_group(esw, extack); + esw->qos.group0 = __esw_qos_create_vports_rate_group(esw, extack); } else { /* The eswitch doesn't support scheduling groups. * Create a software-only group0 using the root TSAR to attach vport QoS to. */ - if (!__esw_qos_alloc_rate_group(esw, esw->qos.root_tsar_ix)) + if (!__esw_qos_alloc_rate_group(esw, esw->qos.root_tsar_ix, + SCHED_NODE_TYPE_VPORTS_TSAR)) esw->qos.group0 = ERR_PTR(-ENOMEM); } if (IS_ERR(esw->qos.group0)) { @@ -1038,7 +1046,7 @@ int mlx5_esw_devlink_rate_node_new(struct devlink_rate *rate_node, void **priv, goto unlock; } - group = esw_qos_create_rate_group(esw, extack); + group = esw_qos_create_vports_rate_group(esw, extack); if (IS_ERR(group)) { err = PTR_ERR(group); goto unlock; From patchwork Wed Oct 16 17:36:05 2024 Content-Type: text/plain; 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Wed, 16 Oct 2024 10:37:12 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Tariq Toukan Subject: [PATCH net-next V3 03/15] net/mlx5: Add parent group support in rate group structure Date: Wed, 16 Oct 2024 20:36:05 +0300 Message-ID: <20241016173617.217736-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004683:EE_|PH8PR12MB7229:EE_ X-MS-Office365-Filtering-Correlation-Id: 73443296-1b1a-452a-54e3-08dcee093678 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: UGSTOa1OMjNZiBUj4pyWzMsTXHr8S2MgXyquibNXobopWsXsGUPK4IxYjGrXY55utvRiH/nM/GfvAwNUVKh4UfdsJo7rDn7aexSShLEg/G37cE1F5DwKYj3MA9qz5ejgabz37XWd+NetGq85WTh4i0VnG8mtK16Wfes0qM2dF7v170lbKwbY6vYI0gGSbhBGYeuu4AF+L/3OkExDsY3CueN0eAid6xJQWT76D9VZyr/qErltNyXrCO8DgGm/QRKCU0Iu3j/94d0ksHuNyOm/qJTrWyCn/WQl+eWqMQt0XT83kVzjJGP0ZAWyIs2Jrfr6dZZF+990wJrlG0giZXPWSVvWl6gbOAVajPfWKDmECwoF3c1whoP364ljxvtNi+SZMXueRTdIH+7QgSy7gj06MfiExyw7uMgjoPolIs7prF35tgEEsBokm7vW1PjZgFVRCn7bdp+9xOY+k0tIhtdIJJETBAFZegtpw9pyiPihzQWPmQk8dFMAoYuoj/7nUhJiQ9anDfjdvTBrxlm3iDZDge1coNz6TtHHpzlllldZZrmYwsihicTr+muaaOnepl8Rd2CO518xvJDhhb7NG0z/NrFpgzEgJVJULtAOJ0Nw6Y53YL9ig36VkK1hUVgykQMoms/VKxUbaNpcLu/l17SpeM3AGkEl177LHBBHlsxsPdR8LT/HqwUNn9YOLSzwCb8LulGMT6Q/5MsJVwrqKu8V0Ttq57EPKG8+Njxo4VI0XEDgB46r78MlJja9ebYwlR6acU5qC6SF14ch1INlmr8i8Uo2T9KakLA9UjUrGdsYOw4GJzTpJ0FkO/r2MxcuEBtdFHK/N7/9ixY8GpXjl16uKqYwbj3C2D/4+hV/xZihn/GEFphcgItq9jErI2Mw/oH3VvZM7Ahct87cmGyU02bkYDJGEHTgWRgPqIWsy6XtANuwHMvBJ+ZRxCzD5Cvx3/sfOSSqvM5BGRW5WpxQeOvaa2sD68750y37C97L23xuCKdBYSWyN1t8d8zGaTjI7V41+Qu65w9ZfYb1QH2lkgpzKIbI5EF73xiTV0HuAfmypWOPwVzwFt/tt/fkH+6XiCZtkcDBDCeV9nUNMB1zOGyqIZ+P3FgsKe07eOtc27r3Zwm5v4+ZygqbqyR3NEmIFa5MQybZIShVaWzhQHHEsLlWPlqyLRaBlkMiGqHJ4O5azC7moHbJSkXHwfwNOCuMIC/pIhJsBpX4OKWose66n+f8SIrg4Hq+XRQpVz6h4jeUH73/SQAokeD9S4LdR3ABW8uYC2FE/srC+Xlsp0xfO9InKT1hZg8+QS1RUv7p4+5EmCJceOajI0jAwpeCaiq+WfeXF6AyTPG8eYN86ZNGwpvRVWtZaH9mlYyT/CPZUFi0JK5brQuXJiecs2ixoSfX2zW3 X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:37:31.4333 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 73443296-1b1a-452a-54e3-08dcee093678 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004683.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7229 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Introduce a `parent` field in the `mlx5_esw_rate_group` structure to support hierarchical group relationships. The `parent` can reference another group or be set to `NULL`, indicating the group is connected to the root TSAR. This change enables the ability to manage groups in a hierarchical structure for future enhancements. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Daniel Machon --- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index b324a6b1b9ff..f2a0d59fa5bb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -72,6 +72,8 @@ struct mlx5_esw_rate_group { u32 min_rate; /* A computed value indicating relative min_rate between group members. */ u32 bw_share; + /* The parent group of this group. */ + struct mlx5_esw_rate_group *parent; /* Membership in the parent list. */ struct list_head parent_entry; /* The type of this group node in the rate hierarchy. */ @@ -505,7 +507,8 @@ static int esw_qos_vport_update_group(struct mlx5_vport *vport, } static struct mlx5_esw_rate_group * -__esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_node_type type) +__esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_node_type type, + struct mlx5_esw_rate_group *parent) { struct mlx5_esw_rate_group *group; @@ -516,6 +519,7 @@ __esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_nod group->esw = esw; group->tsar_ix = tsar_ix; group->type = type; + group->parent = parent; INIT_LIST_HEAD(&group->members); list_add_tail(&group->parent_entry, &esw->qos.domain->groups); return group; @@ -528,7 +532,8 @@ static void __esw_qos_free_rate_group(struct mlx5_esw_rate_group *group) } static struct mlx5_esw_rate_group * -__esw_qos_create_vports_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack) +__esw_qos_create_vports_rate_group(struct mlx5_eswitch *esw, struct mlx5_esw_rate_group *parent, + struct netlink_ext_ack *extack) { struct mlx5_esw_rate_group *group; u32 tsar_ix; @@ -540,7 +545,7 @@ __esw_qos_create_vports_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ return ERR_PTR(err); } - group = __esw_qos_alloc_rate_group(esw, tsar_ix, SCHED_NODE_TYPE_VPORTS_TSAR); + group = __esw_qos_alloc_rate_group(esw, tsar_ix, SCHED_NODE_TYPE_VPORTS_TSAR, parent); if (!group) { NL_SET_ERR_MSG_MOD(extack, "E-Switch alloc group failed"); err = -ENOMEM; @@ -583,7 +588,7 @@ esw_qos_create_vports_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ac if (err) return ERR_PTR(err); - group = __esw_qos_create_vports_rate_group(esw, extack); + group = __esw_qos_create_vports_rate_group(esw, NULL, extack); if (IS_ERR(group)) esw_qos_put(esw); @@ -628,13 +633,13 @@ static int esw_qos_create(struct mlx5_eswitch *esw, struct netlink_ext_ack *exta } if (MLX5_CAP_QOS(dev, log_esw_max_sched_depth)) { - esw->qos.group0 = __esw_qos_create_vports_rate_group(esw, extack); + esw->qos.group0 = __esw_qos_create_vports_rate_group(esw, NULL, extack); } else { /* The eswitch doesn't support scheduling groups. * Create a software-only group0 using the root TSAR to attach vport QoS to. */ if (!__esw_qos_alloc_rate_group(esw, esw->qos.root_tsar_ix, - SCHED_NODE_TYPE_VPORTS_TSAR)) + SCHED_NODE_TYPE_VPORTS_TSAR, NULL)) esw->qos.group0 = ERR_PTR(-ENOMEM); } if (IS_ERR(esw->qos.group0)) { From patchwork Wed Oct 16 17:36:06 2024 Content-Type: text/plain; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Tariq Toukan Subject: [PATCH net-next V3 04/15] net/mlx5: Restrict domain list insertion to root TSAR ancestors Date: Wed, 16 Oct 2024 20:36:06 +0300 Message-ID: <20241016173617.217736-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004683:EE_|LV3PR12MB9187:EE_ X-MS-Office365-Filtering-Correlation-Id: e770b8d4-5beb-44ee-0df2-08dcee09393a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: mOHxDtiTsyHBrNGtzfBW5dGg79P8naW+jfyV0ZVxQpWTkO2t6StvfK8XVmn1ZlCNijmg0Nc2N9PrJelXTuH49k6+4WG7scZXLdBvt3RdTr9xzzPG/Lp93OdgGHtRq5GxfKdG6GFT6SEWfcpBhJSuWQwZbqTr8V2fQ/5LmRjRHbKRD1wMBudsWq3XJc3qBED8k+JtR5VUAFs1WlSEoRnk9TPiYkAWeEDu6DTkVRAiqy9t2nNBYNMU3ol5AOrxePBjiDjRc5ArxHkTwTRqzAbrawGq4j9TatuK/HIXTuakdnm6aJlJ8dOZzlgaik2ZmKoj7o6TKbH0Yml/olphmvQyDTj04owGXB2tqkl7DYUOIJ7/QLRYDhBDGZPmO5t/qV9iKbvCQNWzNXANgmc736ioVqIroYuiV1/1n8diJ5J7mCbncTmrcEJBPeYfTCnDYeWnnkmV4Mx6MpTJ4ujR2QD0FCs3oDAoeG6p8D5rJUYGQGW5uaxBzFhBvHHH4IN5PjsYyehgQ8beqdf2uB/GyegOff0En6OYZ2THvzEGAuUKWFECMM9uSvDXOJMoVDY0VIld6WIqdMQ1vFbC+UYXWHcZP04wJxeEhhWkSz1wVDJLuLk+/+OHFuww0YWzk+rlAUNI9aiEpDHDGrIUw54pa+Tp1Czz0fVl+nV5S6lSvD3TtlZwZhFe3/PEfWPAPh/p5TKITqN2UDHaytV0zh+pyRITvpNI7DMMoQFKXzXA9YhWmWQRqvbkR7L8a7vPcCaXvcvyP+sRgbOM1OcBNxFvAxLQrA/Iv+Ffx62Glffko1VzCG5iNKMuQmv75nqnltiMc1FzAXEA/PPSXfgUtSuqQYZ7clZ453fcm7ojJCGqSHiZYyw3KriFIIST3VN3bKc6zzKF9RjCHs6d7QEfoMz6PC1L2wrehvNnXJ6lwEOu/SgwDElWMBxzDuBSE4p/s99q4vb4Ahi0ZsYk+NukfXqmDmZuKG1fqjRG/8j/qny8yOaid6g+2e5nSSFclTsE0b00/QturH3Z3RFaFp2OvaOR+LP90dPIYROScfgh2Z8YZrM6LwWfHZ/LvWhA/LL5yLKomzF1ORwgwm7eFPcfcxUOtAe33lIH7eQnMrdlbM3/167UGnOLlZehzWgAU7e9XNfadD85bRKR1WQBH27W1rGu6zsTYXY9vZH9BRIKSqAF4DcOPA6RmfHL5GSEvAY5LMY0l9ChbVIIWXiLB2mozGd68zC2J1P8VfahYIDtGdb0DpMGFOBskEohi/0ITOKxeDy+bErhfacH5BboOGAPJOYV1afPVGpYffSDvzQDVhYrQPnXARMvY1vJhV35Iqs4aaY1N+KgqTk+NCjirrTVHoNOb1jJHF1CzCJ6ru3Egb4mJy4SU4I= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:37:35.9958 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e770b8d4-5beb-44ee-0df2-08dcee09393a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004683.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9187 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Update the logic for adding rate groups to the E-Switch domain list, ensuring only groups with the root Transmit Scheduling Arbiter as their parent are included. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Daniel Machon --- drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index f2a0d59fa5bb..dd6fe729f456 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -511,6 +511,7 @@ __esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_nod struct mlx5_esw_rate_group *parent) { struct mlx5_esw_rate_group *group; + struct list_head *parent_list; group = kzalloc(sizeof(*group), GFP_KERNEL); if (!group) @@ -521,7 +522,9 @@ __esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_nod group->type = type; group->parent = parent; INIT_LIST_HEAD(&group->members); - list_add_tail(&group->parent_entry, &esw->qos.domain->groups); + parent_list = parent ? &parent->members : &esw->qos.domain->groups; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Tariq Toukan Subject: [PATCH net-next V3 05/15] net/mlx5: Rename vport QoS group reference to parent Date: Wed, 16 Oct 2024 20:36:07 +0300 Message-ID: <20241016173617.217736-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000203:EE_|SJ0PR12MB6757:EE_ X-MS-Office365-Filtering-Correlation-Id: 60edd1b0-d90c-42d0-398b-08dcee09362a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: sy6rE+e9ufoDh4W1jXA2H3+pw/XIa5nrrCi0SOUzJ7PQk+r814V1Yn/q6SFxLUHx0BbItmK+jddvsQtzY9UfDHlrcbLgQ+7u0Ap/1oVyFCLavCsCTlqem1/ztQaODi4uuCWGv+5WrvKiXfKc2DndlbCU+p2XqAekIzMV3sClyYw3r6CwBPGcf5jjdanTKEzeYv9AKLsRvWjgq27WJSky+zMVeZVvgCBRhoS2AXGIE2EVndEwcTe2SOnWvpVNRrRTLv338thXkOyrGvTH64qM7X24cKTMDsIjNVYw7yJ9QC1AFsmkUSPoQl7t+uO/HBmvfJ49egUNfmLOZXypPk+LvcSbMCnmv9dTqifbKxzlv+m1dCYMMAEB6iTqS3rYCUa/q2vMMAMybNkfmLB4U6jVx8/VQqACk0ikucQJJB/pdnbQCgD7koNV6aC/9xUubXEep2BlLupPMPVSRGp1ZgUTPxdVoZBVpU5vpQL9Nk1rBOoaL2W9SY000JFPoEFDnzdx+WkxbeKB3EHcSZABxvDVpaVUtaEYsQKnucylKIfB/aTgJYcLg2szeb+yZO1iWJwJVScGv7t66DJnURGqw3f5H3+hTKPc3xBbIoGJC3vYsQ/veT3U4DoRPSQdQdjgzC68aq2BbBAfdBlw1p1ENR/CUGRt0h7cPOHrWwsnwOphKG+9sRSHZwvbk+OLgW4KShkvR2wHmlPwHCIdbePgKY5wkWel9zKsie9QShzPSYIzlHfai7kEpkopI5xst/zFPnp/BTAJEw7J3YfxoSouz8vGPJDnN6L5cMISCcH/vZg7UtIBkiuywWCDRmGe7VM5AD8umrfWyil0eGD4VOkYcJRkid7Ocbepq2zupN7kx24eGgTaWeaZHJ4KTidi2DCXkGISiEG7MC3iCasKMsHDdCPBVQYr5X+KbvYukWKrdHKOnepf9it5S0QVpy37p6clzIZAPNgq7EC+u9+QCU3M8C+hv5bages70pzshol2dhXTjNe1dNBAsVaBlneiKO7TCuC46OvzCzR8O3e3gpA1WFgeCx47K7WB05mUlps7xuUows2Jr8y0LJga1F1qg4U/s3mbvAND4nlVqh00P4DYKHqqY3XvDP0X8qhz8Yb+6Qf017KSomW0KEyWeIHZjAkaKgBAj9QJBODrhDC66J9ybHv5YxLb63MrRkYrs9pWsWi225ouOBHzw71KiI2FGSuyP/+acMC/db7akcrdqCxq1F5LDUzN+tamgAWn8hfBaWvJQAxkyBm2ytzFG5/vGtuoqBa10jxK5G3wMpLFFpOLcxZf4WVrJl3QCpoAPFFxFTXcf4D2WoQc+bbbPRTb2hL2x+XiNx4A4sRHhuOkea3vMyXw2aEetcHR9dY5MYkfYg0S+U8WNBsYXIYi03xVdJR2qLph X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:37:31.0464 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60edd1b0-d90c-42d0-398b-08dcee09362a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000203.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6757 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Rename the `group` field in the `mlx5_vport` structure to `parent` to clarify the vport's role as a member of a parent group and distinguish it from the concept of a general group. Additionally, rename `group_entry` to `parent_entry` to reflect this update. This distinction will be important for handling more complex group structures and scheduling elements. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Daniel Machon --- .../mlx5/core/esw/diag/qos_tracepoint.h | 8 ++-- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 42 +++++++++---------- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 6 ++- 3 files changed, 29 insertions(+), 27 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/diag/qos_tracepoint.h b/drivers/net/ethernet/mellanox/mlx5/core/esw/diag/qos_tracepoint.h index 645bad0d625f..2aea01959073 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/diag/qos_tracepoint.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/diag/qos_tracepoint.h @@ -35,18 +35,18 @@ DECLARE_EVENT_CLASS(mlx5_esw_vport_qos_template, __field(unsigned int, sched_elem_ix) __field(unsigned int, bw_share) __field(unsigned int, max_rate) - __field(void *, group) + __field(void *, parent) ), TP_fast_assign(__assign_str(devname); __entry->vport_id = vport->vport; __entry->sched_elem_ix = vport->qos.esw_sched_elem_ix; __entry->bw_share = bw_share; __entry->max_rate = max_rate; - __entry->group = vport->qos.group; + __entry->parent = vport->qos.parent; ), - TP_printk("(%s) vport=%hu sched_elem_ix=%u bw_share=%u, max_rate=%u group=%p\n", + TP_printk("(%s) vport=%hu sched_elem_ix=%u bw_share=%u, max_rate=%u parent=%p\n", __get_str(devname), __entry->vport_id, __entry->sched_elem_ix, - __entry->bw_share, __entry->max_rate, __entry->group + __entry->bw_share, __entry->max_rate, __entry->parent ) ); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index dd6fe729f456..837c4dda814d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -84,11 +84,11 @@ struct mlx5_esw_rate_group { struct list_head members; }; -static void esw_qos_vport_set_group(struct mlx5_vport *vport, struct mlx5_esw_rate_group *group) +static void esw_qos_vport_set_parent(struct mlx5_vport *vport, struct mlx5_esw_rate_group *parent) { - list_del_init(&vport->qos.group_entry); - vport->qos.group = group; - list_add_tail(&vport->qos.group_entry, &group->members); + list_del_init(&vport->qos.parent_entry); + vport->qos.parent = parent; + list_add_tail(&vport->qos.parent_entry, &parent->members); } static int esw_qos_sched_elem_config(struct mlx5_core_dev *dev, u32 sched_elem_ix, @@ -131,7 +131,7 @@ static int esw_qos_vport_config(struct mlx5_vport *vport, u32 max_rate, u32 bw_share, struct netlink_ext_ack *extack) { - struct mlx5_core_dev *dev = vport->qos.group->esw->dev; + struct mlx5_core_dev *dev = vport->qos.parent->esw->dev; int err; err = esw_qos_sched_elem_config(dev, vport->qos.esw_sched_elem_ix, max_rate, bw_share); @@ -157,7 +157,7 @@ static u32 esw_qos_calculate_group_min_rate_divider(struct mlx5_esw_rate_group * /* Find max min_rate across all vports in this group. * This will correspond to fw_max_bw_share in the final bw_share calculation. */ - list_for_each_entry(vport, &group->members, qos.group_entry) { + list_for_each_entry(vport, &group->members, qos.parent_entry) { if (vport->qos.min_rate > max_guarantee) max_guarantee = vport->qos.min_rate; } @@ -217,7 +217,7 @@ static int esw_qos_normalize_group_min_rate(struct mlx5_esw_rate_group *group, u32 bw_share; int err; - list_for_each_entry(vport, &group->members, qos.group_entry) { + list_for_each_entry(vport, &group->members, qos.parent_entry) { bw_share = esw_qos_calc_bw_share(vport->qos.min_rate, divider, fw_max_bw_share); if (bw_share == vport->qos.bw_share) @@ -286,7 +286,7 @@ static int esw_qos_set_vport_min_rate(struct mlx5_vport *vport, previous_min_rate = vport->qos.min_rate; vport->qos.min_rate = min_rate; - err = esw_qos_normalize_group_min_rate(vport->qos.group, extack); + err = esw_qos_normalize_group_min_rate(vport->qos.parent, extack); if (err) vport->qos.min_rate = previous_min_rate; @@ -311,7 +311,7 @@ static int esw_qos_set_vport_max_rate(struct mlx5_vport *vport, /* Use parent group limit if new max rate is 0. */ if (!max_rate) - act_max_rate = vport->qos.group->max_rate; + act_max_rate = vport->qos.parent->max_rate; err = esw_qos_vport_config(vport, act_max_rate, vport->qos.bw_share, extack); @@ -366,7 +366,7 @@ static int esw_qos_set_group_max_rate(struct mlx5_esw_rate_group *group, group->max_rate = max_rate; /* Any unlimited vports in the group should be set with the value of the group. */ - list_for_each_entry(vport, &group->members, qos.group_entry) { + list_for_each_entry(vport, &group->members, qos.parent_entry) { if (vport->qos.max_rate) continue; @@ -409,9 +409,9 @@ static int esw_qos_create_group_sched_elem(struct mlx5_core_dev *dev, u32 parent static int esw_qos_vport_create_sched_element(struct mlx5_vport *vport, u32 max_rate, u32 bw_share) { + struct mlx5_esw_rate_group *parent = vport->qos.parent; u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {}; - struct mlx5_esw_rate_group *group = vport->qos.group; - struct mlx5_core_dev *dev = group->esw->dev; + struct mlx5_core_dev *dev = parent->esw->dev; void *attr; int err; @@ -424,7 +424,7 @@ static int esw_qos_vport_create_sched_element(struct mlx5_vport *vport, SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT); attr = MLX5_ADDR_OF(scheduling_context, sched_ctx, element_attributes); MLX5_SET(vport_element, attr, vport_number, vport->vport); - MLX5_SET(scheduling_context, sched_ctx, parent_element_id, group->tsar_ix); + MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent->tsar_ix); MLX5_SET(scheduling_context, sched_ctx, max_average_bw, max_rate); MLX5_SET(scheduling_context, sched_ctx, bw_share, bw_share); @@ -458,7 +458,7 @@ static int esw_qos_update_group_scheduling_element(struct mlx5_vport *vport, return err; } - esw_qos_vport_set_group(vport, new_group); + esw_qos_vport_set_parent(vport, new_group); /* Use new group max rate if vport max rate is unlimited. */ max_rate = vport->qos.max_rate ? vport->qos.max_rate : new_group->max_rate; err = esw_qos_vport_create_sched_element(vport, max_rate, vport->qos.bw_share); @@ -470,7 +470,7 @@ static int esw_qos_update_group_scheduling_element(struct mlx5_vport *vport, return 0; err_sched: - esw_qos_vport_set_group(vport, curr_group); + esw_qos_vport_set_parent(vport, curr_group); max_rate = vport->qos.max_rate ? vport->qos.max_rate : curr_group->max_rate; if (esw_qos_vport_create_sched_element(vport, max_rate, vport->qos.bw_share)) esw_warn(curr_group->esw->dev, "E-Switch vport group restore failed (vport=%d)\n", @@ -488,7 +488,7 @@ static int esw_qos_vport_update_group(struct mlx5_vport *vport, int err; esw_assert_qos_lock_held(esw); - curr_group = vport->qos.group; + curr_group = vport->qos.parent; new_group = group ?: esw->qos.group0; if (curr_group == new_group) return 0; @@ -715,8 +715,8 @@ static int esw_qos_vport_enable(struct mlx5_vport *vport, if (err) return err; - INIT_LIST_HEAD(&vport->qos.group_entry); - esw_qos_vport_set_group(vport, esw->qos.group0); + INIT_LIST_HEAD(&vport->qos.parent_entry); + esw_qos_vport_set_parent(vport, esw->qos.group0); err = esw_qos_vport_create_sched_element(vport, max_rate, bw_share); if (err) @@ -743,10 +743,10 @@ void mlx5_esw_qos_vport_disable(struct mlx5_vport *vport) esw_qos_lock(esw); if (!vport->qos.enabled) goto unlock; - WARN(vport->qos.group != esw->qos.group0, + WARN(vport->qos.parent != esw->qos.group0, "Disabling QoS on port before detaching it from group"); - dev = vport->qos.group->esw->dev; + dev = vport->qos.parent->esw->dev; err = mlx5_destroy_scheduling_element_cmd(dev, SCHEDULING_HIERARCHY_E_SWITCH, vport->qos.esw_sched_elem_ix); @@ -888,7 +888,7 @@ int mlx5_esw_qos_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num, u32 /* Eswitch QoS wasn't enabled yet. Enable it and vport QoS. */ err = esw_qos_vport_enable(vport, rate_mbps, vport->qos.bw_share, NULL); } else { - struct mlx5_core_dev *dev = vport->qos.group->esw->dev; + struct mlx5_core_dev *dev = vport->qos.parent->esw->dev; MLX5_SET(scheduling_context, ctx, max_average_bw, rate_mbps); bitmask = MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h index 3b901bd36d4b..e789fb14989b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -221,8 +221,10 @@ struct mlx5_vport { u32 max_rate; /* A computed value indicating relative min_rate between vports in a group. */ u32 bw_share; - struct mlx5_esw_rate_group *group; - struct list_head group_entry; + /* The parent group of this vport scheduling element. */ + struct mlx5_esw_rate_group *parent; + /* Membership in the parent 'members' list. */ + struct list_head parent_entry; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Tariq Toukan Subject: [PATCH net-next V3 06/15] net/mlx5: Introduce node struct and rename group terminology to node Date: Wed, 16 Oct 2024 20:36:08 +0300 Message-ID: <20241016173617.217736-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000203:EE_|CY8PR12MB8315:EE_ X-MS-Office365-Filtering-Correlation-Id: da79ea1b-9933-42db-ded0-08dcee093732 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: grhxk+o5TIcO6OdoFt/FepI4sM11X630zZE+gMFmQawFx8EoFMc/S8CihdfRTw7/cKxb2ssRv5swYX2mcx0GpMZjH0iPWMakXY+b1cpFkTp9sd0q9anMJ/9M5kDp0k+XpMI2OT+Jew+K3fyUbZtcJgASeBB3uweH/y6MHoBq2BHOtB4IifmuTC4YpfekmDQOgyK0gAY9KoxHtFqk3OEVqhf3WDtwC/rrbFM+WBsjqUlpx0qSHH/jvfzElf+Fq8xp+WVbp26MpWxsUYwT4sXBgADAmw3YCfkUXGFKUxfBCtC+8AGgyBfFwdFUTNZ5d7t1wMOj5xf2lPxlajxMRZ8xq2dhHB24YXDyqTiGvUV9bMst30Wkq67IDIvN4l6DGdL+fqrdaLaY3z5La6okAAtDUcgC/q+904Q6rllMyq9KWxY1Dp1xTHMlJ6yoFfjyKR5ojJIKkWuvYrgey1b/5/VQquJnGPSx+7DdVRz7Dp3jspPySEINN1jGgl/LfSgw0tEhY0y0ca5xJyMxm9Kd8XmyrTVvdLAbdJ/wI/Tu7xmFdJrPGo09oCKyRI/+RQt/W6mXgSky+JQ0dfg08qu/ukwyMkAGW3ldqcS37+Xp+TjHYsvbGF9SpVcKkpGZdxwV9COv3lSjS3ZlSzz8krDVPUGBQK2tlaj+kfxTh1wnbiY+Osh9vztWiIQzNmCZge17rzGL8zed6we5CIn4YWNlKlzl2MFi6vlLYqZ21h1+R/hepyL2o+Osk102TzUy8ZrDbzl5xkU57jRQNMjUzh3yIf0tr9jAMlW3wK8DDqq1RMc2IiF/Ax10F3QF2CJ45C20VndZWvxkTrPcgezlnF08reauRbZktX6tAmE+JZhF7enhTTHHmH3ACdTTrRSod052YBM6z37yzp+da3sfzmLpcFrbxaihnODB9hOhBwHy+VYJspkKSq+98UHGfYfbUAMqbNXXa6SrVt9iUJ6xvPhErzio0wyUr/429SpBj70F9qXET4oudcn6MF/UMANSmvvfPwTBCfFs2wgMjbDfXs/8Gu3a4FsLLtkz5PaFHq3RULedbkn8Rdn/l22nf0d9GDnEI/hvXXb1FPxD5Ucfo508xtujKvQU8lm9f3g4YQGcjQD23VS9kqys8J9j2cCCT4AURN1cGvxN2l7DsQiqXqYsW2UxjpCDKX6WU1jNIUmvUOtMteJRyCYM8p7vZI6QR8BVAfKw4hps4T5qzbPnBlu+EDa9gz2ISItcVAT+0s5OCmxLJzKLoGCQRnXU4XYsXWwLBP1QPNPb9LLjTWgKwene0MkakYWlNAXMes+PqANC7fUUPpbhwdKa2/sUF27BZj56LROliPltmaxZGEDHSeWoc/i7iq0bxn+o5wSnZu3K6C0NMEc= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:37:32.7808 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da79ea1b-9933-42db-ded0-08dcee093732 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000203.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8315 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Introduce the `mlx5_esw_sched_node` struct, consolidating all rate hierarchy related details, including membership and scheduling parameters. Since the group concept aligns with the `mlx5_esw_sched_node`, replace the `mlx5_esw_rate_group` struct with it and rename the "group" terminology to "node" throughout the rate hierarchy. All relevant code paths and structures have been updated to use the "node" terminology accordingly, laying the groundwork for future patches that will unify the handling of different types of members within the rate hierarchy. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Daniel Machon --- .../mellanox/mlx5/core/esw/devlink_port.c | 2 +- .../mlx5/core/esw/diag/qos_tracepoint.h | 40 +- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 374 +++++++++--------- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 16 +- 4 files changed, 217 insertions(+), 215 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c index 86af1891395f..d0f38818363f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/devlink_port.c @@ -195,7 +195,7 @@ void mlx5_esw_offloads_devlink_port_unregister(struct mlx5_vport *vport) return; dl_port = vport->dl_port; - mlx5_esw_qos_vport_update_group(vport, NULL, NULL); + mlx5_esw_qos_vport_update_node(vport, NULL, NULL); devl_rate_leaf_destroy(&dl_port->dl_port); devl_port_unregister(&dl_port->dl_port); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/diag/qos_tracepoint.h b/drivers/net/ethernet/mellanox/mlx5/core/esw/diag/qos_tracepoint.h index 2aea01959073..0b50ef0871f2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/diag/qos_tracepoint.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/diag/qos_tracepoint.h @@ -62,57 +62,57 @@ DEFINE_EVENT(mlx5_esw_vport_qos_template, mlx5_esw_vport_qos_config, TP_ARGS(dev, vport, bw_share, max_rate) ); -DECLARE_EVENT_CLASS(mlx5_esw_group_qos_template, +DECLARE_EVENT_CLASS(mlx5_esw_node_qos_template, TP_PROTO(const struct mlx5_core_dev *dev, - const struct mlx5_esw_rate_group *group, + const struct mlx5_esw_sched_node *node, unsigned int tsar_ix), - TP_ARGS(dev, group, tsar_ix), + TP_ARGS(dev, node, tsar_ix), TP_STRUCT__entry(__string(devname, dev_name(dev->device)) - __field(const void *, group) + __field(const void *, node) __field(unsigned int, tsar_ix) ), TP_fast_assign(__assign_str(devname); - __entry->group = group; + __entry->node = node; __entry->tsar_ix = tsar_ix; ), - TP_printk("(%s) group=%p tsar_ix=%u\n", - __get_str(devname), __entry->group, __entry->tsar_ix + TP_printk("(%s) node=%p tsar_ix=%u\n", + __get_str(devname), __entry->node, __entry->tsar_ix ) ); -DEFINE_EVENT(mlx5_esw_group_qos_template, mlx5_esw_group_qos_create, +DEFINE_EVENT(mlx5_esw_node_qos_template, mlx5_esw_node_qos_create, TP_PROTO(const struct mlx5_core_dev *dev, - const struct mlx5_esw_rate_group *group, + const struct mlx5_esw_sched_node *node, unsigned int tsar_ix), - TP_ARGS(dev, group, tsar_ix) + TP_ARGS(dev, node, tsar_ix) ); -DEFINE_EVENT(mlx5_esw_group_qos_template, mlx5_esw_group_qos_destroy, +DEFINE_EVENT(mlx5_esw_node_qos_template, mlx5_esw_node_qos_destroy, TP_PROTO(const struct mlx5_core_dev *dev, - const struct mlx5_esw_rate_group *group, + const struct mlx5_esw_sched_node *node, unsigned int tsar_ix), - TP_ARGS(dev, group, tsar_ix) + TP_ARGS(dev, node, tsar_ix) ); -TRACE_EVENT(mlx5_esw_group_qos_config, +TRACE_EVENT(mlx5_esw_node_qos_config, TP_PROTO(const struct mlx5_core_dev *dev, - const struct mlx5_esw_rate_group *group, + const struct mlx5_esw_sched_node *node, unsigned int tsar_ix, u32 bw_share, u32 max_rate), - TP_ARGS(dev, group, tsar_ix, bw_share, max_rate), + TP_ARGS(dev, node, tsar_ix, bw_share, max_rate), TP_STRUCT__entry(__string(devname, dev_name(dev->device)) - __field(const void *, group) + __field(const void *, node) __field(unsigned int, tsar_ix) __field(unsigned int, bw_share) __field(unsigned int, max_rate) ), TP_fast_assign(__assign_str(devname); - __entry->group = group; + __entry->node = node; __entry->tsar_ix = tsar_ix; __entry->bw_share = bw_share; __entry->max_rate = max_rate; ), - TP_printk("(%s) group=%p tsar_ix=%u bw_share=%u max_rate=%u\n", - __get_str(devname), __entry->group, __entry->tsar_ix, + TP_printk("(%s) node=%p tsar_ix=%u bw_share=%u max_rate=%u\n", + __get_str(devname), __entry->node, __entry->tsar_ix, __entry->bw_share, __entry->max_rate ) ); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index 837c4dda814d..840568c66a1a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -11,12 +11,12 @@ /* Minimum supported BW share value by the HW is 1 Mbit/sec */ #define MLX5_MIN_BW_SHARE 1 -/* Holds rate groups associated with an E-Switch. */ +/* Holds rate nodes associated with an E-Switch. */ struct mlx5_qos_domain { /* Serializes access to all qos changes in the qos domain. */ struct mutex lock; - /* List of all mlx5_esw_rate_groups. */ - struct list_head groups; + /* List of all mlx5_esw_sched_nodes. */ + struct list_head nodes; }; static void esw_qos_lock(struct mlx5_eswitch *esw) @@ -43,7 +43,7 @@ static struct mlx5_qos_domain *esw_qos_domain_alloc(void) return NULL; mutex_init(&qos_domain->lock); - INIT_LIST_HEAD(&qos_domain->groups); + INIT_LIST_HEAD(&qos_domain->nodes); return qos_domain; } @@ -65,30 +65,30 @@ enum sched_node_type { SCHED_NODE_TYPE_VPORTS_TSAR, }; -struct mlx5_esw_rate_group { - u32 tsar_ix; +struct mlx5_esw_sched_node { + u32 ix; /* Bandwidth parameters. */ u32 max_rate; u32 min_rate; - /* A computed value indicating relative min_rate between group members. */ + /* A computed value indicating relative min_rate between node's children. */ u32 bw_share; - /* The parent group of this group. */ - struct mlx5_esw_rate_group *parent; - /* Membership in the parent list. */ - struct list_head parent_entry; - /* The type of this group node in the rate hierarchy. */ + /* The parent node in the rate hierarchy. */ + struct mlx5_esw_sched_node *parent; + /* Entry in the parent node's children list. */ + struct list_head entry; + /* The type of this node in the rate hierarchy. */ enum sched_node_type type; - /* The eswitch this group belongs to. */ + /* The eswitch this node belongs to. */ struct mlx5_eswitch *esw; - /* Members of this group.*/ - struct list_head members; + /* The children nodes of this node, empty list for leaf nodes. */ + struct list_head children; }; -static void esw_qos_vport_set_parent(struct mlx5_vport *vport, struct mlx5_esw_rate_group *parent) +static void esw_qos_vport_set_parent(struct mlx5_vport *vport, struct mlx5_esw_sched_node *parent) { list_del_init(&vport->qos.parent_entry); vport->qos.parent = parent; - list_add_tail(&vport->qos.parent_entry, &parent->members); + list_add_tail(&vport->qos.parent_entry, &parent->children); } static int esw_qos_sched_elem_config(struct mlx5_core_dev *dev, u32 sched_elem_ix, @@ -112,17 +112,17 @@ static int esw_qos_sched_elem_config(struct mlx5_core_dev *dev, u32 sched_elem_i bitmask); } -static int esw_qos_group_config(struct mlx5_esw_rate_group *group, - u32 max_rate, u32 bw_share, struct netlink_ext_ack *extack) +static int esw_qos_node_config(struct mlx5_esw_sched_node *node, + u32 max_rate, u32 bw_share, struct netlink_ext_ack *extack) { - struct mlx5_core_dev *dev = group->esw->dev; + struct mlx5_core_dev *dev = node->esw->dev; int err; - err = esw_qos_sched_elem_config(dev, group->tsar_ix, max_rate, bw_share); + err = esw_qos_sched_elem_config(dev, node->ix, max_rate, bw_share); if (err) - NL_SET_ERR_MSG_MOD(extack, "E-Switch modify group TSAR element failed"); + NL_SET_ERR_MSG_MOD(extack, "E-Switch modify node TSAR element failed"); - trace_mlx5_esw_group_qos_config(dev, group, group->tsar_ix, bw_share, max_rate); + trace_mlx5_esw_node_qos_config(dev, node, node->ix, bw_share, max_rate); return err; } @@ -148,16 +148,16 @@ static int esw_qos_vport_config(struct mlx5_vport *vport, return 0; } -static u32 esw_qos_calculate_group_min_rate_divider(struct mlx5_esw_rate_group *group) +static u32 esw_qos_calculate_node_min_rate_divider(struct mlx5_esw_sched_node *node) { - u32 fw_max_bw_share = MLX5_CAP_QOS(group->esw->dev, max_tsar_bw_share); + u32 fw_max_bw_share = MLX5_CAP_QOS(node->esw->dev, max_tsar_bw_share); struct mlx5_vport *vport; u32 max_guarantee = 0; - /* Find max min_rate across all vports in this group. + /* Find max min_rate across all vports in this node. * This will correspond to fw_max_bw_share in the final bw_share calculation. */ - list_for_each_entry(vport, &group->members, qos.parent_entry) { + list_for_each_entry(vport, &node->children, qos.parent_entry) { if (vport->qos.min_rate > max_guarantee) max_guarantee = vport->qos.min_rate; } @@ -165,13 +165,13 @@ static u32 esw_qos_calculate_group_min_rate_divider(struct mlx5_esw_rate_group * if (max_guarantee) return max_t(u32, max_guarantee / fw_max_bw_share, 1); - /* If vports max min_rate divider is 0 but their group has bw_share + /* If vports max min_rate divider is 0 but their node has bw_share * configured, then set bw_share for vports to minimal value. */ - if (group->bw_share) + if (node->bw_share) return 1; - /* A divider of 0 sets bw_share for all group vports to 0, + /* A divider of 0 sets bw_share for all node vports to 0, * effectively disabling min guarantees. */ return 0; @@ -180,23 +180,23 @@ static u32 esw_qos_calculate_group_min_rate_divider(struct mlx5_esw_rate_group * static u32 esw_qos_calculate_min_rate_divider(struct mlx5_eswitch *esw) { u32 fw_max_bw_share = MLX5_CAP_QOS(esw->dev, max_tsar_bw_share); - struct mlx5_esw_rate_group *group; + struct mlx5_esw_sched_node *node; u32 max_guarantee = 0; - /* Find max min_rate across all esw groups. + /* Find max min_rate across all esw nodes. * This will correspond to fw_max_bw_share in the final bw_share calculation. */ - list_for_each_entry(group, &esw->qos.domain->groups, parent_entry) { - if (group->esw == esw && group->tsar_ix != esw->qos.root_tsar_ix && - group->min_rate > max_guarantee) - max_guarantee = group->min_rate; + list_for_each_entry(node, &esw->qos.domain->nodes, entry) { + if (node->esw == esw && node->ix != esw->qos.root_tsar_ix && + node->min_rate > max_guarantee) + max_guarantee = node->min_rate; } if (max_guarantee) return max_t(u32, max_guarantee / fw_max_bw_share, 1); - /* If no group has min_rate configured, a divider of 0 sets all - * groups' bw_share to 0, effectively disabling min guarantees. + /* If no node has min_rate configured, a divider of 0 sets all + * nodes' bw_share to 0, effectively disabling min guarantees. */ return 0; } @@ -208,16 +208,16 @@ static u32 esw_qos_calc_bw_share(u32 min_rate, u32 divider, u32 fw_max) return min_t(u32, max_t(u32, DIV_ROUND_UP(min_rate, divider), MLX5_MIN_BW_SHARE), fw_max); } -static int esw_qos_normalize_group_min_rate(struct mlx5_esw_rate_group *group, - struct netlink_ext_ack *extack) +static int esw_qos_normalize_node_min_rate(struct mlx5_esw_sched_node *node, + struct netlink_ext_ack *extack) { - u32 fw_max_bw_share = MLX5_CAP_QOS(group->esw->dev, max_tsar_bw_share); - u32 divider = esw_qos_calculate_group_min_rate_divider(group); + u32 fw_max_bw_share = MLX5_CAP_QOS(node->esw->dev, max_tsar_bw_share); + u32 divider = esw_qos_calculate_node_min_rate_divider(node); struct mlx5_vport *vport; u32 bw_share; int err; - list_for_each_entry(vport, &group->members, qos.parent_entry) { + list_for_each_entry(vport, &node->children, qos.parent_entry) { bw_share = esw_qos_calc_bw_share(vport->qos.min_rate, divider, fw_max_bw_share); if (bw_share == vport->qos.bw_share) @@ -237,28 +237,29 @@ static int esw_qos_normalize_min_rate(struct mlx5_eswitch *esw, struct netlink_e { u32 fw_max_bw_share = MLX5_CAP_QOS(esw->dev, max_tsar_bw_share); u32 divider = esw_qos_calculate_min_rate_divider(esw); - struct mlx5_esw_rate_group *group; + struct mlx5_esw_sched_node *node; u32 bw_share; int err; - list_for_each_entry(group, &esw->qos.domain->groups, parent_entry) { - if (group->esw != esw || group->tsar_ix == esw->qos.root_tsar_ix) + list_for_each_entry(node, &esw->qos.domain->nodes, entry) { + if (node->esw != esw || node->ix == esw->qos.root_tsar_ix) continue; - bw_share = esw_qos_calc_bw_share(group->min_rate, divider, fw_max_bw_share); + bw_share = esw_qos_calc_bw_share(node->min_rate, divider, + fw_max_bw_share); - if (bw_share == group->bw_share) + if (bw_share == node->bw_share) continue; - err = esw_qos_group_config(group, group->max_rate, bw_share, extack); + err = esw_qos_node_config(node, node->max_rate, bw_share, extack); if (err) return err; - group->bw_share = bw_share; + node->bw_share = bw_share; - /* All the group's vports need to be set with default bw_share + /* All the node's vports need to be set with default bw_share * to enable them with QOS */ - err = esw_qos_normalize_group_min_rate(group, extack); + err = esw_qos_normalize_node_min_rate(node, extack); if (err) return err; @@ -286,7 +287,7 @@ static int esw_qos_set_vport_min_rate(struct mlx5_vport *vport, previous_min_rate = vport->qos.min_rate; vport->qos.min_rate = min_rate; - err = esw_qos_normalize_group_min_rate(vport->qos.parent, extack); + err = esw_qos_normalize_node_min_rate(vport->qos.parent, extack); if (err) vport->qos.min_rate = previous_min_rate; @@ -309,7 +310,7 @@ static int esw_qos_set_vport_max_rate(struct mlx5_vport *vport, if (max_rate == vport->qos.max_rate) return 0; - /* Use parent group limit if new max rate is 0. */ + /* Use parent node limit if new max rate is 0. */ if (!max_rate) act_max_rate = vport->qos.parent->max_rate; @@ -321,10 +322,10 @@ static int esw_qos_set_vport_max_rate(struct mlx5_vport *vport, return err; } -static int esw_qos_set_group_min_rate(struct mlx5_esw_rate_group *group, - u32 min_rate, struct netlink_ext_ack *extack) +static int esw_qos_set_node_min_rate(struct mlx5_esw_sched_node *node, + u32 min_rate, struct netlink_ext_ack *extack) { - struct mlx5_eswitch *esw = group->esw; + struct mlx5_eswitch *esw = node->esw; u32 previous_min_rate; int err; @@ -332,17 +333,17 @@ static int esw_qos_set_group_min_rate(struct mlx5_esw_rate_group *group, MLX5_CAP_QOS(esw->dev, max_tsar_bw_share) < MLX5_MIN_BW_SHARE) return -EOPNOTSUPP; - if (min_rate == group->min_rate) + if (min_rate == node->min_rate) return 0; - previous_min_rate = group->min_rate; - group->min_rate = min_rate; + previous_min_rate = node->min_rate; + node->min_rate = min_rate; err = esw_qos_normalize_min_rate(esw, extack); if (err) { - NL_SET_ERR_MSG_MOD(extack, "E-Switch group min rate setting failed"); + NL_SET_ERR_MSG_MOD(extack, "E-Switch node min rate setting failed"); /* Attempt restoring previous configuration */ - group->min_rate = previous_min_rate; + node->min_rate = previous_min_rate; if (esw_qos_normalize_min_rate(esw, extack)) NL_SET_ERR_MSG_MOD(extack, "E-Switch BW share restore failed"); } @@ -350,23 +351,23 @@ static int esw_qos_set_group_min_rate(struct mlx5_esw_rate_group *group, return err; } -static int esw_qos_set_group_max_rate(struct mlx5_esw_rate_group *group, - u32 max_rate, struct netlink_ext_ack *extack) +static int esw_qos_set_node_max_rate(struct mlx5_esw_sched_node *node, + u32 max_rate, struct netlink_ext_ack *extack) { struct mlx5_vport *vport; int err; - if (group->max_rate == max_rate) + if (node->max_rate == max_rate) return 0; - err = esw_qos_group_config(group, max_rate, group->bw_share, extack); + err = esw_qos_node_config(node, max_rate, node->bw_share, extack); if (err) return err; - group->max_rate = max_rate; + node->max_rate = max_rate; - /* Any unlimited vports in the group should be set with the value of the group. */ - list_for_each_entry(vport, &group->members, qos.parent_entry) { + /* Any unlimited vports in the node should be set with the value of the node. */ + list_for_each_entry(vport, &node->children, qos.parent_entry) { if (vport->qos.max_rate) continue; @@ -379,8 +380,8 @@ static int esw_qos_set_group_max_rate(struct mlx5_esw_rate_group *group, return err; } -static int esw_qos_create_group_sched_elem(struct mlx5_core_dev *dev, u32 parent_element_id, - u32 *tsar_ix) +static int esw_qos_create_node_sched_elem(struct mlx5_core_dev *dev, u32 parent_element_id, + u32 *tsar_ix) { u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {}; void *attr; @@ -409,7 +410,7 @@ static int esw_qos_create_group_sched_elem(struct mlx5_core_dev *dev, u32 parent static int esw_qos_vport_create_sched_element(struct mlx5_vport *vport, u32 max_rate, u32 bw_share) { - struct mlx5_esw_rate_group *parent = vport->qos.parent; + struct mlx5_esw_sched_node *parent = vport->qos.parent; u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {}; struct mlx5_core_dev *dev = parent->esw->dev; void *attr; @@ -424,7 +425,7 @@ static int esw_qos_vport_create_sched_element(struct mlx5_vport *vport, SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT); attr = MLX5_ADDR_OF(scheduling_context, sched_ctx, element_attributes); MLX5_SET(vport_element, attr, vport_number, vport->vport); - MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent->tsar_ix); + MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent->ix); MLX5_SET(scheduling_context, sched_ctx, max_average_bw, max_rate); MLX5_SET(scheduling_context, sched_ctx, bw_share, bw_share); @@ -442,15 +443,15 @@ static int esw_qos_vport_create_sched_element(struct mlx5_vport *vport, return 0; } -static int esw_qos_update_group_scheduling_element(struct mlx5_vport *vport, - struct mlx5_esw_rate_group *curr_group, - struct mlx5_esw_rate_group *new_group, - struct netlink_ext_ack *extack) +static int esw_qos_update_node_scheduling_element(struct mlx5_vport *vport, + struct mlx5_esw_sched_node *curr_node, + struct mlx5_esw_sched_node *new_node, + struct netlink_ext_ack *extack) { u32 max_rate; int err; - err = mlx5_destroy_scheduling_element_cmd(curr_group->esw->dev, + err = mlx5_destroy_scheduling_element_cmd(curr_node->esw->dev, SCHEDULING_HIERARCHY_E_SWITCH, vport->qos.esw_sched_elem_ix); if (err) { @@ -458,129 +459,129 @@ static int esw_qos_update_group_scheduling_element(struct mlx5_vport *vport, return err; } - esw_qos_vport_set_parent(vport, new_group); - /* Use new group max rate if vport max rate is unlimited. */ - max_rate = vport->qos.max_rate ? vport->qos.max_rate : new_group->max_rate; + esw_qos_vport_set_parent(vport, new_node); + /* Use new node max rate if vport max rate is unlimited. */ + max_rate = vport->qos.max_rate ? vport->qos.max_rate : new_node->max_rate; err = esw_qos_vport_create_sched_element(vport, max_rate, vport->qos.bw_share); if (err) { - NL_SET_ERR_MSG_MOD(extack, "E-Switch vport group set failed."); + NL_SET_ERR_MSG_MOD(extack, "E-Switch vport node set failed."); goto err_sched; } return 0; err_sched: - esw_qos_vport_set_parent(vport, curr_group); - max_rate = vport->qos.max_rate ? vport->qos.max_rate : curr_group->max_rate; + esw_qos_vport_set_parent(vport, curr_node); + max_rate = vport->qos.max_rate ? vport->qos.max_rate : curr_node->max_rate; if (esw_qos_vport_create_sched_element(vport, max_rate, vport->qos.bw_share)) - esw_warn(curr_group->esw->dev, "E-Switch vport group restore failed (vport=%d)\n", + esw_warn(curr_node->esw->dev, "E-Switch vport node restore failed (vport=%d)\n", vport->vport); return err; } -static int esw_qos_vport_update_group(struct mlx5_vport *vport, - struct mlx5_esw_rate_group *group, - struct netlink_ext_ack *extack) +static int esw_qos_vport_update_node(struct mlx5_vport *vport, + struct mlx5_esw_sched_node *node, + struct netlink_ext_ack *extack) { struct mlx5_eswitch *esw = vport->dev->priv.eswitch; - struct mlx5_esw_rate_group *new_group, *curr_group; + struct mlx5_esw_sched_node *new_node, *curr_node; int err; esw_assert_qos_lock_held(esw); - curr_group = vport->qos.parent; - new_group = group ?: esw->qos.group0; - if (curr_group == new_group) + curr_node = vport->qos.parent; + new_node = node ?: esw->qos.node0; + if (curr_node == new_node) return 0; - err = esw_qos_update_group_scheduling_element(vport, curr_group, new_group, extack); + err = esw_qos_update_node_scheduling_element(vport, curr_node, new_node, extack); if (err) return err; - /* Recalculate bw share weights of old and new groups */ - if (vport->qos.bw_share || new_group->bw_share) { - esw_qos_normalize_group_min_rate(curr_group, extack); - esw_qos_normalize_group_min_rate(new_group, extack); + /* Recalculate bw share weights of old and new nodes */ + if (vport->qos.bw_share || new_node->bw_share) { + esw_qos_normalize_node_min_rate(curr_node, extack); + esw_qos_normalize_node_min_rate(new_node, extack); } return 0; } -static struct mlx5_esw_rate_group * -__esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_node_type type, - struct mlx5_esw_rate_group *parent) +static struct mlx5_esw_sched_node * +__esw_qos_alloc_node(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_node_type type, + struct mlx5_esw_sched_node *parent) { - struct mlx5_esw_rate_group *group; - struct list_head *parent_list; + struct list_head *parent_children; + struct mlx5_esw_sched_node *node; - group = kzalloc(sizeof(*group), GFP_KERNEL); - if (!group) + node = kzalloc(sizeof(*node), GFP_KERNEL); + if (!node) return NULL; - group->esw = esw; - group->tsar_ix = tsar_ix; - group->type = type; - group->parent = parent; - INIT_LIST_HEAD(&group->members); - parent_list = parent ? &parent->members : &esw->qos.domain->groups; - list_add_tail(&group->parent_entry, parent_list); + node->esw = esw; + node->ix = tsar_ix; + node->type = type; + node->parent = parent; + INIT_LIST_HEAD(&node->children); + parent_children = parent ? &parent->children : &esw->qos.domain->nodes; + list_add_tail(&node->entry, parent_children); - return group; + return node; } -static void __esw_qos_free_rate_group(struct mlx5_esw_rate_group *group) +static void __esw_qos_free_node(struct mlx5_esw_sched_node *node) { - list_del(&group->parent_entry); - kfree(group); + list_del(&node->entry); + kfree(node); } -static struct mlx5_esw_rate_group * -__esw_qos_create_vports_rate_group(struct mlx5_eswitch *esw, struct mlx5_esw_rate_group *parent, +static struct mlx5_esw_sched_node * +__esw_qos_create_vports_sched_node(struct mlx5_eswitch *esw, struct mlx5_esw_sched_node *parent, struct netlink_ext_ack *extack) { - struct mlx5_esw_rate_group *group; + struct mlx5_esw_sched_node *node; u32 tsar_ix; int err; - err = esw_qos_create_group_sched_elem(esw->dev, esw->qos.root_tsar_ix, &tsar_ix); + err = esw_qos_create_node_sched_elem(esw->dev, esw->qos.root_tsar_ix, &tsar_ix); if (err) { - NL_SET_ERR_MSG_MOD(extack, "E-Switch create TSAR for group failed"); + NL_SET_ERR_MSG_MOD(extack, "E-Switch create TSAR for node failed"); return ERR_PTR(err); } - group = __esw_qos_alloc_rate_group(esw, tsar_ix, SCHED_NODE_TYPE_VPORTS_TSAR, parent); - if (!group) { - NL_SET_ERR_MSG_MOD(extack, "E-Switch alloc group failed"); + node = __esw_qos_alloc_node(esw, tsar_ix, SCHED_NODE_TYPE_VPORTS_TSAR, parent); + if (!node) { + NL_SET_ERR_MSG_MOD(extack, "E-Switch alloc node failed"); err = -ENOMEM; - goto err_alloc_group; + goto err_alloc_node; } err = esw_qos_normalize_min_rate(esw, extack); if (err) { - NL_SET_ERR_MSG_MOD(extack, "E-Switch groups normalization failed"); + NL_SET_ERR_MSG_MOD(extack, "E-Switch nodes normalization failed"); goto err_min_rate; } - trace_mlx5_esw_group_qos_create(esw->dev, group, group->tsar_ix); + trace_mlx5_esw_node_qos_create(esw->dev, node, node->ix); - return group; + return node; err_min_rate: - __esw_qos_free_rate_group(group); -err_alloc_group: + __esw_qos_free_node(node); +err_alloc_node: if (mlx5_destroy_scheduling_element_cmd(esw->dev, SCHEDULING_HIERARCHY_E_SWITCH, tsar_ix)) - NL_SET_ERR_MSG_MOD(extack, "E-Switch destroy TSAR for group failed"); + NL_SET_ERR_MSG_MOD(extack, "E-Switch destroy TSAR for node failed"); return ERR_PTR(err); } static int esw_qos_get(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack); static void esw_qos_put(struct mlx5_eswitch *esw); -static struct mlx5_esw_rate_group * -esw_qos_create_vports_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack) +static struct mlx5_esw_sched_node * +esw_qos_create_vports_sched_node(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack) { - struct mlx5_esw_rate_group *group; + struct mlx5_esw_sched_node *node; int err; esw_assert_qos_lock_held(esw); @@ -591,31 +592,30 @@ esw_qos_create_vports_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ac if (err) return ERR_PTR(err); - group = __esw_qos_create_vports_rate_group(esw, NULL, extack); - if (IS_ERR(group)) + node = __esw_qos_create_vports_sched_node(esw, NULL, extack); + if (IS_ERR(node)) esw_qos_put(esw); - return group; + return node; } -static int __esw_qos_destroy_rate_group(struct mlx5_esw_rate_group *group, - struct netlink_ext_ack *extack) +static int __esw_qos_destroy_node(struct mlx5_esw_sched_node *node, struct netlink_ext_ack *extack) { - struct mlx5_eswitch *esw = group->esw; + struct mlx5_eswitch *esw = node->esw; int err; - trace_mlx5_esw_group_qos_destroy(esw->dev, group, group->tsar_ix); + trace_mlx5_esw_node_qos_destroy(esw->dev, node, node->ix); err = mlx5_destroy_scheduling_element_cmd(esw->dev, SCHEDULING_HIERARCHY_E_SWITCH, - group->tsar_ix); + node->ix); if (err) NL_SET_ERR_MSG_MOD(extack, "E-Switch destroy TSAR_ID failed"); - __esw_qos_free_rate_group(group); + __esw_qos_free_node(node); err = esw_qos_normalize_min_rate(esw, extack); if (err) - NL_SET_ERR_MSG_MOD(extack, "E-Switch groups normalization failed"); + NL_SET_ERR_MSG_MOD(extack, "E-Switch nodes normalization failed"); return err; @@ -629,32 +629,34 @@ static int esw_qos_create(struct mlx5_eswitch *esw, struct netlink_ext_ack *exta if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling)) return -EOPNOTSUPP; - err = esw_qos_create_group_sched_elem(esw->dev, 0, &esw->qos.root_tsar_ix); + err = esw_qos_create_node_sched_elem(esw->dev, 0, &esw->qos.root_tsar_ix); if (err) { esw_warn(dev, "E-Switch create root TSAR failed (%d)\n", err); return err; } if (MLX5_CAP_QOS(dev, log_esw_max_sched_depth)) { - esw->qos.group0 = __esw_qos_create_vports_rate_group(esw, NULL, extack); + esw->qos.node0 = __esw_qos_create_vports_sched_node(esw, NULL, extack); } else { - /* The eswitch doesn't support scheduling groups. - * Create a software-only group0 using the root TSAR to attach vport QoS to. + /* The eswitch doesn't support scheduling nodes. + * Create a software-only node0 using the root TSAR to attach vport QoS to. */ - if (!__esw_qos_alloc_rate_group(esw, esw->qos.root_tsar_ix, - SCHED_NODE_TYPE_VPORTS_TSAR, NULL)) - esw->qos.group0 = ERR_PTR(-ENOMEM); + if (!__esw_qos_alloc_node(esw, + esw->qos.root_tsar_ix, + SCHED_NODE_TYPE_VPORTS_TSAR, + NULL)) + esw->qos.node0 = ERR_PTR(-ENOMEM); } - if (IS_ERR(esw->qos.group0)) { - err = PTR_ERR(esw->qos.group0); - esw_warn(dev, "E-Switch create rate group 0 failed (%d)\n", err); - goto err_group0; + if (IS_ERR(esw->qos.node0)) { + err = PTR_ERR(esw->qos.node0); + esw_warn(dev, "E-Switch create rate node 0 failed (%d)\n", err); + goto err_node0; } refcount_set(&esw->qos.refcnt, 1); return 0; -err_group0: +err_node0: if (mlx5_destroy_scheduling_element_cmd(esw->dev, SCHEDULING_HIERARCHY_E_SWITCH, esw->qos.root_tsar_ix)) esw_warn(esw->dev, "E-Switch destroy root TSAR failed.\n"); @@ -666,11 +668,11 @@ static void esw_qos_destroy(struct mlx5_eswitch *esw) { int err; - if (esw->qos.group0->tsar_ix != esw->qos.root_tsar_ix) - __esw_qos_destroy_rate_group(esw->qos.group0, NULL); + if (esw->qos.node0->ix != esw->qos.root_tsar_ix) + __esw_qos_destroy_node(esw->qos.node0, NULL); else - __esw_qos_free_rate_group(esw->qos.group0); - esw->qos.group0 = NULL; + __esw_qos_free_node(esw->qos.node0); + esw->qos.node0 = NULL; err = mlx5_destroy_scheduling_element_cmd(esw->dev, SCHEDULING_HIERARCHY_E_SWITCH, @@ -716,7 +718,7 @@ static int esw_qos_vport_enable(struct mlx5_vport *vport, return err; INIT_LIST_HEAD(&vport->qos.parent_entry); - esw_qos_vport_set_parent(vport, esw->qos.group0); + esw_qos_vport_set_parent(vport, esw->qos.node0); err = esw_qos_vport_create_sched_element(vport, max_rate, bw_share); if (err) @@ -743,8 +745,8 @@ void mlx5_esw_qos_vport_disable(struct mlx5_vport *vport) esw_qos_lock(esw); if (!vport->qos.enabled) goto unlock; - WARN(vport->qos.parent != esw->qos.group0, - "Disabling QoS on port before detaching it from group"); + WARN(vport->qos.parent != esw->qos.node0, + "Disabling QoS on port before detaching it from node"); dev = vport->qos.parent->esw->dev; err = mlx5_destroy_scheduling_element_cmd(dev, @@ -1004,8 +1006,8 @@ int mlx5_esw_devlink_rate_leaf_tx_max_set(struct devlink_rate *rate_leaf, void * int mlx5_esw_devlink_rate_node_tx_share_set(struct devlink_rate *rate_node, void *priv, u64 tx_share, struct netlink_ext_ack *extack) { - struct mlx5_esw_rate_group *group = priv; - struct mlx5_eswitch *esw = group->esw; + struct mlx5_esw_sched_node *node = priv; + struct mlx5_eswitch *esw = node->esw; int err; err = esw_qos_devlink_rate_to_mbps(esw->dev, "tx_share", &tx_share, extack); @@ -1013,7 +1015,7 @@ int mlx5_esw_devlink_rate_node_tx_share_set(struct devlink_rate *rate_node, void return err; esw_qos_lock(esw); - err = esw_qos_set_group_min_rate(group, tx_share, extack); + err = esw_qos_set_node_min_rate(node, tx_share, extack); esw_qos_unlock(esw); return err; } @@ -1021,8 +1023,8 @@ int mlx5_esw_devlink_rate_node_tx_share_set(struct devlink_rate *rate_node, void int mlx5_esw_devlink_rate_node_tx_max_set(struct devlink_rate *rate_node, void *priv, u64 tx_max, struct netlink_ext_ack *extack) { - struct mlx5_esw_rate_group *group = priv; - struct mlx5_eswitch *esw = group->esw; + struct mlx5_esw_sched_node *node = priv; + struct mlx5_eswitch *esw = node->esw; int err; err = esw_qos_devlink_rate_to_mbps(esw->dev, "tx_max", &tx_max, extack); @@ -1030,7 +1032,7 @@ int mlx5_esw_devlink_rate_node_tx_max_set(struct devlink_rate *rate_node, void * return err; esw_qos_lock(esw); - err = esw_qos_set_group_max_rate(group, tx_max, extack); + err = esw_qos_set_node_max_rate(node, tx_max, extack); esw_qos_unlock(esw); return err; } @@ -1038,7 +1040,7 @@ int mlx5_esw_devlink_rate_node_tx_max_set(struct devlink_rate *rate_node, void * int mlx5_esw_devlink_rate_node_new(struct devlink_rate *rate_node, void **priv, struct netlink_ext_ack *extack) { - struct mlx5_esw_rate_group *group; + struct mlx5_esw_sched_node *node; struct mlx5_eswitch *esw; int err = 0; @@ -1054,13 +1056,13 @@ int mlx5_esw_devlink_rate_node_new(struct devlink_rate *rate_node, void **priv, goto unlock; } - group = esw_qos_create_vports_rate_group(esw, extack); - if (IS_ERR(group)) { - err = PTR_ERR(group); + node = esw_qos_create_vports_sched_node(esw, extack); + if (IS_ERR(node)) { + err = PTR_ERR(node); goto unlock; } - *priv = group; + *priv = node; unlock: esw_qos_unlock(esw); return err; @@ -1069,36 +1071,36 @@ int mlx5_esw_devlink_rate_node_new(struct devlink_rate *rate_node, void **priv, int mlx5_esw_devlink_rate_node_del(struct devlink_rate *rate_node, void *priv, struct netlink_ext_ack *extack) { - struct mlx5_esw_rate_group *group = priv; - struct mlx5_eswitch *esw = group->esw; + struct mlx5_esw_sched_node *node = priv; + struct mlx5_eswitch *esw = node->esw; int err; esw_qos_lock(esw); - err = __esw_qos_destroy_rate_group(group, extack); + err = __esw_qos_destroy_node(node, extack); esw_qos_put(esw); esw_qos_unlock(esw); return err; } -int mlx5_esw_qos_vport_update_group(struct mlx5_vport *vport, - struct mlx5_esw_rate_group *group, - struct netlink_ext_ack *extack) +int mlx5_esw_qos_vport_update_node(struct mlx5_vport *vport, + struct mlx5_esw_sched_node *node, + struct netlink_ext_ack *extack) { struct mlx5_eswitch *esw = vport->dev->priv.eswitch; int err = 0; - if (group && group->esw != esw) { + if (node && node->esw != esw) { NL_SET_ERR_MSG_MOD(extack, "Cross E-Switch scheduling is not supported"); return -EOPNOTSUPP; } esw_qos_lock(esw); - if (!vport->qos.enabled && !group) + if (!vport->qos.enabled && !node) goto unlock; err = esw_qos_vport_enable(vport, 0, 0, extack); if (!err) - err = esw_qos_vport_update_group(vport, group, extack); + err = esw_qos_vport_update_node(vport, node, extack); unlock: esw_qos_unlock(esw); return err; @@ -1109,12 +1111,12 @@ int mlx5_esw_devlink_rate_parent_set(struct devlink_rate *devlink_rate, void *priv, void *parent_priv, struct netlink_ext_ack *extack) { - struct mlx5_esw_rate_group *group; + struct mlx5_esw_sched_node *node; struct mlx5_vport *vport = priv; if (!parent) - return mlx5_esw_qos_vport_update_group(vport, NULL, extack); + return mlx5_esw_qos_vport_update_node(vport, NULL, extack); - group = parent_priv; - return mlx5_esw_qos_vport_update_group(vport, group, extack); + node = parent_priv; + return mlx5_esw_qos_vport_update_node(vport, node, extack); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h index e789fb14989b..38f912f5a707 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -222,7 +222,7 @@ struct mlx5_vport { /* A computed value indicating relative min_rate between vports in a group. */ u32 bw_share; /* The parent group of this vport scheduling element. */ - struct mlx5_esw_rate_group *parent; + struct mlx5_esw_sched_node *parent; /* Membership in the parent 'members' list. */ struct list_head parent_entry; } qos; @@ -372,11 +372,11 @@ struct mlx5_eswitch { refcount_t refcnt; u32 root_tsar_ix; struct mlx5_qos_domain *domain; - /* Contains all vports with QoS enabled but no explicit group. - * Cannot be NULL if QoS is enabled, but may be a fake group - * referencing the root TSAR if the esw doesn't support groups. + /* Contains all vports with QoS enabled but no explicit node. + * Cannot be NULL if QoS is enabled, but may be a fake node + * referencing the root TSAR if the esw doesn't support nodes. */ - struct mlx5_esw_rate_group *group0; + struct mlx5_esw_sched_node *node0; } qos; struct mlx5_esw_bridge_offloads *br_offloads; @@ -436,9 +436,9 @@ int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, u16 vport_num, bool setting); int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport, u32 max_rate, u32 min_rate); -int mlx5_esw_qos_vport_update_group(struct mlx5_vport *vport, - struct mlx5_esw_rate_group *group, - struct netlink_ext_ack *extack); +int mlx5_esw_qos_vport_update_node(struct mlx5_vport *vport, + struct mlx5_esw_sched_node *node, + struct netlink_ext_ack *extack); int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting); int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting); int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, From patchwork Wed Oct 16 17:36:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13838677 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2047.outbound.protection.outlook.com [40.107.244.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55D7214A4E2 for ; Wed, 16 Oct 2024 17:37:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Tariq Toukan Subject: [PATCH net-next V3 07/15] net/mlx5: Refactor vport scheduling element creation function Date: Wed, 16 Oct 2024 20:36:09 +0300 Message-ID: <20241016173617.217736-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004682:EE_|LV2PR12MB5967:EE_ X-MS-Office365-Filtering-Correlation-Id: e2cfbfb3-c107-4200-8887-08dcee093edd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: sz62T5BNCAWPnBJB1XAcU7JPra2ANJVQosAPEuV1TonMjQyeBBtS94lg+eFVnLfpBfdSIZ1GQAtG59atLtBBRhlHSepN8N23dx+Hi42W36jVsed9chTQyOKono76e0yaR21nTyNQVG+9CooJGKSgShsKeOMeOgrD++msHRQpHV29b/ZxVOfdeTDS9l/zrhm+Co1i8l9X6ydqstBGG0sFh+AAPPpLO8c+9XWRwsNCGFjof7DAzmG50oCfrIG5zfNaB/IS+vkthKr4rvm4dTgSYUSOwBubrBZUMBTY2CuawBPwCijTLOlK2kwn79XtTS0TbAIfPrJMIskZ29FuZ13ccaKttKIE8zwZ35zMSxGSmGxTtAzuKGVPR4vkfm+ETJXR2BFRTl1BASwGQwPIjnkc7uigekD+SjXYfghPtt1+haTAETH+3pXiiDbQEVxzNBy9KwjSzCHRtbBGPBgY9Njf5Cc1bBFl0pvzJEuMBF7pnV8GLSu9Z+P/C/TOfD7rNlWu+77Rg7hlud53DlQLcHev9h5CsFjOjYeJTHIDO2suzc6Np/J0h84ONZ/vSqEEey9rocRZjEkSqPx8fBuNzYseJm2lclzHDSQ/oKvS6mYZLFxoLDOKv9CgaJqWKJIMIMNIvJUUuDor3ueDsb7vV21tW4yAzCR5Hj+lPE9rwJ8lI9Fq+CCLoJWetJgW4WU6esCsRbcmPdfggmDX4XBoYBduuICSWw55QNf/2RQZ4awRUsTRKxed93+UpUVwlzm6am6o/CWsd+XZ33CRCw972xa6djb/4/ZMt/64OVvgEiciCC4Lh5r7v75MKljMaNiG4apqU4CBPo1MO+RI0mGXrEMZkbk2oiySMwFQKw5DUW8puKLBPJvPhP36T1DzXsWEef7S7kAp562gKm1jKzxOp2x4tPMgo5RU8b3XSP0RZSoVsYbkIN+w41sObI2vn+d1ydF+tbyui/PX0uAA7Ho2wdykXgvUyAp5kU/6ObDEIHqgto1x1/w/8b3zCeZakXauNPO1R6gSez8azqKLYW09znFtETITks94nKyN+YxwfrN3yeJTZKBz/MAAOVhKfpVZ/GwF5nEaTqmg124blC9x3OvTHlqrc0ID44pQtCH5s3cBgw9uazbd5geBcwa/I6CQeYt9JZhSudn2AgQLZ0rJ+EaYSod5bdejpH8fOpahVeKHHsGmzXc0ZDseKcchl6vm8mk6IESSxVnM0u3ljJY+gNXysky4SsL3qxc0reTBGyWB0Zd8q3Ro1suC8MPSKn+lvD/VN/5M/LCV477UKoGEKQ9S3WCEFoMZT0tgQvkmR+uY9BtyHcV0hkwKCdROycV9YsJOpL+zRfc82IaaPMPd928fOG6Tnv5sd/IgT1iC6yRr8cQ= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:37:45.4558 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2cfbfb3-c107-4200-8887-08dcee093edd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004682.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5967 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Modify the vport scheduling element creation function to get the parent node directly, aligning it with the group creation function. This ensures a consistent flow for scheduling elements creation, as the parent nodes already contain the device and parent element index. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 27 ++++++++++--------- 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index 840568c66a1a..bcdb745994d2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -407,10 +407,10 @@ static int esw_qos_create_node_sched_elem(struct mlx5_core_dev *dev, u32 parent_ tsar_ix); } -static int esw_qos_vport_create_sched_element(struct mlx5_vport *vport, - u32 max_rate, u32 bw_share) +static int +esw_qos_vport_create_sched_element(struct mlx5_vport *vport, struct mlx5_esw_sched_node *parent, + u32 max_rate, u32 bw_share, u32 *sched_elem_ix) { - struct mlx5_esw_sched_node *parent = vport->qos.parent; u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {}; struct mlx5_core_dev *dev = parent->esw->dev; void *attr; @@ -432,7 +432,7 @@ static int esw_qos_vport_create_sched_element(struct mlx5_vport *vport, err = mlx5_create_scheduling_element_cmd(dev, SCHEDULING_HIERARCHY_E_SWITCH, sched_ctx, - &vport->qos.esw_sched_elem_ix); + sched_elem_ix); if (err) { esw_warn(dev, "E-Switch create vport scheduling element failed (vport=%d,err=%d)\n", @@ -459,21 +459,23 @@ static int esw_qos_update_node_scheduling_element(struct mlx5_vport *vport, return err; } - esw_qos_vport_set_parent(vport, new_node); /* Use new node max rate if vport max rate is unlimited. */ max_rate = vport->qos.max_rate ? vport->qos.max_rate : new_node->max_rate; - err = esw_qos_vport_create_sched_element(vport, max_rate, vport->qos.bw_share); + err = esw_qos_vport_create_sched_element(vport, new_node, max_rate, vport->qos.bw_share, + &vport->qos.esw_sched_elem_ix); if (err) { NL_SET_ERR_MSG_MOD(extack, "E-Switch vport node set failed."); goto err_sched; } + esw_qos_vport_set_parent(vport, new_node); + return 0; err_sched: - esw_qos_vport_set_parent(vport, curr_node); max_rate = vport->qos.max_rate ? vport->qos.max_rate : curr_node->max_rate; - if (esw_qos_vport_create_sched_element(vport, max_rate, vport->qos.bw_share)) + if (esw_qos_vport_create_sched_element(vport, curr_node, max_rate, vport->qos.bw_share, + &vport->qos.esw_sched_elem_ix)) esw_warn(curr_node->esw->dev, "E-Switch vport node restore failed (vport=%d)\n", vport->vport); @@ -717,13 +719,14 @@ static int esw_qos_vport_enable(struct mlx5_vport *vport, if (err) return err; - INIT_LIST_HEAD(&vport->qos.parent_entry); - esw_qos_vport_set_parent(vport, esw->qos.node0); - - err = esw_qos_vport_create_sched_element(vport, max_rate, bw_share); + err = esw_qos_vport_create_sched_element(vport, esw->qos.node0, max_rate, bw_share, + &vport->qos.esw_sched_elem_ix); if (err) goto err_out; + INIT_LIST_HEAD(&vport->qos.parent_entry); + esw_qos_vport_set_parent(vport, esw->qos.node0); + vport->qos.enabled = true; trace_mlx5_esw_vport_qos_create(vport->dev, vport, bw_share, max_rate); From patchwork Wed Oct 16 17:36:10 2024 Content-Type: text/plain; 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Wed, 16 Oct 2024 10:37:30 -0700 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Tariq Toukan Subject: [PATCH net-next V3 08/15] net/mlx5: Refactor vport QoS to use scheduling node structure Date: Wed, 16 Oct 2024 20:36:10 +0300 Message-ID: <20241016173617.217736-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004680:EE_|DS0PR12MB7780:EE_ X-MS-Office365-Filtering-Correlation-Id: afa4925a-6a2d-411e-e631-08dcee09420a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: yIWSTxlNuHwwaVJd1SRT2L0rUifY8e7SQlVgL0ZFfPso3T/Mbh5jWE7jGFUTLW/ZPXzB7GOWzP3FgJDdMGVGTZvyPpgzuAMYF5m/6RkeSSB5xQJTyloRgR0Y6BPDGRDsceh0uxZIR9k8DxWUZT1pcZeo31TvBO/eB9JlItqWpSuwn6g2JpiOz9Vq1ifcPmRLxVeiHnoMsu7/e4i6lt83QkEgb9RX7m7/rVrGkBDIKfZFdaRTSM/+i1DZ4aUrtomcAOjLGcSgijxFj1F7/5mKUbiBNau0elUaLKoj08zcQ62rg9mK0YccFTdSFdecVFcdBh59UWw9H9MO0Ca/9zLBrFUe9Ps6I4omGZ/9p02dlpLTsjtP4X3stGQajs0Dsur/lLiFBxFOVTrCwUW4BRGGfHin5i5W+OkbKFAgVF2pJIVv8TLlIwFca1S8caSPHKJVYjCIZUROggN6uVWRU0dNv3wzSJYsxfWEE45t8n1UBmt5I7csACcQalORc/HKG/aEC87BkTRHNe5J6oRcAKIkdfXknibGwIVWZqWJSJ+gvuZX97JYXW8UKGIxKnTAvcuPbfiMyn7hdgvCvMe6vkGtz9bFPlZWfLb8ICEgdW31CVzbRH5OkcSNMhfe/9L2ip30uY3vo3l6HGYm6/JKU3yXnLo+x3JKkuEKJXQXdFHzh6IWvQqpH7O7qMou7dhyQw5P+33eVLYVTWFMdL3c6/fgXoI725snwIiloZvLCwIa4NtLKCLw37/n+7Yfzbvd7MXXA4yW5YLsX2PKA/yDrBCrfX54ndht7E8IteaIPGap8NvgjJAulMzeZD3Z1Y9v+62zxddeg5HiM+mJDa96tuY4ofnIyVOw4RAalTRlz3hmsLmfIEWyO6/UQ0rBjI42pReSX7mFHZ0phyu7aacaw3BLi7+t7xDosqjaioQuQ69jx/b+J//XFhhuDbKjxTgXRUue4G/ydTrLUuSqBSG9eIOuwZlqjtpW+qrbqmCtF91PtFZBddowzeoQVuLK8dOzFeCzhXUSrVUgXV0tEMNyAgb6/B2rOKiQ2SteemxeDcTKx1YKDTLh2CNSvAFeLUE4bXFXii/yS3/W2FarZLhdnjZszYRur8vmKDHO+QSHKnBdBTmtFTjG4IPdrk1ZclklSb/VzzZIT1RUmCiK0aZ6VMvetNR9JMC8mzXRF/3rewBHejn7OzXIwUR3WSrmh2qvfLkoqW7gz8N47YufJ1hKVL6LQm6XYpK8btBgQ5AhH4QCcRhIvepsV5EttuEey/xu5jj4TkcSuraloLNvBwErL7A/aqegEsVughVJtbH6AqPwDVgvCItQ4rr28+Cht8x3g5E/WatCOsCYv9Wzf+ZUjgjSciB5TVtBvyCeGN4Ca0JMlDFk1A6Qy9t+i2BycLQ4J9Zf X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:37:50.7863 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: afa4925a-6a2d-411e-e631-08dcee09420a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004680.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7780 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Refactor the vport QoS structure by moving group membership and scheduling details into the `mlx5_esw_sched_node` structure. This change consolidates the vport into the rate hierarchy by unifying the handling of different types of scheduling element nodes. In addition, add a direct reference to the mlx5_vport within the mlx5_esw_sched_node structure, to ensure that the vport is easily accessible when a scheduling node is associated with a vport. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../mlx5/core/esw/diag/qos_tracepoint.h | 7 +- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 154 +++++++++++------- .../net/ethernet/mellanox/mlx5/core/esw/qos.h | 3 + .../net/ethernet/mellanox/mlx5/core/eswitch.c | 2 + .../net/ethernet/mellanox/mlx5/core/eswitch.h | 11 +- 5 files changed, 110 insertions(+), 67 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/diag/qos_tracepoint.h b/drivers/net/ethernet/mellanox/mlx5/core/esw/diag/qos_tracepoint.h index 0b50ef0871f2..43550a416a6f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/diag/qos_tracepoint.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/diag/qos_tracepoint.h @@ -9,6 +9,7 @@ #include #include "eswitch.h" +#include "qos.h" TRACE_EVENT(mlx5_esw_vport_qos_destroy, TP_PROTO(const struct mlx5_core_dev *dev, const struct mlx5_vport *vport), @@ -19,7 +20,7 @@ TRACE_EVENT(mlx5_esw_vport_qos_destroy, ), TP_fast_assign(__assign_str(devname); __entry->vport_id = vport->vport; - __entry->sched_elem_ix = vport->qos.esw_sched_elem_ix; + __entry->sched_elem_ix = mlx5_esw_qos_vport_get_sched_elem_ix(vport); ), TP_printk("(%s) vport=%hu sched_elem_ix=%u\n", __get_str(devname), __entry->vport_id, __entry->sched_elem_ix @@ -39,10 +40,10 @@ DECLARE_EVENT_CLASS(mlx5_esw_vport_qos_template, ), TP_fast_assign(__assign_str(devname); __entry->vport_id = vport->vport; - __entry->sched_elem_ix = vport->qos.esw_sched_elem_ix; + __entry->sched_elem_ix = mlx5_esw_qos_vport_get_sched_elem_ix(vport); __entry->bw_share = bw_share; __entry->max_rate = max_rate; - __entry->parent = vport->qos.parent; + __entry->parent = mlx5_esw_qos_vport_get_parent(vport); ), TP_printk("(%s) vport=%hu sched_elem_ix=%u bw_share=%u, max_rate=%u parent=%p\n", __get_str(devname), __entry->vport_id, __entry->sched_elem_ix, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index bcdb745994d2..2d10453afc8a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -63,6 +63,7 @@ static void esw_qos_domain_release(struct mlx5_eswitch *esw) enum sched_node_type { SCHED_NODE_TYPE_VPORTS_TSAR, + SCHED_NODE_TYPE_VPORT, }; struct mlx5_esw_sched_node { @@ -82,13 +83,34 @@ struct mlx5_esw_sched_node { struct mlx5_eswitch *esw; /* The children nodes of this node, empty list for leaf nodes. */ struct list_head children; + /* Valid only if this node is associated with a vport. */ + struct mlx5_vport *vport; }; -static void esw_qos_vport_set_parent(struct mlx5_vport *vport, struct mlx5_esw_sched_node *parent) +static void +esw_qos_node_set_parent(struct mlx5_esw_sched_node *node, struct mlx5_esw_sched_node *parent) { - list_del_init(&vport->qos.parent_entry); - vport->qos.parent = parent; - list_add_tail(&vport->qos.parent_entry, &parent->children); + list_del_init(&node->entry); + node->parent = parent; + list_add_tail(&node->entry, &parent->children); + node->esw = parent->esw; +} + +u32 mlx5_esw_qos_vport_get_sched_elem_ix(const struct mlx5_vport *vport) +{ + if (!vport->qos.sched_node) + return 0; + + return vport->qos.sched_node->ix; +} + +struct mlx5_esw_sched_node * +mlx5_esw_qos_vport_get_parent(const struct mlx5_vport *vport) +{ + if (!vport->qos.sched_node) + return NULL; + + return vport->qos.sched_node->parent; } static int esw_qos_sched_elem_config(struct mlx5_core_dev *dev, u32 sched_elem_ix, @@ -131,10 +153,11 @@ static int esw_qos_vport_config(struct mlx5_vport *vport, u32 max_rate, u32 bw_share, struct netlink_ext_ack *extack) { - struct mlx5_core_dev *dev = vport->qos.parent->esw->dev; + struct mlx5_esw_sched_node *vport_node = vport->qos.sched_node; + struct mlx5_core_dev *dev = vport_node->parent->esw->dev; int err; - err = esw_qos_sched_elem_config(dev, vport->qos.esw_sched_elem_ix, max_rate, bw_share); + err = esw_qos_sched_elem_config(dev, vport_node->ix, max_rate, bw_share); if (err) { esw_warn(dev, "E-Switch modify vport scheduling element failed (vport=%d,err=%d)\n", @@ -151,15 +174,15 @@ static int esw_qos_vport_config(struct mlx5_vport *vport, static u32 esw_qos_calculate_node_min_rate_divider(struct mlx5_esw_sched_node *node) { u32 fw_max_bw_share = MLX5_CAP_QOS(node->esw->dev, max_tsar_bw_share); - struct mlx5_vport *vport; + struct mlx5_esw_sched_node *vport_node; u32 max_guarantee = 0; /* Find max min_rate across all vports in this node. * This will correspond to fw_max_bw_share in the final bw_share calculation. */ - list_for_each_entry(vport, &node->children, qos.parent_entry) { - if (vport->qos.min_rate > max_guarantee) - max_guarantee = vport->qos.min_rate; + list_for_each_entry(vport_node, &node->children, entry) { + if (vport_node->min_rate > max_guarantee) + max_guarantee = vport_node->min_rate; } if (max_guarantee) @@ -213,21 +236,22 @@ static int esw_qos_normalize_node_min_rate(struct mlx5_esw_sched_node *node, { u32 fw_max_bw_share = MLX5_CAP_QOS(node->esw->dev, max_tsar_bw_share); u32 divider = esw_qos_calculate_node_min_rate_divider(node); - struct mlx5_vport *vport; + struct mlx5_esw_sched_node *vport_node; u32 bw_share; int err; - list_for_each_entry(vport, &node->children, qos.parent_entry) { - bw_share = esw_qos_calc_bw_share(vport->qos.min_rate, divider, fw_max_bw_share); + list_for_each_entry(vport_node, &node->children, entry) { + bw_share = esw_qos_calc_bw_share(vport_node->min_rate, divider, fw_max_bw_share); - if (bw_share == vport->qos.bw_share) + if (bw_share == vport_node->bw_share) continue; - err = esw_qos_vport_config(vport, vport->qos.max_rate, bw_share, extack); + err = esw_qos_vport_config(vport_node->vport, vport_node->max_rate, bw_share, + extack); if (err) return err; - vport->qos.bw_share = bw_share; + vport_node->bw_share = bw_share; } return 0; @@ -271,25 +295,25 @@ static int esw_qos_normalize_min_rate(struct mlx5_eswitch *esw, struct netlink_e static int esw_qos_set_vport_min_rate(struct mlx5_vport *vport, u32 min_rate, struct netlink_ext_ack *extack) { - struct mlx5_eswitch *esw = vport->dev->priv.eswitch; + struct mlx5_esw_sched_node *vport_node = vport->qos.sched_node; u32 fw_max_bw_share, previous_min_rate; bool min_rate_supported; int err; - esw_assert_qos_lock_held(esw); + esw_assert_qos_lock_held(vport_node->esw); fw_max_bw_share = MLX5_CAP_QOS(vport->dev, max_tsar_bw_share); min_rate_supported = MLX5_CAP_QOS(vport->dev, esw_bw_share) && fw_max_bw_share >= MLX5_MIN_BW_SHARE; if (min_rate && !min_rate_supported) return -EOPNOTSUPP; - if (min_rate == vport->qos.min_rate) + if (min_rate == vport_node->min_rate) return 0; - previous_min_rate = vport->qos.min_rate; - vport->qos.min_rate = min_rate; - err = esw_qos_normalize_node_min_rate(vport->qos.parent, extack); + previous_min_rate = vport_node->min_rate; + vport_node->min_rate = min_rate; + err = esw_qos_normalize_node_min_rate(vport_node->parent, extack); if (err) - vport->qos.min_rate = previous_min_rate; + vport_node->min_rate = previous_min_rate; return err; } @@ -297,27 +321,27 @@ static int esw_qos_set_vport_min_rate(struct mlx5_vport *vport, static int esw_qos_set_vport_max_rate(struct mlx5_vport *vport, u32 max_rate, struct netlink_ext_ack *extack) { - struct mlx5_eswitch *esw = vport->dev->priv.eswitch; + struct mlx5_esw_sched_node *vport_node = vport->qos.sched_node; u32 act_max_rate = max_rate; bool max_rate_supported; int err; - esw_assert_qos_lock_held(esw); + esw_assert_qos_lock_held(vport_node->esw); max_rate_supported = MLX5_CAP_QOS(vport->dev, esw_rate_limit); if (max_rate && !max_rate_supported) return -EOPNOTSUPP; - if (max_rate == vport->qos.max_rate) + if (max_rate == vport_node->max_rate) return 0; /* Use parent node limit if new max rate is 0. */ if (!max_rate) - act_max_rate = vport->qos.parent->max_rate; + act_max_rate = vport_node->parent->max_rate; - err = esw_qos_vport_config(vport, act_max_rate, vport->qos.bw_share, extack); + err = esw_qos_vport_config(vport, act_max_rate, vport_node->bw_share, extack); if (!err) - vport->qos.max_rate = max_rate; + vport_node->max_rate = max_rate; return err; } @@ -354,7 +378,7 @@ static int esw_qos_set_node_min_rate(struct mlx5_esw_sched_node *node, static int esw_qos_set_node_max_rate(struct mlx5_esw_sched_node *node, u32 max_rate, struct netlink_ext_ack *extack) { - struct mlx5_vport *vport; + struct mlx5_esw_sched_node *vport_node; int err; if (node->max_rate == max_rate) @@ -367,11 +391,12 @@ static int esw_qos_set_node_max_rate(struct mlx5_esw_sched_node *node, node->max_rate = max_rate; /* Any unlimited vports in the node should be set with the value of the node. */ - list_for_each_entry(vport, &node->children, qos.parent_entry) { - if (vport->qos.max_rate) + list_for_each_entry(vport_node, &node->children, entry) { + if (vport_node->max_rate) continue; - err = esw_qos_vport_config(vport, max_rate, vport->qos.bw_share, extack); + err = esw_qos_vport_config(vport_node->vport, max_rate, vport_node->bw_share, + extack); if (err) NL_SET_ERR_MSG_MOD(extack, "E-Switch vport implicit rate limit setting failed"); @@ -448,34 +473,37 @@ static int esw_qos_update_node_scheduling_element(struct mlx5_vport *vport, struct mlx5_esw_sched_node *new_node, struct netlink_ext_ack *extack) { + struct mlx5_esw_sched_node *vport_node = vport->qos.sched_node; u32 max_rate; int err; err = mlx5_destroy_scheduling_element_cmd(curr_node->esw->dev, SCHEDULING_HIERARCHY_E_SWITCH, - vport->qos.esw_sched_elem_ix); + vport_node->ix); if (err) { NL_SET_ERR_MSG_MOD(extack, "E-Switch destroy vport scheduling element failed"); return err; } /* Use new node max rate if vport max rate is unlimited. */ - max_rate = vport->qos.max_rate ? vport->qos.max_rate : new_node->max_rate; - err = esw_qos_vport_create_sched_element(vport, new_node, max_rate, vport->qos.bw_share, - &vport->qos.esw_sched_elem_ix); + max_rate = vport_node->max_rate ? vport_node->max_rate : new_node->max_rate; + err = esw_qos_vport_create_sched_element(vport, new_node, max_rate, + vport_node->bw_share, + &vport_node->ix); if (err) { NL_SET_ERR_MSG_MOD(extack, "E-Switch vport node set failed."); goto err_sched; } - esw_qos_vport_set_parent(vport, new_node); + esw_qos_node_set_parent(vport->qos.sched_node, new_node); return 0; err_sched: - max_rate = vport->qos.max_rate ? vport->qos.max_rate : curr_node->max_rate; - if (esw_qos_vport_create_sched_element(vport, curr_node, max_rate, vport->qos.bw_share, - &vport->qos.esw_sched_elem_ix)) + max_rate = vport_node->max_rate ? vport_node->max_rate : curr_node->max_rate; + if (esw_qos_vport_create_sched_element(vport, curr_node, max_rate, + vport_node->bw_share, + &vport_node->ix)) esw_warn(curr_node->esw->dev, "E-Switch vport node restore failed (vport=%d)\n", vport->vport); @@ -486,12 +514,13 @@ static int esw_qos_vport_update_node(struct mlx5_vport *vport, struct mlx5_esw_sched_node *node, struct netlink_ext_ack *extack) { + struct mlx5_esw_sched_node *vport_node = vport->qos.sched_node; struct mlx5_eswitch *esw = vport->dev->priv.eswitch; struct mlx5_esw_sched_node *new_node, *curr_node; int err; esw_assert_qos_lock_held(esw); - curr_node = vport->qos.parent; + curr_node = vport_node->parent; new_node = node ?: esw->qos.node0; if (curr_node == new_node) return 0; @@ -501,7 +530,7 @@ static int esw_qos_vport_update_node(struct mlx5_vport *vport, return err; /* Recalculate bw share weights of old and new nodes */ - if (vport->qos.bw_share || new_node->bw_share) { + if (vport_node->bw_share || new_node->bw_share) { esw_qos_normalize_node_min_rate(curr_node, extack); esw_qos_normalize_node_min_rate(new_node, extack); } @@ -709,6 +738,7 @@ static int esw_qos_vport_enable(struct mlx5_vport *vport, u32 max_rate, u32 bw_share, struct netlink_ext_ack *extack) { struct mlx5_eswitch *esw = vport->dev->priv.eswitch; + u32 sched_elem_ix; int err; esw_assert_qos_lock_held(esw); @@ -720,18 +750,28 @@ static int esw_qos_vport_enable(struct mlx5_vport *vport, return err; err = esw_qos_vport_create_sched_element(vport, esw->qos.node0, max_rate, bw_share, - &vport->qos.esw_sched_elem_ix); + &sched_elem_ix); if (err) goto err_out; - INIT_LIST_HEAD(&vport->qos.parent_entry); - esw_qos_vport_set_parent(vport, esw->qos.node0); + vport->qos.sched_node = __esw_qos_alloc_node(esw, sched_elem_ix, SCHED_NODE_TYPE_VPORT, + esw->qos.node0); + if (!vport->qos.sched_node) { + err = -ENOMEM; + goto err_alloc; + } vport->qos.enabled = true; + vport->qos.sched_node->vport = vport; + trace_mlx5_esw_vport_qos_create(vport->dev, vport, bw_share, max_rate); return 0; +err_alloc: + if (mlx5_destroy_scheduling_element_cmd(esw->dev, + SCHEDULING_HIERARCHY_E_SWITCH, sched_elem_ix)) + esw_warn(esw->dev, "E-Switch destroy vport scheduling element failed.\n"); err_out: esw_qos_put(esw); @@ -741,6 +781,7 @@ static int esw_qos_vport_enable(struct mlx5_vport *vport, void mlx5_esw_qos_vport_disable(struct mlx5_vport *vport) { struct mlx5_eswitch *esw = vport->dev->priv.eswitch; + struct mlx5_esw_sched_node *vport_node; struct mlx5_core_dev *dev; int err; @@ -748,20 +789,23 @@ void mlx5_esw_qos_vport_disable(struct mlx5_vport *vport) esw_qos_lock(esw); if (!vport->qos.enabled) goto unlock; - WARN(vport->qos.parent != esw->qos.node0, + vport_node = vport->qos.sched_node; + WARN(vport_node->parent != esw->qos.node0, "Disabling QoS on port before detaching it from node"); - dev = vport->qos.parent->esw->dev; + dev = vport_node->esw->dev; + trace_mlx5_esw_vport_qos_destroy(dev, vport); + err = mlx5_destroy_scheduling_element_cmd(dev, SCHEDULING_HIERARCHY_E_SWITCH, - vport->qos.esw_sched_elem_ix); + vport_node->ix); if (err) esw_warn(dev, "E-Switch destroy vport scheduling element failed (vport=%d,err=%d)\n", vport->vport, err); + __esw_qos_free_node(vport_node); memset(&vport->qos, 0, sizeof(vport->qos)); - trace_mlx5_esw_vport_qos_destroy(dev, vport); esw_qos_put(esw); unlock: @@ -794,8 +838,8 @@ bool mlx5_esw_qos_get_vport_rate(struct mlx5_vport *vport, u32 *max_rate, u32 *m esw_qos_lock(esw); enabled = vport->qos.enabled; if (enabled) { - *max_rate = vport->qos.max_rate; - *min_rate = vport->qos.min_rate; + *max_rate = vport->qos.sched_node->max_rate; + *min_rate = vport->qos.sched_node->min_rate; } esw_qos_unlock(esw); return enabled; @@ -891,16 +935,16 @@ int mlx5_esw_qos_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num, u32 esw_qos_lock(esw); if (!vport->qos.enabled) { /* Eswitch QoS wasn't enabled yet. Enable it and vport QoS. */ - err = esw_qos_vport_enable(vport, rate_mbps, vport->qos.bw_share, NULL); + err = esw_qos_vport_enable(vport, rate_mbps, 0, NULL); } else { - struct mlx5_core_dev *dev = vport->qos.parent->esw->dev; + struct mlx5_core_dev *dev = vport->qos.sched_node->parent->esw->dev; MLX5_SET(scheduling_context, ctx, max_average_bw, rate_mbps); bitmask = MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW; err = mlx5_modify_scheduling_element_cmd(dev, SCHEDULING_HIERARCHY_E_SWITCH, ctx, - vport->qos.esw_sched_elem_ix, + vport->qos.sched_node->ix, bitmask); } esw_qos_unlock(esw); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h index b4045efbaf9e..61a6fdd5c267 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h @@ -13,6 +13,9 @@ int mlx5_esw_qos_set_vport_rate(struct mlx5_vport *evport, u32 max_rate, u32 min bool mlx5_esw_qos_get_vport_rate(struct mlx5_vport *vport, u32 *max_rate, u32 *min_rate); void mlx5_esw_qos_vport_disable(struct mlx5_vport *vport); +u32 mlx5_esw_qos_vport_get_sched_elem_ix(const struct mlx5_vport *vport); +struct mlx5_esw_sched_node *mlx5_esw_qos_vport_get_parent(const struct mlx5_vport *vport); + int mlx5_esw_devlink_rate_leaf_tx_share_set(struct devlink_rate *rate_leaf, void *priv, u64 tx_share, struct netlink_ext_ack *extack); int mlx5_esw_devlink_rate_leaf_tx_max_set(struct devlink_rate *rate_leaf, void *priv, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c index 2bcd42305f46..09719e9b8611 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -1061,6 +1061,7 @@ static void mlx5_eswitch_clear_vf_vports_info(struct mlx5_eswitch *esw) unsigned long i; mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs) { + kfree(vport->qos.sched_node); memset(&vport->qos, 0, sizeof(vport->qos)); memset(&vport->info, 0, sizeof(vport->info)); vport->info.link_state = MLX5_VPORT_ADMIN_STATE_AUTO; @@ -1073,6 +1074,7 @@ static void mlx5_eswitch_clear_ec_vf_vports_info(struct mlx5_eswitch *esw) unsigned long i; mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs) { + kfree(vport->qos.sched_node); memset(&vport->qos, 0, sizeof(vport->qos)); memset(&vport->info, 0, sizeof(vport->info)); vport->info.link_state = MLX5_VPORT_ADMIN_STATE_AUTO; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h index 38f912f5a707..e77ec82787de 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -216,15 +216,8 @@ struct mlx5_vport { struct { /* Initially false, set to true whenever any QoS features are used. */ bool enabled; - u32 esw_sched_elem_ix; - u32 min_rate; - u32 max_rate; - /* A computed value indicating relative min_rate between vports in a group. */ - u32 bw_share; - /* The parent group of this vport scheduling element. */ - struct mlx5_esw_sched_node *parent; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Tariq Toukan Subject: [PATCH net-next V3 09/15] net/mlx5: Remove vport QoS enabled flag Date: Wed, 16 Oct 2024 20:36:11 +0300 Message-ID: <20241016173617.217736-10-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000467F:EE_|DS0PR12MB8367:EE_ X-MS-Office365-Filtering-Correlation-Id: e99683b0-7122-477f-ea40-08dcee094532 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: pLc7SROrYJkjwBSTFlAI8EmCtZgV0SJN0IzlPI7tC89qOUCBWgtb9e8usECisW+2qKTB2/Uq/EzjXVWG7CHGv2x1XHvoTIAo4TfzyWnWSo3++I2908+mbPa5bZIqNW3m76ICaYWJyzoZ8yR8ojMjXGBO127pxRvlAInBkR47WMULUPUsA6jeBUR09uA7PcfcmgDwoCY2x3H8qOjW1acsmcI+3QdyTTfup7vcW/RO4RvWbmEbcNScnlZ3aQg9snSYcx9EJlJiVp2Rf44KGoHGG8CkNFraH77hWKwBlKe2Isof8Z52i16Wj4Mn3EBBTO2pTfIv9IS4Z7OCHBFRa2ouShdl0E0anxq7Zu4IdZ0yWTnfoWwODmBnh6LxgF4tdn9K+qPSRVedmWD/xBLAUqdWzfHY63Px7lFLGnZO/+dtfQf1j+Vpi/KURLVE8o/HaD8OOQhCfDCOyGwq4ZFFaERBw4AROLLUK/8qnLxXHtLSrZ5RUfkMiJ+0YDauTHFRM+tF6rmGbSIU7BLxVOWZBfrd8ZzJ0NGl3ZAodSJfv8C+/WFJYyThlKrVCRzeRiusCXc57tRLjylwFWZHXyfH4YPTc0FcS+u7X1pi5FMOgwFFQtnptKKLvxcazIgl0bKFucp+054jcfjcZ9CGq8e0yYxOECI47YOgN70RBP6KyaQFUa/blLy17Fc92o+4MDZH7JU7QF7gt8vZPZY5ZG9DASgJkV4EHz4tS+3QK3zI4yPZMP+QAX8pO4wk70T3TU6BECrCcWOwHycucv0MzPquselsKOSTSZ+aP3hjfbR5EQKFQ0aAcRVgg/ku1tjUQ3MtHXsCIunMHXBIlMPqrFYSr+0WL2EYyetxq0KHQuTqPW8S2YKsnBijnqCnaXZlec4L3YH2OoYQUjJeLNFuqNVnzUc1VOhkbzi5w51QwLej1lgS506cdLTAJvu8LU3xAJotyLa8OAVx9to8ETt/d28K/LvvBspcpuIWzwCluhcYQQrI1x9Mz+aG//HR9f5FErKAN4tHarK5dq0qdQIdogjOk/ZbocBSNxf/8m66tSfZuuwNGrD8iPQztIX6gY9BBmbdSshGkI7h0y3kyDgd9F0V7oXxQLh7+8nEwW19vT82qbGf+CNmc+Z1ZfnQ1jzGpZq7WPoGlB6yCXPRgMe9nUeVz/AAKE4qXAdQ7TLmRSnjVOR5vCMNRzUJRM6qj9/Yjksz2aKlEYEdoRh7HjJuWeREPX+FuV7RKxq30Hc8trKyQpH5OuizpvtahwWCzvGmvQOiq2+0cm5bAX8PgJspq/DDnetL4q8FMvO/tPl8C3cwCFNaG//3ZcS3pCKliuJ48kL+rzuzAB/PRYPYpP/TxYs2Vetyhh8GLbDpRcruCUBk5oViCN79HDOeMo/yOyIeXu8vruop X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:37:56.0817 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e99683b0-7122-477f-ea40-08dcee094532 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000467F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8367 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Remove the `enabled` flag from the `vport->qos` struct, as QoS now relies solely on the `sched_node` pointer to determine whether QoS features are in use. Currently, the vport `qos` struct consists only of the `sched_node`, introducing an unnecessary two-level reference. However, the qos struct is retained as it will be extended in future patches to support new QoS features. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c | 13 ++++++------- drivers/net/ethernet/mellanox/mlx5/core/eswitch.h | 2 -- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index 2d10453afc8a..77e835fd099d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -742,7 +742,7 @@ static int esw_qos_vport_enable(struct mlx5_vport *vport, int err; esw_assert_qos_lock_held(esw); - if (vport->qos.enabled) + if (vport->qos.sched_node) return 0; err = esw_qos_get(esw, extack); @@ -761,7 +761,6 @@ static int esw_qos_vport_enable(struct mlx5_vport *vport, goto err_alloc; } - vport->qos.enabled = true; vport->qos.sched_node->vport = vport; trace_mlx5_esw_vport_qos_create(vport->dev, vport, bw_share, max_rate); @@ -787,9 +786,9 @@ void mlx5_esw_qos_vport_disable(struct mlx5_vport *vport) lockdep_assert_held(&esw->state_lock); esw_qos_lock(esw); - if (!vport->qos.enabled) - goto unlock; vport_node = vport->qos.sched_node; + if (!vport_node) + goto unlock; WARN(vport_node->parent != esw->qos.node0, "Disabling QoS on port before detaching it from node"); @@ -836,7 +835,7 @@ bool mlx5_esw_qos_get_vport_rate(struct mlx5_vport *vport, u32 *max_rate, u32 *m bool enabled; esw_qos_lock(esw); - enabled = vport->qos.enabled; + enabled = !!vport->qos.sched_node; if (enabled) { *max_rate = vport->qos.sched_node->max_rate; *min_rate = vport->qos.sched_node->min_rate; @@ -933,7 +932,7 @@ int mlx5_esw_qos_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num, u32 } esw_qos_lock(esw); - if (!vport->qos.enabled) { + if (!vport->qos.sched_node) { /* Eswitch QoS wasn't enabled yet. Enable it and vport QoS. */ err = esw_qos_vport_enable(vport, rate_mbps, 0, NULL); } else { @@ -1142,7 +1141,7 @@ int mlx5_esw_qos_vport_update_node(struct mlx5_vport *vport, } esw_qos_lock(esw); - if (!vport->qos.enabled && !node) + if (!vport->qos.sched_node && !node) goto unlock; err = esw_qos_vport_enable(vport, 0, 0, extack); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h index e77ec82787de..14dd42d44e6f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -214,8 +214,6 @@ struct mlx5_vport { /* Protected with the E-Switch qos domain lock. */ struct { - /* Initially false, set to true whenever any QoS features are used. */ - bool enabled; /* Vport scheduling element node. */ struct mlx5_esw_sched_node *sched_node; } qos; From patchwork Wed Oct 16 17:36:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13838679 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2065.outbound.protection.outlook.com [40.107.243.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49613212659 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Tariq Toukan Subject: [PATCH net-next V3 10/15] net/mlx5: Simplify QoS scheduling element configuration Date: Wed, 16 Oct 2024 20:36:12 +0300 Message-ID: <20241016173617.217736-11-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000203:EE_|DM4PR12MB7551:EE_ X-MS-Office365-Filtering-Correlation-Id: c69e3c4a-f674-432d-a97d-08dcee094467 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: uehUQ/AxCVifTLXH1OwQUzSCZd0ERYf5b29Z0KgjZ7pb7cb7G9h5R3Ry3QxSJ5dWyYJRV1uwc/BEjtI0b4N4fWBXCe3biTGrWB1qN5Zy+KtIyeDv+BO8OWzpnGiV6MxBOKakMM7XE2+wmjlIh0FH1Z9Ziu0u3AqQRTzs2X7fHTFfg/LJcE4JONKBe8am7zO53RLmRrppTKWwLqZHRjTNYIDwaGsrRskXkxh+Qk5ej1sfh+wTTxxHacNkeSFHEEYZq2OKbHr2cy475M187hDRR1bTw8JqFCk92X1Y5uEQuMeUINEO/06o/QhZfAtHxBLEviqngjNs3ny+DMkcvXnvfDt5sWgrCN9FcgskBQmwRV9zdi8qnp6PW+vrZJgNkbsxiJcjZKV4bevZ3LEx4ICHCG95p++ZOuQEc3CccydQcLlKRPAocI8mYtVtoMUph9swTsT2kOin8wx3JOTCbrHbNXVJCj8XAfy2f0d5tNHT5/31YA0fGJk6WMVFlRyLH+NFRnIWyr4LGsUYzTgUP2mW89jh5MbeWXMUxMoeCwomMA2z4PnCmwNfuLRDBTT7ekRJePK8/2S9Qao/yVBWIkc8UrmCq7Vt59lc5NKUO/WsXJmj+wbK7rK3hRG14BAnxNhvfA8k6LLjRYf5MXfjlfBtz2+pnS7BS6mxTA2QKI5yTj6IxUwLVjDJFjmU3+EBOVEk90NVxfFD1XFOKCMZJYfavvAaGtvkjRHqfXlNVX1dLdPwLpOtfXNnStpxsH7uOWUiyIpM7qufWY3Re4CVZq61zfs7lt/hEn1KHVUovMn1YCHiXuDARImLbE+m/dU0OWqfBsBrtZppfn7wGEsO3ip+RhncxGMxV65Oj1qkJrnG5woPVWaEcuiv75J+Qx+9IIuRKv7rTubxwgqJSeJw33XCnSEsjqgfdjz15RHYWtsULNVRSwywlPNx88wP4QBn1G/SXafDr1cVAgQpi6XdJE/5V8kERHAPQOX9L2tkgYCjcD47ClJWxIFXtsLgdQ4d7umyGHnsMwr0tpDmPBlIcbot1lzivQpCUjMg7b6u3znuoQLMY2atK5dr/MgmUoO1sU3SYK8QlGl7Pb1HiWY4RVO+KNrDwfFRY11Fuo2idopX/SkIuTjqU5Vjzw66VHNNhApvNieTe92kcbt5ob1ZCpXnJK5Rv0g3rzoV25PrJugy7Arpe82HEWxFouO1D56yUSfSmb6ME1ZXQ/c3r2F66TqSoZFJ8VgPg7RVhBpjIvAld3v2WgyJpmadzYNHulbeu0NIWZU4I/PSkDP+MsbobigmVDB9FeOlJgNQXxO+dA9edo23ZCIj654cIkR/hpuRWqzlapkno/yKuRQD9PAdrCGws3/F8gZQMr/i0xdxHZrxS8UnLNZDaR9TTmg9WSJ3+qIK X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:37:54.9372 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c69e3c4a-f674-432d-a97d-08dcee094467 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000203.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7551 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Simplify the configuration of QoS scheduling elements by removing the separate functions `esw_qos_node_config` and `esw_qos_vport_config`. Instead, directly use the existing `esw_qos_sched_elem_config` function for both nodes and vports. This unification helps in generalizing operations on scheduling elements nodes. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 86 +++++++++---------- 1 file changed, 40 insertions(+), 46 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index 77e835fd099d..7b243ba5558c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -66,6 +66,11 @@ enum sched_node_type { SCHED_NODE_TYPE_VPORT, }; +static const char * const sched_node_type_str[] = { + [SCHED_NODE_TYPE_VPORTS_TSAR] = "vports TSAR", + [SCHED_NODE_TYPE_VPORT] = "vport", +}; + struct mlx5_esw_sched_node { u32 ix; /* Bandwidth parameters. */ @@ -113,11 +118,27 @@ mlx5_esw_qos_vport_get_parent(const struct mlx5_vport *vport) return vport->qos.sched_node->parent; } -static int esw_qos_sched_elem_config(struct mlx5_core_dev *dev, u32 sched_elem_ix, - u32 max_rate, u32 bw_share) +static void esw_qos_sched_elem_config_warn(struct mlx5_esw_sched_node *node, int err) +{ + if (node->vport) { + esw_warn(node->esw->dev, + "E-Switch modify %s scheduling element failed (vport=%d,err=%d)\n", + sched_node_type_str[node->type], node->vport->vport, err); + return; + } + + esw_warn(node->esw->dev, + "E-Switch modify %s scheduling element failed (err=%d)\n", + sched_node_type_str[node->type], err); +} + +static int esw_qos_sched_elem_config(struct mlx5_esw_sched_node *node, u32 max_rate, u32 bw_share, + struct netlink_ext_ack *extack) { u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {}; + struct mlx5_core_dev *dev = node->esw->dev; u32 bitmask = 0; + int err; if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling)) return -EOPNOTSUPP; @@ -127,46 +148,22 @@ static int esw_qos_sched_elem_config(struct mlx5_core_dev *dev, u32 sched_elem_i bitmask |= MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW; bitmask |= MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE; - return mlx5_modify_scheduling_element_cmd(dev, - SCHEDULING_HIERARCHY_E_SWITCH, - sched_ctx, - sched_elem_ix, - bitmask); -} - -static int esw_qos_node_config(struct mlx5_esw_sched_node *node, - u32 max_rate, u32 bw_share, struct netlink_ext_ack *extack) -{ - struct mlx5_core_dev *dev = node->esw->dev; - int err; - - err = esw_qos_sched_elem_config(dev, node->ix, max_rate, bw_share); - if (err) - NL_SET_ERR_MSG_MOD(extack, "E-Switch modify node TSAR element failed"); - - trace_mlx5_esw_node_qos_config(dev, node, node->ix, bw_share, max_rate); - - return err; -} - -static int esw_qos_vport_config(struct mlx5_vport *vport, - u32 max_rate, u32 bw_share, - struct netlink_ext_ack *extack) -{ - struct mlx5_esw_sched_node *vport_node = vport->qos.sched_node; - struct mlx5_core_dev *dev = vport_node->parent->esw->dev; - int err; - - err = esw_qos_sched_elem_config(dev, vport_node->ix, max_rate, bw_share); + err = mlx5_modify_scheduling_element_cmd(dev, + SCHEDULING_HIERARCHY_E_SWITCH, + sched_ctx, + node->ix, + bitmask); if (err) { - esw_warn(dev, - "E-Switch modify vport scheduling element failed (vport=%d,err=%d)\n", - vport->vport, err); - NL_SET_ERR_MSG_MOD(extack, "E-Switch modify vport scheduling element failed"); + esw_qos_sched_elem_config_warn(node, err); + NL_SET_ERR_MSG_MOD(extack, "E-Switch modify scheduling element failed"); + return err; } - trace_mlx5_esw_vport_qos_config(dev, vport, bw_share, max_rate); + if (node->type == SCHED_NODE_TYPE_VPORTS_TSAR) + trace_mlx5_esw_node_qos_config(dev, node, node->ix, bw_share, max_rate); + else if (node->type == SCHED_NODE_TYPE_VPORT) + trace_mlx5_esw_vport_qos_config(dev, node->vport, bw_share, max_rate); return 0; } @@ -246,8 +243,7 @@ static int esw_qos_normalize_node_min_rate(struct mlx5_esw_sched_node *node, if (bw_share == vport_node->bw_share) continue; - err = esw_qos_vport_config(vport_node->vport, vport_node->max_rate, bw_share, - extack); + err = esw_qos_sched_elem_config(vport_node, vport_node->max_rate, bw_share, extack); if (err) return err; @@ -274,7 +270,7 @@ static int esw_qos_normalize_min_rate(struct mlx5_eswitch *esw, struct netlink_e if (bw_share == node->bw_share) continue; - err = esw_qos_node_config(node, node->max_rate, bw_share, extack); + err = esw_qos_sched_elem_config(node, node->max_rate, bw_share, extack); if (err) return err; @@ -338,8 +334,7 @@ static int esw_qos_set_vport_max_rate(struct mlx5_vport *vport, if (!max_rate) act_max_rate = vport_node->parent->max_rate; - err = esw_qos_vport_config(vport, act_max_rate, vport_node->bw_share, extack); - + err = esw_qos_sched_elem_config(vport_node, act_max_rate, vport_node->bw_share, extack); if (!err) vport_node->max_rate = max_rate; @@ -384,7 +379,7 @@ static int esw_qos_set_node_max_rate(struct mlx5_esw_sched_node *node, if (node->max_rate == max_rate) return 0; - err = esw_qos_node_config(node, max_rate, node->bw_share, extack); + err = esw_qos_sched_elem_config(node, max_rate, node->bw_share, extack); if (err) return err; @@ -395,8 +390,7 @@ static int esw_qos_set_node_max_rate(struct mlx5_esw_sched_node *node, if (vport_node->max_rate) continue; - err = esw_qos_vport_config(vport_node->vport, max_rate, vport_node->bw_share, - extack); + err = esw_qos_sched_elem_config(vport_node, max_rate, vport_node->bw_share, extack); if (err) NL_SET_ERR_MSG_MOD(extack, "E-Switch vport implicit rate limit setting failed"); From patchwork Wed Oct 16 17:36:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13838681 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2051.outbound.protection.outlook.com [40.107.94.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B56C8212624 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Tariq Toukan Subject: [PATCH net-next V3 11/15] net/mlx5: Generalize QoS operations for nodes and vports Date: Wed, 16 Oct 2024 20:36:13 +0300 Message-ID: <20241016173617.217736-12-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000467F:EE_|PH0PR12MB5648:EE_ X-MS-Office365-Filtering-Correlation-Id: 46401c90-2c24-41ab-bbd6-08dcee09496f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: TfcExRdqEWv2aM4ZnzC0SAW/BO66TVKFdd/u8xryRfuyS3ozLuu5e1rmlgqjddqNqqKkHa0DCXgUE7POKmAqs8czgFNjTQ6Tmq7EIZXhYbsXrmbouYn4vvL+1cCmhLMqKGwcHD+4TL319sZ8bBI+dnxN72M4fvpTvyzOi20Pa0wrJNRio3Pws+1/i3ZXU7rvjHgp672M5lwwP/7YCDcQloHDjnKFRT4FA7eHOIZTlz9oXQ7GlYupSLnICwq15UKDW0HGRwhpygOBT4oaMwnYa1K8Kxhcfn28K0eU+lZr0/P6A9ltzoKSvp/eK3QNYtRLn+kqYcd4PshX44U/1UCsvqz+50mJ2HS3i/BQgp1oDMRSQtuAuedA+hlXbuc3lfTLsqESVM9qu6iP2JbCPxtufs4jXOcJ/Z7oirjuKjRrHtuaiu7Y+M7QMQ+RE1Iq6T1khzys7gXKqNkPK5jn/Kd17hGFWnK2o2Z5jN8fgwONkvif0Y9Ibn0fOFdHeWsSxBLttpFk1ZV1PFDS+cHoQQGAJpnbQSBkBOdngTIWdKuZStYNbADR+b77fagsfQtzjOAYUJtnWnxOtWupIz1NbKd9fd+UIsISscFZWD+9aJ5UhTLHHt5woFmAqn07SG4tWKw7mO1hcGyGBdknJD8uN3FcpThURAQHqf5nKYrl+BwYhX2s6I9h6Ktb1ed8k0Rf4aP/SUIFuUsttJIv1BeuiZQl+ctqTxtTAYi4eDfOLyPavkEDGJXRIxa29pwqAlIOGAqBpDjSk1ww88Nq/6ezDhtEw8hQ3XgaKFYNeQI8WZ+TZjkB9nNGKYg5wx/ZbxFX+YKW8HVM6edBm4+ZL/CZJZWnhdpcL18JIKkn2tLbhm0FMn9x1z1B9P55j+rg7oETwUUaQiIlElI1ZTnh6XDN+8b6vEKNhVMbRoFAs+M4FcupCUiWTJUyLQPIg4zbsCbLMMu3Tv87dQmSW1S+E+OVNozlbDiQbwpzzyZZ9sxceC+3th9Wwc4fss1OK9Wyij7mnCCPmt7eu1F+tXZRJBrcr2cwDYvWrGQlzk85e211AsrfqDt1HGu7ycryg+APIxv2fXK8N9D8yQ5Cg9rCR37zMBAlptvc5stX+FSqhipsmjbtu0vPxQSMLwavhe2WlDqzsiMbOL37Qa2yJX1PnE8g7pEGe+3L28Fdk+VZ8BnVyBjgDmDzCbhfrWg85liFDKR9c1iPRn6KNe1QUs1moK47/wvE4Zc8tjarRASOCY+ghp396O9XBJX2xnwVAdj9VK2yi7o+7RL1Z0IgmTaXyMiUTzM8EwzEgfHVVhR1my649Dc7dY8Zu0xS61a3VdZhSabFuKGzADQesPvj+PGoyCkCASc2dM9ev6caNdrS1XJPpUtEHLk= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:38:03.2537 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 46401c90-2c24-41ab-bbd6-08dcee09496f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000467F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5648 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Refactor QoS normalization and rate calculation functions to operate on mlx5_esw_sched_node, allowing for generalized handling of both vports and nodes. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 115 +++++++----------- 1 file changed, 43 insertions(+), 72 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index 7b243ba5558c..7e7f99b38a37 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -168,45 +168,18 @@ static int esw_qos_sched_elem_config(struct mlx5_esw_sched_node *node, u32 max_r return 0; } -static u32 esw_qos_calculate_node_min_rate_divider(struct mlx5_esw_sched_node *node) -{ - u32 fw_max_bw_share = MLX5_CAP_QOS(node->esw->dev, max_tsar_bw_share); - struct mlx5_esw_sched_node *vport_node; - u32 max_guarantee = 0; - - /* Find max min_rate across all vports in this node. - * This will correspond to fw_max_bw_share in the final bw_share calculation. - */ - list_for_each_entry(vport_node, &node->children, entry) { - if (vport_node->min_rate > max_guarantee) - max_guarantee = vport_node->min_rate; - } - - if (max_guarantee) - return max_t(u32, max_guarantee / fw_max_bw_share, 1); - - /* If vports max min_rate divider is 0 but their node has bw_share - * configured, then set bw_share for vports to minimal value. - */ - if (node->bw_share) - return 1; - - /* A divider of 0 sets bw_share for all node vports to 0, - * effectively disabling min guarantees. - */ - return 0; -} - -static u32 esw_qos_calculate_min_rate_divider(struct mlx5_eswitch *esw) +static u32 esw_qos_calculate_min_rate_divider(struct mlx5_eswitch *esw, + struct mlx5_esw_sched_node *parent) { + struct list_head *nodes = parent ? &parent->children : &esw->qos.domain->nodes; u32 fw_max_bw_share = MLX5_CAP_QOS(esw->dev, max_tsar_bw_share); struct mlx5_esw_sched_node *node; u32 max_guarantee = 0; - /* Find max min_rate across all esw nodes. + /* Find max min_rate across all nodes. * This will correspond to fw_max_bw_share in the final bw_share calculation. */ - list_for_each_entry(node, &esw->qos.domain->nodes, entry) { + list_for_each_entry(node, nodes, entry) { if (node->esw == esw && node->ix != esw->qos.root_tsar_ix && node->min_rate > max_guarantee) max_guarantee = node->min_rate; @@ -215,7 +188,14 @@ static u32 esw_qos_calculate_min_rate_divider(struct mlx5_eswitch *esw) if (max_guarantee) return max_t(u32, max_guarantee / fw_max_bw_share, 1); - /* If no node has min_rate configured, a divider of 0 sets all + /* If nodes max min_rate divider is 0 but their parent has bw_share + * configured, then set bw_share for nodes to minimal value. + */ + + if (parent && parent->bw_share) + return 1; + + /* If the node nodes has min_rate configured, a divider of 0 sets all * nodes' bw_share to 0, effectively disabling min guarantees. */ return 0; @@ -228,59 +208,50 @@ static u32 esw_qos_calc_bw_share(u32 min_rate, u32 divider, u32 fw_max) return min_t(u32, max_t(u32, DIV_ROUND_UP(min_rate, divider), MLX5_MIN_BW_SHARE), fw_max); } -static int esw_qos_normalize_node_min_rate(struct mlx5_esw_sched_node *node, - struct netlink_ext_ack *extack) +static int esw_qos_update_sched_node_bw_share(struct mlx5_esw_sched_node *node, + u32 divider, + struct netlink_ext_ack *extack) { u32 fw_max_bw_share = MLX5_CAP_QOS(node->esw->dev, max_tsar_bw_share); - u32 divider = esw_qos_calculate_node_min_rate_divider(node); - struct mlx5_esw_sched_node *vport_node; u32 bw_share; int err; - list_for_each_entry(vport_node, &node->children, entry) { - bw_share = esw_qos_calc_bw_share(vport_node->min_rate, divider, fw_max_bw_share); + bw_share = esw_qos_calc_bw_share(node->min_rate, divider, fw_max_bw_share); - if (bw_share == vport_node->bw_share) - continue; + if (bw_share == node->bw_share) + return 0; - err = esw_qos_sched_elem_config(vport_node, vport_node->max_rate, bw_share, extack); - if (err) - return err; + err = esw_qos_sched_elem_config(node, node->max_rate, bw_share, extack); + if (err) + return err; - vport_node->bw_share = bw_share; - } + node->bw_share = bw_share; - return 0; + return err; } -static int esw_qos_normalize_min_rate(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack) +static int esw_qos_normalize_min_rate(struct mlx5_eswitch *esw, + struct mlx5_esw_sched_node *parent, + struct netlink_ext_ack *extack) { - u32 fw_max_bw_share = MLX5_CAP_QOS(esw->dev, max_tsar_bw_share); - u32 divider = esw_qos_calculate_min_rate_divider(esw); + struct list_head *nodes = parent ? &parent->children : &esw->qos.domain->nodes; + u32 divider = esw_qos_calculate_min_rate_divider(esw, parent); struct mlx5_esw_sched_node *node; - u32 bw_share; - int err; - list_for_each_entry(node, &esw->qos.domain->nodes, entry) { - if (node->esw != esw || node->ix == esw->qos.root_tsar_ix) - continue; - bw_share = esw_qos_calc_bw_share(node->min_rate, divider, - fw_max_bw_share); + list_for_each_entry(node, nodes, entry) { + int err; - if (bw_share == node->bw_share) + if (node->esw != esw || node->ix == esw->qos.root_tsar_ix) continue; - err = esw_qos_sched_elem_config(node, node->max_rate, bw_share, extack); + err = esw_qos_update_sched_node_bw_share(node, divider, extack); if (err) return err; - node->bw_share = bw_share; - - /* All the node's vports need to be set with default bw_share - * to enable them with QOS - */ - err = esw_qos_normalize_node_min_rate(node, extack); + if (list_empty(&node->children)) + continue; + err = esw_qos_normalize_min_rate(node->esw, node, extack); if (err) return err; } @@ -307,7 +278,7 @@ static int esw_qos_set_vport_min_rate(struct mlx5_vport *vport, previous_min_rate = vport_node->min_rate; vport_node->min_rate = min_rate; - err = esw_qos_normalize_node_min_rate(vport_node->parent, extack); + err = esw_qos_normalize_min_rate(vport_node->parent->esw, vport_node->parent, extack); if (err) vport_node->min_rate = previous_min_rate; @@ -357,13 +328,13 @@ static int esw_qos_set_node_min_rate(struct mlx5_esw_sched_node *node, previous_min_rate = node->min_rate; node->min_rate = min_rate; - err = esw_qos_normalize_min_rate(esw, extack); + err = esw_qos_normalize_min_rate(esw, NULL, extack); if (err) { NL_SET_ERR_MSG_MOD(extack, "E-Switch node min rate setting failed"); /* Attempt restoring previous configuration */ node->min_rate = previous_min_rate; - if (esw_qos_normalize_min_rate(esw, extack)) + if (esw_qos_normalize_min_rate(esw, NULL, extack)) NL_SET_ERR_MSG_MOD(extack, "E-Switch BW share restore failed"); } @@ -525,8 +496,8 @@ static int esw_qos_vport_update_node(struct mlx5_vport *vport, /* Recalculate bw share weights of old and new nodes */ if (vport_node->bw_share || new_node->bw_share) { - esw_qos_normalize_node_min_rate(curr_node, extack); - esw_qos_normalize_node_min_rate(new_node, extack); + esw_qos_normalize_min_rate(curr_node->esw, curr_node, extack); + esw_qos_normalize_min_rate(new_node->esw, new_node, extack); } return 0; @@ -581,7 +552,7 @@ __esw_qos_create_vports_sched_node(struct mlx5_eswitch *esw, struct mlx5_esw_sch goto err_alloc_node; } - err = esw_qos_normalize_min_rate(esw, extack); + err = esw_qos_normalize_min_rate(esw, NULL, extack); if (err) { NL_SET_ERR_MSG_MOD(extack, "E-Switch nodes normalization failed"); goto err_min_rate; @@ -638,7 +609,7 @@ static int __esw_qos_destroy_node(struct mlx5_esw_sched_node *node, struct netli NL_SET_ERR_MSG_MOD(extack, "E-Switch destroy TSAR_ID failed"); __esw_qos_free_node(node); - err = esw_qos_normalize_min_rate(esw, extack); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Moshe Shemesh , Aya Levin , Tariq Toukan Subject: [PATCH net-next V3 12/15] net/mlx5: Add sync reset drop mode support Date: Wed, 16 Oct 2024 20:36:14 +0300 Message-ID: <20241016173617.217736-13-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004680:EE_|MW6PR12MB8952:EE_ X-MS-Office365-Filtering-Correlation-Id: 3cddf701-d3f2-47be-8485-08dcee094a84 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: uxqYVQXUfVOcQttrLmLE7i7qXWVs8sTf4OrAG+kZ/EcaCLhO3wOWRaW6seIqyUalRODiuUYsmoE6NLkw8OmGohj7VfB4QBZtj6LXN7RDgnBDd2R7vpqWIORL/12Yc7htXUe4PidFY4LaHunkCr2vF0MdZqU+Ghr8RIgU3MiE4ddV27iGClC99OjcMjNiiMWUvtCvPWMOpqQ0GHNQUHnPMFk+g/r81NOM3gGdD8OBqECrgNC1ou56csfntxFZRV10Pwz9RAMWlSBzgntD2Hb6QzLozFfE17tb5D1EHYA29e/AzeThwvHoiARS/+D8NHQBe+k4kP8iCZyY+rJp2Vs5XWrKdRM6Bm8xbgkrUKjpmlNa1CmFmMuw0str9c67ES4/x3yG9CCeP7POeBHTYa6WZXs64J99s+bPya8wMeiCcJt3QH52xp3+ZMIdYk3KTQOQ8BfhSZO+D7Cjy6HeSowGHtK0k0RT59P0jQmYnMlgNPvE/0KXD/sS9I3oIDxQb3KpF9dOABy5jfOU2yoTEv0IYQgD3z9xjmKT9eagUUDtNq6H3xSFBrejmWjgYyjyOUftcyu5wmGip7wJvbjHw3kNU4Aa7rr+6ye6VNxT/vFk7NTYtKYBzHXjz4lOVnNUgGS37CCHrnisRjmtjcPbGu4TAKDJXEv7mwiun+taxZbH2AcBrD/FWmZszaHM4AqE1jbgiK8Uiz3tCj0jTzk+0IWNtSLZ6csQGtIKTIlEjPDzzMApO6V79Q7HIWNfwIPuinTl2PDWPUFJh7ZWjKchG2zteRPvqYRgpM2TaUHa8f7SwIPoe72MUJO00EdhC3/MBsdigmBS/SNgGzurSTsnR2XoA/JQvKvDUoY54h3QtGp4fHf23DlrWBwB4Jd28XPsiwFyPOLjZS7FU+j34GLi5a9S2Qi3HHL09nh92q9NcLYXfCyRpwG1TNlIKuXuvKn68to88Bodk6nnrhGmKTlrsCGDs3XAw60SgR3OmzaXI25DDH8uUew0SYsRI9XLtYezSWfKrFbvFVtcViIcBDUbpeBGWxemgMwnJkbcrCFgdY+8+CReQoTBv3BxRUWkTF68RondL5HZSY5PBoGiRNvJTOc/SqbVCQEaA8bHtt8iiSC3X4locrv8AUUIryUrPRSa26zcWf/ktjd9KGc4csQDG9dvwGi9fuYnQJrHzEUROYuecusGdO+G4AWODW56wcfIqYrpE2BhoMqiHQG/dTKrwqq9ebJ7EOoI+owCkgrtFvpDBr5I4+rLkoofmbQigCJ/W/aco8rR4z45H5RTTl9yPrzH0LjfJrptN4acHqHHJis7VcbWPJ9vLO+CQjX9DZjLNo13eIfiAffgxBAGVqktkIr+4kH0ycb2irtLvwNgcwPT57HEsHIniGSOmBFuO6o2h3Mk X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:38:04.9895 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3cddf701-d3f2-47be-8485-08dcee094a84 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004680.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8952 X-Patchwork-Delegate: kuba@kernel.org From: Moshe Shemesh On sync reset flow, firmware may request a PF, which already acknowledged the unload event, to move to drop mode. Drop mode means that this PF will reduce polling frequency, as this PF is not going to have another active part in the reset, but only reload back after the reset. Signed-off-by: Moshe Shemesh Reviewed-by: Aya Levin Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c index 4f55e55ecb55..566710d34a7b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c @@ -35,6 +35,7 @@ struct mlx5_fw_reset { enum { MLX5_FW_RST_STATE_IDLE = 0, MLX5_FW_RST_STATE_TOGGLE_REQ = 4, + MLX5_FW_RST_STATE_DROP_MODE = 5, }; enum { @@ -616,6 +617,7 @@ static void mlx5_sync_reset_unload_event(struct work_struct *work) struct mlx5_fw_reset *fw_reset; struct mlx5_core_dev *dev; unsigned long timeout; + int poll_freq = 20; bool reset_action; u8 rst_state; int err; @@ -651,7 +653,12 @@ static void mlx5_sync_reset_unload_event(struct work_struct *work) reset_action = true; break; } - msleep(20); + if (rst_state == MLX5_FW_RST_STATE_DROP_MODE) { + mlx5_core_info(dev, "Sync Reset Drop mode ack\n"); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Benjamin Poirier , "Tariq Toukan" Subject: [PATCH net-next V3 13/15] net/mlx5: Only create VEPA flow table when in VEPA mode Date: Wed, 16 Oct 2024 20:36:15 +0300 Message-ID: <20241016173617.217736-14-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000208:EE_|DM4PR12MB6184:EE_ X-MS-Office365-Filtering-Correlation-Id: 972788c9-e84f-4762-28e1-08dcee0947a7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: p2coCIXuPZnyzpEsSEoTBVaOo6k+Z1AU6+cyTY7dFn9JgF30aC+gHZiYLWZnJwYH0TMF9Zv4DTcEj6AYQSUIMt8GjcYgGFvzp+3u3b1dlu+wRaFtnPrGL9Rsrtsid2BhkcRF9yCs9weosfyaHTy5/wTSqrCSDrEmQM/gFT+ZyPLRu+AZfH14Xw7LP8A2QEzGw44wF+hjU/ovGMJ6b93XW4OAhKeiJSchKobpmhC5rzL4ZslSHkd19Q1dmAKTe8qgZe6ECgayLb+b+AK1bqSImc3MA32SdafPCtO5FGrL8V8tUCJdIUulVNgyirEuUMKWBQG69zKziHfWbq+rbQiZAC/TT83ZqWTGh4VBUTkLOqKhYGcWF1nqER2iMy1HKEHMnqbWj4MlyTas/aWlY1HW1icP/YR8tvS87uKpftQYuAAZlACY+XJI3QIQTCs/5Z263wpe70tpz94MeJwHDgZtguoqkv5ZL1DyKFjxHF4ryeCeFKLc+KP+cb1xfYx1Z4xOEm6gy+JeVq+iM0fbCuPnF1j8pJZWb80bjsJ3Z0bpsrWbM/yegRvIHPPnDxxZgLMqDPLAnmgAbwTTEkVm7iOTlFbltk7aea1dG/r4CXIqXo1mSCR3Yqks83p034He91ju124gW6YN6PjxP9pXgiu8Oq6Pp8bIFShneu0Ycgrgf0qg3XC4RGMJM8RHRLkK+3Xvjqkm12gT/cMYo0JPUMSHiwzYPhS9CydOhB32OEy81j6RrPCQZeydrpy0jBTmf/L4TObJaCpjZi1A10gQjK7D6DxR1moe8L4JPj/YFX8CZM4I9avBIVeqoxAUo3RGhc79jlbcGWTQzlk/6xojID/dUkGUJrdD6mIZoHW/8attKzBZnRWQef4+ntZYWhNlyhgiPZl+/DL/x5+fPdVzhwRnLL/aUc8NO1tAO3WRmbkRpiagW9ZnIel4n6dYZrK/D8ImMJZv+fqmbG2jaMk54ZklOrd7oad7VgXOZ3lA5FrNoF15XkDDiPLX5nZgPwkuCzqaNUY/V/zpuJBuMoqTBLcobD90y+psE0rM+jeT4uzXY5vTl730v0CjMvSWQHVv16NluyyMbTk1UFtonhXeUtLrxwZ/N199sZgIkP4vxV02PzHpv/tOgB1D5Ms0h/oYMAyvDLCR/AnV+1s4ZkrYq5ulVQ5JVMPDSM5PiegePBR0vsdMNC6JKA+BD61jpDqlya3nRMzxjjlExZpZ9dPws8NXS2uKOmk/VUNkDEcWSNdziUpjKaTWU7Gqm/boXKb3fphVJMp2AQ9p6EWlWY3Y+CQ/lamRHUjFeEk61hi3VtKOuoEYzHou8IVnSB+cORmkD2FGZjyuxhQgqy/TBkhoZO5w5RR2IXXgLnHU9v5hsWlCImHRSVDEnIlOzcVoDyBccru7 X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:38:00.3865 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 972788c9-e84f-4762-28e1-08dcee0947a7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000208.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6184 X-Patchwork-Delegate: kuba@kernel.org From: Benjamin Poirier Currently, when VFs are created, two flow tables are added for the eswitch: the "fdb" table, which contains rules for each VF and the "vepa_fdb" table. In the default VEB mode, the vepa_fdb table is empty. When switching to VEPA mode, flow steering rules are added to vepa_fdb. Even though the vepa_fdb table is empty in VEB mode, its presence adds some cost to packet processing. In some workloads, this leads to drops which are reported by the rx_discards_phy ethtool counter. In order to improve performance, only create vepa_fdb when in VEPA mode. Tests were done on a ConnectX-6 Lx adapter forwarding 64B packets between both ports using dpdk-testpmd. Numbers are Rx-pps for each port, as reported by testpmd. Without changes: traffic to unknown mac testpmd on PF numvfs=0,0 35257998,35264499 numvfs=1,1 24590124,24590888 testpmd on VF with numvfs=1,1 20434338,20434887 traffic to VF mac testpmd on VF with numvfs=1,1 30341014,30340749 With changes: traffic to unknown mac testpmd on PF numvfs=0,0 35404361,35383378 numvfs=1,1 29801247,29790757 testpmd on VF with numvfs=1,1 24310435,24309084 traffic to VF mac testpmd on VF with numvfs=1,1 34811436,34781706 Signed-off-by: Benjamin Poirier Reviewed-by: Cosmin Ratiu Reviewed-by: Saeed Mahameed Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/esw/legacy.c | 27 +++++++++---------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/legacy.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/legacy.c index 288c797e4a78..45183de424f3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/legacy.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/legacy.c @@ -176,20 +176,10 @@ static void esw_destroy_legacy_vepa_table(struct mlx5_eswitch *esw) static int esw_create_legacy_table(struct mlx5_eswitch *esw) { - int err; - memset(&esw->fdb_table.legacy, 0, sizeof(struct legacy_fdb)); atomic64_set(&esw->user_count, 0); - err = esw_create_legacy_vepa_table(esw); - if (err) - return err; - - err = esw_create_legacy_fdb_table(esw); - if (err) - esw_destroy_legacy_vepa_table(esw); - - return err; + return esw_create_legacy_fdb_table(esw); } static void esw_cleanup_vepa_rules(struct mlx5_eswitch *esw) @@ -259,15 +249,22 @@ static int _mlx5_eswitch_set_vepa_locked(struct mlx5_eswitch *esw, if (!setting) { esw_cleanup_vepa_rules(esw); + esw_destroy_legacy_vepa_table(esw); return 0; } if (esw->fdb_table.legacy.vepa_uplink_rule) return 0; + err = esw_create_legacy_vepa_table(esw); + if (err) + return err; + spec = kvzalloc(sizeof(*spec), GFP_KERNEL); - if (!spec) - return -ENOMEM; + if (!spec) { + err = -ENOMEM; + goto out; + } /* Uplink rule forward uplink traffic to FDB */ misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); @@ -303,8 +300,10 @@ static int _mlx5_eswitch_set_vepa_locked(struct mlx5_eswitch *esw, out: kvfree(spec); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Moshe Shemesh , "Yevgeny Kliteynik" , Tariq Toukan Subject: [PATCH net-next V3 14/15] net/mlx5: fs, rename packet reformat struct member action Date: Wed, 16 Oct 2024 20:36:16 +0300 Message-ID: <20241016173617.217736-15-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000208:EE_|BY5PR12MB4210:EE_ X-MS-Office365-Filtering-Correlation-Id: 893420fe-349b-4191-fbf3-08dcee0949e0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: mwecWcoaHK9R3zDHBwqck8QpdSXCCJT6b/IllAyozhqenky5r1TFBdLlpoJ/HaZt5gclso97uWlHBmq9dHvYx2nn83EzX2v+PrqW7H93ARiaCnVLhZrOu5fMRnmpDoX4vg3+BvnvDfOrpkWrizIos39H9uqyHhCB3D5I2rywWN7txY4DfalCkP/k9HYpXgX702+iC0eKpmOkeSoQgM9rTit6aYbf/TVwJDtXdkwShwLbSWPkagHNbQHl2UP65nGCQ5dRjPHBDLa5/VQiDUIwXuFSA91virRDd72ZB3uCEHRzZjAc1hz+aUdsjYirAO6ougJxb3uT+cf/1yEeQtBQTVdWOa852yBGA/aF5QeaaP3XAuDHFTZhj9WsEOlM6QobrJHoWWMybI2/8JSuPOIW4DVLICiSdI3D4q8uBvCSwxprfpiFAVym6CwoHIuHcnDhh+zgkjLzWd1b44F3JCO0CeJZcVEqodbIVqnIW0H++vxKcdV0tGMkYxIFb1MZtlZ/8c4NaNpgt+n310w+r3bSYU9lT+NGr6cWy6uNBA/k7mYJZDgHsTGmcn0FAX7XUmOdZ+edxnvvCNWaRRi18Uu4+87Pw/0AZae3RMO4g3LUxTd/x2WR314ZEZ0Ak8IynRb2yxNbxT6be5633NOoJZVpLgouRYxkyU8t61vmvVXCpnxPJF3Va8RRNjsKAggvaS4OEEJv2XgTNV/FrbJoN5sDflerFk+wUj+fZacl8Qm5JNhwxY/Og+HBgbaDJPHHOSb9hC8zK5jrJqe5CWky7iNkjhZnWXCbdzs1tNCq7Pbc6FqMQ42S2rnlguKBLgCUlKhcUV+Vvx/96ud0eh7+6crLBaLsRkZRSU9Ojonyu+2RvjL1gJGH3dx89eamTJZnLCIJSingYe0XXt1iOV4ZA9SQ89jl5inAzw24T68+SVkAjzkZjq68s0kgZ17UZHp0bhpIvWqMh3TttJSxqy5hv4uHn7qjgaT+KXpMs/3VBC6WV5xhqpgC7f+rBK6JWVJJR/zj4LPqOuWoDEFJItdavxjS8L3R83bujsI9ZkT0LVc4nJFoKO8Ukk9r/Y/FPckAwOL8qNARUOQZuWzMaKva9zUvBsRrdPGOfaKRA5j/RdMv4jtYUXbH13+jitJBgqQORL0xt9yrwIYTudkNpYzI5FucFUcbmLIfUAcJWeOw59pAcpQ2V6bF1LIl31XixO7U9CL9TKnb+9TaVSAZ5JtdV0H21nCOT79cdoCTLbRFoEtq2/QzlXw3yymW7rvWwxZqu4jp2kx5bPOjEKo4R8fWPwCWdSZA32c8C+gBUp9azFFM7im4fiBM0DNU9SYL6PuhXceRd43lZmK4oQPbzw++C8tPatvCbPGR1gszDBrkedxpidWFOmPruevsrMr9jDgeE0wJ X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:38:04.1209 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 893420fe-349b-4191-fbf3-08dcee0949e0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000208.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4210 X-Patchwork-Delegate: kuba@kernel.org From: Moshe Shemesh As preparation for HW Steering support, rename packet reformat struct member action to fs_dr_action, to distinguish from fs_hws_action which will be added. Add a pointer where needed to keep code line shorter and more readable. Reviewed-by: Yevgeny Kliteynik Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/fs_core.h | 2 +- .../mellanox/mlx5/core/steering/fs_dr.c | 23 +++++++++++-------- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h index 964937f17cf5..195f1cbd0a34 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h @@ -73,7 +73,7 @@ struct mlx5_pkt_reformat { int reformat_type; /* from mlx5_ifc */ enum mlx5_flow_resource_owner owner; union { - struct mlx5_fs_dr_action action; + struct mlx5_fs_dr_action fs_dr_action; u32 id; }; }; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c index 833cb68c744f..8dd412454c97 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c @@ -256,6 +256,7 @@ static int mlx5_cmd_dr_create_fte(struct mlx5_flow_root_namespace *ns, { struct mlx5dr_domain *domain = ns->fs_dr_domain.dr_domain; struct mlx5dr_action_dest *term_actions; + struct mlx5_pkt_reformat *pkt_reformat; struct mlx5dr_match_parameters params; struct mlx5_core_dev *dev = ns->dev; struct mlx5dr_action **fs_dr_actions; @@ -332,18 +333,19 @@ static int mlx5_cmd_dr_create_fte(struct mlx5_flow_root_namespace *ns, if (fte->act_dests.action.action & MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) { bool is_decap; - if (fte->act_dests.action.pkt_reformat->owner == MLX5_FLOW_RESOURCE_OWNER_FW) { + pkt_reformat = fte->act_dests.action.pkt_reformat; + if (pkt_reformat->owner == MLX5_FLOW_RESOURCE_OWNER_FW) { err = -EINVAL; mlx5dr_err(domain, "FW-owned reformat can't be used in SW rule\n"); goto free_actions; } - is_decap = fte->act_dests.action.pkt_reformat->reformat_type == + is_decap = pkt_reformat->reformat_type == MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2; if (is_decap) actions[num_actions++] = - fte->act_dests.action.pkt_reformat->action.dr_action; + pkt_reformat->fs_dr_action.dr_action; else delay_encap_set = true; } @@ -395,8 +397,7 @@ static int mlx5_cmd_dr_create_fte(struct mlx5_flow_root_namespace *ns, } if (delay_encap_set) - actions[num_actions++] = - fte->act_dests.action.pkt_reformat->action.dr_action; + actions[num_actions++] = pkt_reformat->fs_dr_action.dr_action; /* The order of the actions below is not important */ @@ -458,9 +459,11 @@ static int mlx5_cmd_dr_create_fte(struct mlx5_flow_root_namespace *ns, term_actions[num_term_actions].dest = tmp_action; if (dst->dest_attr.vport.flags & - MLX5_FLOW_DEST_VPORT_REFORMAT_ID) + MLX5_FLOW_DEST_VPORT_REFORMAT_ID) { + pkt_reformat = dst->dest_attr.vport.pkt_reformat; term_actions[num_term_actions].reformat = - dst->dest_attr.vport.pkt_reformat->action.dr_action; + pkt_reformat->fs_dr_action.dr_action; + } num_term_actions++; break; @@ -671,7 +674,7 @@ static int mlx5_cmd_dr_packet_reformat_alloc(struct mlx5_flow_root_namespace *ns } pkt_reformat->owner = MLX5_FLOW_RESOURCE_OWNER_SW; - pkt_reformat->action.dr_action = action; + pkt_reformat->fs_dr_action.dr_action = action; return 0; } @@ -679,7 +682,7 @@ static int mlx5_cmd_dr_packet_reformat_alloc(struct mlx5_flow_root_namespace *ns static void mlx5_cmd_dr_packet_reformat_dealloc(struct mlx5_flow_root_namespace *ns, struct mlx5_pkt_reformat *pkt_reformat) { - mlx5dr_action_destroy(pkt_reformat->action.dr_action); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Moshe Shemesh , "Yevgeny Kliteynik" , Tariq Toukan Subject: [PATCH net-next V3 15/15] net/mlx5: fs, rename modify header struct member action Date: Wed, 16 Oct 2024 20:36:17 +0300 Message-ID: <20241016173617.217736-16-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000467F:EE_|DS7PR12MB8203:EE_ X-MS-Office365-Filtering-Correlation-Id: 17c96d0f-01e3-41e0-5fa3-08dcee095005 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: 10PkB/xw5HRr8OOMRTpR7Lc0uCBiLYSOmao0Wk1/m2H/1RYdBoBx7RsBgenlISuTrdzpIWvuvG6e2FhtHEwOnlI4E/29s2KrZCdO8YDBoSNDFkMRXlE6FQQkusyA4OlPS67YWi8ATakttc1Q6ymdy2qOzB+5/gMf2lsfPYxpCYSLTqVn4aP+O8Zk/kzXFFow6uXRReTc8wMJBiJ0YF4DnRXuq2lx6C58NmomD358Qq9XmJE+z1h1yUfKUBlmTnnDAIbP2mi/umem6TWDWYeSPkbASMmYwYDE6j2sScl9h21AL/vLvcLtMW0Z3XHJc/pY4+RzzYrjmSoqZq4FMnIIOLW46rDd1lYPw9MiCPy50q3dubXTB1ukGwDDIJZIYYkeFXXZ4gtvxeOIgKToYvLhLkqmw5R5/+IYDwZFUvUmvuMxZ4eBvYpeV6p/QuvsUaPDhoeEfjgEht+51ZxYgc4/9aomlPaZQfA8Xs0DrdmeUEh3R/uWqCPqIh+H6mms+cwyX4dtmVJrDtzYB5hOSN4eohOIt5RRgzUWH7SNDVR7xs/qEW2QpHs4J3vW6Kpjtda3otFVIfvVk5Gqt8N/0o9rdjrVnzCPeavHGF9ySbpAHnr3TNhEC/CiANtVTwgXZIWV1jld51b6tKOB2XvzrjCwTKUf8me2PebZEtZpRdz3RrM5BJ4BOVzRLjtQtJDuw5MeWVWcDnO4QFu7yNo5idmmlIu+SjbDlku49CQDclUjYJbd0EIR4ARFxYq5ZODwuhdzCT0hQtF2ejqWoAs32XVMMwgi+2Dt7igX4vLdiqq79MPRj1OQCgsYn9Kic/sOyiTrsJvtGC+sbfpxM9wr15BhJlgei8zMKpIj/S7sKdDUtQSeIx87vry4pyoNwaVpGOlrIJhwepfF9G16OVNAikia9FkHGtrkFcBJq5AnAiVHW+8JjI7AtpJ0P+tabG6A/mE0R33lrZ/aGdVYKGTqPh/QDreV4PJ3i9furNjSX48mk+V3tM169iph4csw/o851qdMmBfbJR8tIpFSP1JTg18TldoEk20Frq7w3G4eMLFJ5iC0rFkEM0kZMsuxAlp1Bvb255S+Am8Z8IJ5ThMJTSSLn3HrVkYXqVPC11PyLYsNZbm0R4QTAuvMKdpc2d4vnXQLKRYllaCKG9y/qPdCfL7fkMr4tCncUz3vKBXzViJSASChTgkNNBsYEFfnUxLVic/xvGWwdF4jUMqv26PizgDkEjn9s3l699l2w9ftbolRezzQgzGmCb0+kZQtqEFblAIpniNixv1emSYjIor/6WZ5AJjpNlR8RiDKZ9aTwHnXedxYS8QqAfyKkHlK1Zw0/DW9OAszgkuc3mpKgX17KXzltM2Ywrqw03fl0DdV9QrxH0ryzItTJ4So2G2uRAzaTaaO X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:38:14.2382 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17c96d0f-01e3-41e0-5fa3-08dcee095005 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000467F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8203 X-Patchwork-Delegate: kuba@kernel.org From: Moshe Shemesh As preparation for HW Steering support, rename modify header struct member action to fs_dr_action, to distinguish from fs_hws_action which will be added. Add a pointer where needed to keep code line shorter and more readable. Reviewed-by: Yevgeny Kliteynik Signed-off-by: Moshe Shemesh Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en/tc/ct_fs_smfs.c | 4 ++-- drivers/net/ethernet/mellanox/mlx5/core/fs_core.h | 2 +- .../net/ethernet/mellanox/mlx5/core/steering/fs_dr.c | 12 +++++++----- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs_smfs.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs_smfs.c index 1c062a2e8996..45737d039252 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs_smfs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ct_fs_smfs.c @@ -318,7 +318,7 @@ mlx5_ct_fs_smfs_ct_rule_add(struct mlx5_ct_fs *fs, struct mlx5_flow_spec *spec, } actions[num_actions++] = smfs_rule->count_action; - actions[num_actions++] = attr->modify_hdr->action.dr_action; + actions[num_actions++] = attr->modify_hdr->fs_dr_action.dr_action; actions[num_actions++] = fs_smfs->fwd_action; nat = (attr->ft == fs_smfs->ct_nat); @@ -379,7 +379,7 @@ static int mlx5_ct_fs_smfs_ct_rule_update(struct mlx5_ct_fs *fs, struct mlx5_ct_ struct mlx5dr_rule *rule; actions[0] = smfs_rule->count_action; - actions[1] = attr->modify_hdr->action.dr_action; + actions[1] = attr->modify_hdr->fs_dr_action.dr_action; actions[2] = fs_smfs->fwd_action; rule = mlx5_smfs_rule_create(smfs_rule->smfs_matcher->dr_matcher, spec, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h index 195f1cbd0a34..b30976627c6b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h @@ -63,7 +63,7 @@ struct mlx5_modify_hdr { enum mlx5_flow_namespace_type ns_type; enum mlx5_flow_resource_owner owner; union { - struct mlx5_fs_dr_action action; + struct mlx5_fs_dr_action fs_dr_action; u32 id; }; }; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c index 8dd412454c97..4b349d4005e4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c @@ -372,9 +372,11 @@ static int mlx5_cmd_dr_create_fte(struct mlx5_flow_root_namespace *ns, actions[num_actions++] = tmp_action; } - if (fte->act_dests.action.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) - actions[num_actions++] = - fte->act_dests.action.modify_hdr->action.dr_action; + if (fte->act_dests.action.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) { + struct mlx5_modify_hdr *modify_hdr = fte->act_dests.action.modify_hdr; + + actions[num_actions++] = modify_hdr->fs_dr_action.dr_action; + } if (fte->act_dests.action.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) { tmp_action = create_action_push_vlan(domain, &fte->act_dests.action.vlan[0]); @@ -705,7 +707,7 @@ static int mlx5_cmd_dr_modify_header_alloc(struct mlx5_flow_root_namespace *ns, } modify_hdr->owner = MLX5_FLOW_RESOURCE_OWNER_SW; - modify_hdr->action.dr_action = action; + modify_hdr->fs_dr_action.dr_action = action; return 0; } @@ -713,7 +715,7 @@ static int mlx5_cmd_dr_modify_header_alloc(struct mlx5_flow_root_namespace *ns, static void mlx5_cmd_dr_modify_header_dealloc(struct mlx5_flow_root_namespace *ns, struct mlx5_modify_hdr *modify_hdr) { - mlx5dr_action_destroy(modify_hdr->action.dr_action); + mlx5dr_action_destroy(modify_hdr->fs_dr_action.dr_action); } static int