From patchwork Wed Oct 16 23:30:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 13839061 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59B7AD2F7D6 for ; Wed, 16 Oct 2024 23:33:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=VVT5NjucKejzRiT5jUNXrU8R/6dUkvf+IblHz9+7Bmc=; b=Wx4Mh7FIlM5qcXvBX0C/rv6zVl 6PkDRwxgA5CCMbGW+63I/J9KGBGRGs9wX+aXv5p9XYtBZ13h+i/kQ5o28UK2bXZHYTc+yvX3PS74+ 8ZcNnsPQjOg1dq6qQ5SR2UpwwMyRAfNKjslTq5C0dzTjk0xKnHr1HURFPypdNM7vAyiXRcOAgjWEA 8qxsI0ySk2AqxgplDqCoZLPz9UXQjtqL77VXA0jcTbSeNZ18M5CynjRDEHXj7AixLBRtCBk4h6fjE UdikYYu58Bt+C/gtN3Tj3v+Qy94ee1570UH/44/m+LGY2Cw4kJd4sEtL4+rMmQOw11JQv+BCNEwZ8 ID1e3TFQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t1DWW-0000000DEbX-49dZ; Wed, 16 Oct 2024 23:33:48 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t1DTg-0000000DECH-25Xd for linux-arm-kernel@lists.infradead.org; Wed, 16 Oct 2024 23:30:54 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUkOW095566; Wed, 16 Oct 2024 18:30:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1729121446; bh=VVT5NjucKejzRiT5jUNXrU8R/6dUkvf+IblHz9+7Bmc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kwETLeIbzrxTavbqp+dk4lTCsIk9zyNR/MzLT/n8mHYT1hbGpZ1y276vew32NvMLo Aftm7if1jM4KQeZ/4K3WvarHaP8VADl1LRYLHH4rPrSDL3T7FxGdef09HF5LETGIUr jPAc3jY9iSi/sPRdEYVNx8qLrolAXxx3sEJ8ikDY= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 49GNUkYI011740 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 16 Oct 2024 18:30:46 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 16 Oct 2024 18:30:46 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 16 Oct 2024 18:30:46 -0500 Received: from fllvsmtp7.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUj7i070988; Wed, 16 Oct 2024 18:30:45 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH 1/5] dt-bindings: soc: ti: ti,j721e-system-controller: Add PCIe ctrl property Date: Wed, 16 Oct 2024 18:30:40 -0500 Message-ID: <20241016233044.240699-2-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241016233044.240699-1-afd@ti.com> References: <20241016233044.240699-1-afd@ti.com> MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241016_163052_653256_C8BB6724 X-CRM114-Status: GOOD ( 10.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a pattern property for pcie-ctrl which can be part of this controller. Signed-off-by: Andrew Davis --- .../bindings/soc/ti/ti,j721e-system-controller.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml index 378e9cc5fac2a..2a64fc61d1262 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml @@ -68,6 +68,11 @@ patternProperties: description: The node corresponding to SoC chip identification. + "^pcie-ctrl@[0-9a-f]+$": + type: object + description: + This is the PCIe control region. + required: - compatible - reg From patchwork Wed Oct 16 23:30:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 13839062 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE119D2F7D2 for ; Wed, 16 Oct 2024 23:35:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=RJdIXxeQZdLKxRUVJuHwy/nEqfURaOs7bbsYKHNkBFU=; b=3BxR4E6IdCEUqGzhdmRr/c4zgL llwxUAo6vH1+xFEmjpLSfrMVTTcyPfY12gK8uxwo8ol6wy7nvj86/iWkMDnl5gKbqRY+J4NWSSPki QZvexOoDo+MruDTMznt24jW41fpfkAq1QCBPfknVq3YxosyV0GE/yqLiIqrsE1gC+idxAiGf6lA73 kyVFmJU+hjbrCZLhyKQrQRzLBZHoPNpyW8l8hEQyN2lEDp/dYUe+GafTtbBcYPx6KJLSMDFT8jJqg aziZrQiQZYPHrP/HiATS+rh2O5ldMQYEjs8Jnw5m41pCfDd6owLzJ4Xme6jx0SbiTWrF3OQYHtLT5 RNW4V3/g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t1DXz-0000000DEhQ-3nKP; Wed, 16 Oct 2024 23:35:19 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t1DTg-0000000DECK-2wGh for linux-arm-kernel@lists.infradead.org; Wed, 16 Oct 2024 23:30:55 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUkAi016130; Wed, 16 Oct 2024 18:30:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1729121446; bh=RJdIXxeQZdLKxRUVJuHwy/nEqfURaOs7bbsYKHNkBFU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=o69j6gGsn5BQhDdKgQGWCFQC58P6g1yLegtOnN8Q7Gz8y5ueDDcsYzMRAaeztnYXS pXyehI92st1robpEE3NPTielXWbQf1RnWd1kJEbCoIpUPqLfu1K83vemd0DlGvlTVP cIBvc+CgBSIX76CeSMHs2rk++SttAaYCnl30s+tE= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 49GNUkgH086782 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 16 Oct 2024 18:30:46 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 16 Oct 2024 18:30:46 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 16 Oct 2024 18:30:46 -0500 Received: from fllvsmtp7.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUj7j070988; Wed, 16 Oct 2024 18:30:46 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH 2/5] arm64: dts: ti: k3-j721e: Add PCIe ctrl node to scm_conf region Date: Wed, 16 Oct 2024 18:30:41 -0500 Message-ID: <20241016233044.240699-3-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241016233044.240699-1-afd@ti.com> References: <20241016233044.240699-1-afd@ti.com> MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241016_163053_029695_383ADBA2 X-CRM114-Status: GOOD ( 12.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe nodes. Signed-off-by: Andrew Davis --- .../boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 28 ++++++++++++++++--- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso index 4062709d65792..a8a502a6207f6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso @@ -38,7 +38,7 @@ pcie0_ep: pcie-ep@2900000 { reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; max-link-speed = <3>; num-lanes = <1>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 0da785be80ff4..3b08e71081df3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -44,6 +44,26 @@ scm_conf: scm-conf@100000 { #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; + pcie0_ctrl: pcie-ctrl@4070 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4070 0x4>; + }; + + pcie1_ctrl: pcie-ctrl@4074 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4074 0x4>; + }; + + pcie2_ctrl: pcie-ctrl@4078 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4078 0x4>; + }; + + pcie3_ctrl: pcie-ctrl@407c { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x407c 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x4080 0x50>; @@ -945,7 +965,7 @@ pcie0_rc: pcie@2900000 { interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; @@ -974,7 +994,7 @@ pcie1_rc: pcie@2910000 { interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; @@ -1003,7 +1023,7 @@ pcie2_rc: pcie@2920000 { interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; + ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; @@ -1032,7 +1052,7 @@ pcie3_rc: pcie@2930000 { interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; + ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>; max-link-speed = <3>; num-lanes = <2>; power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; From patchwork Wed Oct 16 23:30:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 13839060 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC806D2F7D2 for ; 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Wed, 16 Oct 2024 18:30:46 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 16 Oct 2024 18:30:46 -0500 Received: from fllvsmtp7.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUj7k070988; Wed, 16 Oct 2024 18:30:46 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH 3/5] arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm_conf region Date: Wed, 16 Oct 2024 18:30:42 -0500 Message-ID: <20241016233044.240699-4-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241016233044.240699-1-afd@ti.com> References: <20241016233044.240699-1-afd@ti.com> MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241016_163052_653361_9BB12021 X-CRM114-Status: GOOD ( 12.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe node. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 9386bf3ef9f68..45091aa0fb1b0 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -32,6 +32,11 @@ scm_conf: scm-conf@100000 { #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; + pcie1_ctrl: pcie-ctrl@4074 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4074 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x4080 0x20>; @@ -745,7 +750,7 @@ pcie1_rc: pcie@2910000 { interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; max-link-speed = <3>; num-lanes = <4>; power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; From patchwork Wed Oct 16 23:30:43 2024 Content-Type: text/plain; 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Wed, 16 Oct 2024 18:30:46 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH 4/5] arm64: dts: ti: k3-j721s2: Add PCIe ctrl node to scm_conf region Date: Wed, 16 Oct 2024 18:30:43 -0500 Message-ID: <20241016233044.240699-5-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241016233044.240699-1-afd@ti.com> References: <20241016233044.240699-1-afd@ti.com> MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241016_163056_870539_C8B2737A X-CRM114-Status: GOOD ( 13.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe node. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso index 5ff390915b75b..8c2cd99cf2b42 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso @@ -38,7 +38,7 @@ pcie1_ep: pcie-ep@2910000 { reg-names = "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names = "link_state"; interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; max-link-speed = <3>; num-lanes = <1>; power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 9ed6949b40e9d..b32b0ce8be462 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -57,6 +57,11 @@ phy_gmii_sel_cpsw: phy@34 { #phy-cells = <1>; }; + pcie1_ctrl: pcie-ctrl@74 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x74 0x4>; + }; + serdes_ln_ctrl: mux-controller@80 { compatible = "reg-mux"; reg = <0x80 0x10>; @@ -1398,7 +1403,7 @@ pcie1_rc: pcie@2910000 { interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; max-link-speed = <3>; num-lanes = <4>; power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; From patchwork Wed Oct 16 23:30:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 13839065 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 04241D2F7D6 for ; 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Wed, 16 Oct 2024 18:30:47 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 16 Oct 2024 18:30:47 -0500 Received: from fllvsmtp7.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUj7m070988; Wed, 16 Oct 2024 18:30:47 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH 5/5] arm64: dts: ti: k3-am64: Add PCIe ctrl node to main_conf region Date: Wed, 16 Oct 2024 18:30:44 -0500 Message-ID: <20241016233044.240699-6-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241016233044.240699-1-afd@ti.com> References: <20241016233044.240699-1-afd@ti.com> MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241016_163057_550823_5143A58B X-CRM114-Status: GOOD ( 11.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe node. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 7eae18399caa6..66587f20aa0fe 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -51,6 +51,11 @@ chipid@14 { reg = <0x00000014 0x4>; }; + pcie0_ctrl: pcie-ctrl@4070 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4070 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x4080 0x4>; @@ -1036,7 +1041,7 @@ pcie0_rc: pcie@f102000 { interrupt-names = "link_state"; interrupts = ; device_type = "pci"; - ti,syscon-pcie-ctrl = <&main_conf 0x4070>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; max-link-speed = <2>; num-lanes = <1>; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;