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Fri, 18 Oct 2024 09:11:03 +0000 Received: from PN3P287MB1171.INDP287.PROD.OUTLOOK.COM ([fe80::12a8:c951:3e4b:5a8a]) by PN3P287MB1171.INDP287.PROD.OUTLOOK.COM ([fe80::12a8:c951:3e4b:5a8a%4]) with mapi id 15.20.8069.020; Fri, 18 Oct 2024 09:11:03 +0000 From: Bhavin Sharma To: shawnguo@kernel.org, krzk+dt@kernel.org, robh@kernel.org Cc: Bhavin Sharma , Conor Dooley , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Peng Fan , Joao Paulo Goncalves , Hiago De Franco , Hugo Villeneuve , Michael Walle , Alexander Stein , Mathieu Othacehe , Gregor Herburger , Max Merchel , Tim Harvey , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] arm64: dts: imx8mp: Add Boundary Device Nitrogen8MP Universal SMARC Carrier Board Date: Fri, 18 Oct 2024 14:39:27 +0530 Message-ID: <20241018091023.29286-2-bhavin.sharma@siliconsignals.io> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241018091023.29286-1-bhavin.sharma@siliconsignals.io> References: <20241018091023.29286-1-bhavin.sharma@siliconsignals.io> X-ClientProxiedBy: PN3PR01CA0143.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:bf::7) To PN3P287MB1171.INDP287.PROD.OUTLOOK.COM (2603:1096:c01:1a1::5) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PN3P287MB1171:EE_|PN2P287MB0738:EE_ X-MS-Office365-Filtering-Correlation-Id: 9e432c67-21ce-4fb5-6710-08dcef54cab8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024|52116014|38350700014; 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Initial support includes: - Serial console - eMMC - SD card Signed-off-by: Bhavin Sharma --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mp-nitrogen-smarc-som.dtsi | 349 ++++++++++++++++++ .../imx8mp-nitrogen-smarc-universal-board.dts | 17 + 3 files changed, 367 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-universal-board.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 9d3df8b218a2..c7f4cf51dc14 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -173,6 +173,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-smarc-universal-board.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi new file mode 100644 index 000000000000..89f820ddad54 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Boundary Devices + * Copyright 2024 Silicon Signals Pvt. Ltd. + * + * Author : Bhavin Sharma + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" + +/ { + model = "Boundary Device Nitrogen8MP SMARC SoM"; + compatible = "boundary,imx8mp-nitrogen-smarc-som", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + function = LED_FUNCTION_POWER; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c6 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6>; + status = "okay"; + + mcp23018: gpio@20 { + compatible = "microchip,mcp23018"; + gpio-controller; + #gpio-cells = <0x2>; + reg = <0x20>; + interrupts-extended = <&gpio4 22 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <0x2>; + microchip,irq-mirror; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcp23018>; + reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; + }; +}; + +/* Console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* SD-card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c6: i2c6grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 + MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 + >; + }; + + pinctrl_mcp23018: mcp23018grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1c0 + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x100 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x10 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x150 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x150 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x150 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x150 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x150 + MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x150 + MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x150 + MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x150 + MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x150 + MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x10 + MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x140 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x14 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x154 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x154 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x154 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x154 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x154 + MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x154 + MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x154 + MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x154 + MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x154 + MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x14 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x12 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x152 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x152 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x152 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x152 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x152 + MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x152 + MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x152 + MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x152 + MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x152 + MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x12 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x140 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-universal-board.dts b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-universal-board.dts new file mode 100644 index 000000000000..4a08fa38dcde --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-universal-board.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Boundary Devices + * Copyright 2024 Silicon Signals Pvt. Ltd. + * + * Author : Bhavin Sharma + */ + +/dts-v1/; + +#include "imx8mp-nitrogen-smarc-som.dtsi" + +/ { + model = "Boundary Device Nitrogen8MP Universal SMARC Carrier Board"; + compatible = "boundary,imx8mp-nitrogen-smarc-universal-board", + "boundary,imx8mp-nitrogen-smarc-som", "fsl,imx8mp"; +}; From patchwork Fri Oct 18 09:09:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhavin Sharma X-Patchwork-Id: 13841438 Received: from IND01-BMX-obe.outbound.protection.outlook.com (mail-bmxind01on2103.outbound.protection.outlook.com [40.107.239.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0651E191F78 for ; Fri, 18 Oct 2024 09:11:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.239.103 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729242678; 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Signed-off-by: Bhavin Sharma Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b39a7e031177..58979c030519 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1097,6 +1097,12 @@ properties: - const: avnet,sm2s-imx8mp # SM2S-IMX8PLUS SoM - const: fsl,imx8mp + - description: Boundary Device Nitrogen8MP Universal SMARC Carrier Board + items: + - const: boundary,imx8mp-nitrogen-smarc-universal-board + - const: boundary,imx8mp-nitrogen-smarc-som + - const: fsl,imx8mp + - description: i.MX8MP DHCOM based Boards items: - enum: