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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Andrew Halaney , Simon Horman , Jon Hunter Cc: kernel@quicinc.com Subject: [PATCH net v1] net: stmmac: Disable PCS Link and AN interrupt when PCS AN is disabled Date: Fri, 18 Oct 2024 15:24:07 -0700 Message-Id: <20241018222407.1139697-1-quic_abchauha@quicinc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: nw6KsqhYcNVQIR2DbZb4gluPPVHacxjE X-Proofpoint-GUID: nw6KsqhYcNVQIR2DbZb4gluPPVHacxjE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 mlxscore=0 bulkscore=0 clxscore=1015 suspectscore=0 mlxlogscore=979 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410180143 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241018_152421_258185_0A4B1AC7 X-CRM114-Status: GOOD ( 12.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently we disable PCS ANE when the link speed is 2.5Gbps. mac_link_up callback internally calls the fix_mac_speed which internally calls stmmac_pcs_ctrl_ane to disable the ANE for 2.5Gbps. We observed that the CPU utilization is pretty high. That is because we saw that the PCS interrupt status line for Link and AN always remain asserted. Since we are disabling the PCS ANE for 2.5Gbps it makes sense to also disable the PCS link status and AN complete in the interrupt enable register. Interrupt storm Issue:- [ 25.465754][ C2] stmmac_pcs: Link Down [ 25.469888][ C2] stmmac_pcs: Link Down [ 25.474030][ C2] stmmac_pcs: Link Down [ 25.478164][ C2] stmmac_pcs: Link Down [ 25.482305][ C2] stmmac_pcs: Link Down [ 25.486441][ C2] stmmac_pcs: Link Down [ 25.486635][ C4] watchdog0: pretimeout event [ 25.490585][ C2] stmmac_pcs: Link Down [ 25.499341][ C2] stmmac_pcs: Link Down [ 25.503484][ C2] stmmac_pcs: Link Down [ 25.507619][ C2] stmmac_pcs: Link Down [ 25.511760][ C2] stmmac_pcs: Link Down [ 25.515897][ C2] stmmac_pcs: Link Down [ 25.520038][ C2] stmmac_pcs: Link Down [ 25.524174][ C2] stmmac_pcs: Link Down [ 25.528316][ C2] stmmac_pcs: Link Down [ 25.532451][ C2] stmmac_pcs: Link Down [ 25.536591][ C2] stmmac_pcs: Link Down [ 25.540724][ C2] stmmac_pcs: Link Down [ 25.544866][ C2] stmmac_pcs: Link Down Once we disabled PCS ANE and Link Status interrupt issue disappears. Fixes: a818bd12538c ("net: stmmac: dwmac-qcom-ethqos: Add support for 2.5G SGMII") Signed-off-by: Abhishek Chauhan --- drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c index e65a65666cc1..db77d07af9fe 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c @@ -751,7 +751,16 @@ static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex, static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral, bool loopback) { + u32 intr_mask = readl(ioaddr + GMAC_INT_EN); + dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback); + + if (!ane) + intr_mask &= ~(GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE); + else + intr_mask |= (GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE); + + writel(intr_mask, ioaddr + GMAC_INT_EN); } static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)