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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0a48903sm2276459f8f.37.2024.10.20.11.21.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 11:21:53 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/6] dt-bindings: timer: exynos4210-mct: Add samsung,exynos8895-mct compatible Date: Sun, 20 Oct 2024 21:21:16 +0300 Message-ID: <20241020182121.377969-2-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> References: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Just like most Samsung Exynos SoCs, Exynos8895 uses almost the same Multi-Core Timer block with no functional differences. Add dedicated samsung,exynos8895-mct compatible to the dt-schema for representing the MCT timer of Exynos8895 SoC. Signed-off-by: Ivaylo Ivanov Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/timer/samsung,exynos4210-mct.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index 774b7992a..02d1c3558 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -33,6 +33,7 @@ properties: - samsung,exynos5420-mct - samsung,exynos5433-mct - samsung,exynos850-mct + - samsung,exynos8895-mct - tesla,fsd-mct - const: samsung,exynos4210-mct @@ -133,6 +134,7 @@ allOf: - samsung,exynos5420-mct - samsung,exynos5433-mct - samsung,exynos850-mct + - samsung,exynos8895-mct then: properties: interrupts: From patchwork Sun Oct 20 18:21:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivaylo Ivanov X-Patchwork-Id: 13843197 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBEF619644B; Sun, 20 Oct 2024 18:21:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729448519; cv=none; b=XC9x7NtDITaDP+zRmcC4uD5EhyQL7rq10gsIVeVleatWkHNiDnBESJZCaiYRn9Pxz3NJP56oVSTJaAC21lmq07fNbJ4OmFqMCqccISJssjEeYzW0OaL++nHl7iN6Uus54I5jBIKkFlTBd/w64mreBk+cLvVjtGzJ8zwIDlfHF2g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729448519; c=relaxed/simple; bh=+SKnYOBkQ9uRpdUnkVZEGCogf+pRwPjMWuroZ0c6eOE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Px7Bo/hEjcoIUurLgm1obOnF9zLVZnygENput0mvZrpxjOUvB8flo2xHA1TzxKgS2ZuT3TLy+lZWGtdiAd5wQfOqUdpXbo8Br0BFv60qgvhH3BR930H/Lu+gpGdEP55GpT1asyHpicxhO1TRJT5FZJN1rsTwU23FINGVCF6WNG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Y3gMOSIt; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Y3gMOSIt" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-43162cf1eaaso30896675e9.0; Sun, 20 Oct 2024 11:21:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729448516; x=1730053316; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BOGuZBzdjkFcdt2iKU9LrAuNdSVHouuBuYJiJneV5u0=; b=Y3gMOSIthGBb6y7O2fNAGnkk1HWl/pOdX8/CUtRDm6kgavu7xUxF5o6KUyHLsms0a+ M2oUuefu+Yfn3m0buE4AoJzyLFnu4pKjOyQDWzAiPP5tfvqqc0SO1TxRgJN4hI6KQl+D /uqjLstolsQcnwl7UTZRbR8t9GQfOJMDn81AcMGO+tdS677wWbtlk9mViN88McccAZ55 ttmByJ2waRnvhhh8WbbHkeNsh/58QNpZhTsPkhRyVAhqqQYRNMj5ZqfN1gL5WuxYVQml bHcMXqslhzsxieOrrZmZhdS3tYfiIk42+dKyCAa2FP4ZSXJwW9oW5MVpeoiTrXeKZH3h mA2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729448516; x=1730053316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BOGuZBzdjkFcdt2iKU9LrAuNdSVHouuBuYJiJneV5u0=; b=iWYutMfubCpPRERHwwTm/rDdMT0/GWXzN/ZTDzEAAsMVJAUeTf3Fg2vU7B9ekESFBl 93ap+vOEvdqQE/Vs5qsWPW6viXP0XkZVykgNFrlPLAWYCiGbz7D9eT0Br1s4aa94ogtm rbReU7YpmEbloHfy81dqHgqqnh1DKG4QKyq9m63jeENpBO2TJQtAshJRlLH3E9JH/T+w uUPPnLf1xer4jZ5RbmwhqwphAs7srUV5d18T9tP25YCxbwnG0Ia5cAjMhcyafEEwMw0q CLddQKN0Vc3pC0299TyXQuhn4/swj53bhSjCS56Podt0f4FDlRVdstCqqy6EBuBuGi20 ujRA== X-Forwarded-Encrypted: i=1; AJvYcCV1V8Sovo/FGIQIoGQDBlKeIrJaG69Y9Dtah2ITWNA0iV4d021JlZg9MkR+uHqvHzPkn47eJYgAFFphzKUS@vger.kernel.org, AJvYcCVgBV7RcIwwTd4f9LgTgcrg0UzbrK0aOeR+uq9hTJQqnLxf4Nz1nlFmohBN6HWVOiStx8yan+I1xWp0@vger.kernel.org, AJvYcCWhauoq5qgxn4q52uwQTPF0uIDpvQqG1R3ItmhrDBxLHXfh4hSXmJ7zdYDoqVokqGw0votEZfLpHdfWUKM+dtg3l0U=@vger.kernel.org X-Gm-Message-State: AOJu0Yy8HSDjMs8yCngV01KI6Rxgw+2KDT7M9vmbo7wF4TWc+uEB8p8X Pr/QpE4okN/GfKuZUGoFmy6LrS5F31RO4HMWXXBsZOyUmMuXaV40/QHRbjhx X-Google-Smtp-Source: AGHT+IERV5gK0lNy0vobuAkOc9gFbu9smR5sqdfQrx4tjIF3P+r9hp2ckFPSqHYP7ZHOB662YVTfoQ== X-Received: by 2002:a05:600c:3511:b0:431:54f3:11ab with SMTP id 5b1f17b1804b1-43161691204mr93465895e9.33.1729448515987; Sun, 20 Oct 2024 11:21:55 -0700 (PDT) Received: from ivaylo-T580.. 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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0a48903sm2276459f8f.37.2024.10.20.11.21.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 11:21:55 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/6] spi: dt-bindings: samsung: Add a compatible for samsung,exynos8895-spi Date: Sun, 20 Oct 2024 21:21:17 +0300 Message-ID: <20241020182121.377969-3-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> References: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 According to the vendor kernel, the Exynos8895 SoC has an SPI configuration that matches with the Exynos850 one. SPI FIFO depth is 64 bytes for all SPI blocks. All blocks have DIV_4 as the default internal clock divider, and an internal loopback mode to run a loopback test. Reuse the samsung,exynos850-spi compatible. Signed-off-by: Ivaylo Ivanov Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/spi/samsung,spi.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml index f681372da..3c206a64d 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -26,6 +26,10 @@ properties: - samsung,exynos850-spi - samsung,exynosautov9-spi - tesla,fsd-spi + - items: + - enum: + - samsung,exynos8895-spi + - const: samsung,exynos850-spi - const: samsung,exynos7-spi deprecated: true From patchwork Sun Oct 20 18:21:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivaylo Ivanov X-Patchwork-Id: 13843198 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6590E197A81; Sun, 20 Oct 2024 18:21:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729448521; cv=none; b=ZwVTfz0Flc/w2EXbNYsJpPkNkd0Dj9jxkwq/0YYvXuwLYazCYtM2JwXlv0KlTqnjSdoD1v3gEUT6uXuilwBJwfNNMEjh220Jb8DfXEjuq5a4Aff1gBNRIiiHCcuwYoK0Dz66eoYX/k6l4ssoXOnZa9TZSAeSXzy4AENIZBurI4c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729448521; c=relaxed/simple; bh=Owgw5vMmpv+QSuNxHW76hpQPPLHvuGsaZd0es3OPokE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KHyQa/2/8R6me8cmf+cQmDr+QWyNiMaf2i/W+f2qp4tGhB+6T55oIhw/S0/kHvugvm48RrowAzC5DpvU/K/ad1bUsUGj397Is1oM1PekW2krl0Lg95ebRXrVgs+0t0JDya/oaIvt69SMzo9e2QG6lv3AYOurkAT9MX+8N9lsI9A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=f028NmKr; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="f028NmKr" Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-37d41894a32so2391428f8f.1; Sun, 20 Oct 2024 11:21:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729448517; x=1730053317; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YB/d8ya+iA886QHQfDVagGNmaaeyxRfUU+uDgU8KNSI=; b=f028NmKrYmmfIO4Z+6DnPlbQ9Vmu31G1CfXjXtNirt0+cYxrdiOOBUH7ct+vql0Cxd uTkRFn23bXNsFdz3zcD/yGbPzH41ai91HSziPivc88EwRA32AW7ii1A3qKDzcHem50JZ 1vJiMJhDf0NNJE4VSIIZ6xBD7vKsoMRCFfgUGBsNO2NbGfzLCnDzR+R1YmCX/Qp4bqo/ ibmATFYLnsvvoE/NcE1RrYMe12m3tRCxoNRlnkX1Jtmo4VFoxbWYICDxUPMK58X9NOhT a6cVhbbCWRiOHpLDXUGevuE9Dpahvsh7YhK8EAEHNdpEdTC6uVzENjUZmW3uLhnLwGAY bHeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729448517; x=1730053317; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YB/d8ya+iA886QHQfDVagGNmaaeyxRfUU+uDgU8KNSI=; b=Fv7NRMrk8s4tn4BQWIc/Odh/A4vWgqRtO7ldlTBsilimL3ZooVdYvPgCDqwbb/I8uj uUYO6elUvfqJgo/3Vp1fYyVJJ9YHSdgo35o7Lt0xqopn0Sxi347PbGEG1fJt+XNeBIVI 8X9WjRvdK3QuG2SzJO8d5wky0ODa+b4a1AcvAFNDNrN92j+6LRiTVkAPFM6dS4Ass0dj yuTT/L56af+MQ37GoMxNOlaWRrMAXhqFOokHufH9RGbQ66XR4oQymsU7CKOXzXumxKDu YXxB3YBGOo2k/b+bPKcmw4vnYYAowWf5phikVixXCbJkJD7r+Nn8NWe2zAJVbNxRRu2V yk0Q== X-Forwarded-Encrypted: i=1; AJvYcCUNtgvkBtdI7SG70+ICBFtsf6tFIAUeLXdXAKUWXVHLLjg4SVItzup2RzGv3bqwwp5RIAlwF7j8izTfvQmaP8NGcBg=@vger.kernel.org, AJvYcCW7YMwj2CykXJlNtMVRba6DppmtaYtbX4l8yyq/yOFG8IOPdcjmwA14+FWRbrKm5TWS77CVcs6dNhEV3KDM@vger.kernel.org, AJvYcCWQoupG3qkR3TeYQwDEZMJ8Jy9t47487EqZZmkgvByuahjOjLtCWaqD+4A1OPbaNJG2i3KQYo8Fv689@vger.kernel.org X-Gm-Message-State: AOJu0YweaLU3Bx41kjhTdNLBjFXw/6DEJmjjT5sAdNvH0/rf2b0KX1hD kxs4YlUNo9i97HyO2jx6JOXSnRKGtvcpbF7V50GsWYUM5EZDwn9oEY8dflTi X-Google-Smtp-Source: AGHT+IGugZhfDYe/BbnZuzhu75x/LfLnNt9NNzUAVI8e+4gLSVOjfsqQBBgKKgOE12vwsXyIiSmRbA== X-Received: by 2002:a05:6000:183:b0:376:dbb5:10c2 with SMTP id ffacd0b85a97d-37ecf08650fmr5774026f8f.29.1729448517433; Sun, 20 Oct 2024 11:21:57 -0700 (PDT) Received: from ivaylo-T580.. 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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0a48903sm2276459f8f.37.2024.10.20.11.21.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 11:21:57 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/6] arm64: dts: exynos: Add clock management unit nodes Date: Sun, 20 Oct 2024 21:21:18 +0300 Message-ID: <20241020182121.377969-4-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> References: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add clock management unit nodes for: - cmu_top, which provides muxes, divs and gates for other CMUs - cmu_peris, which provides clocks for GIC and MCT - cmu_fsys0, which provides clocks for USBDRD30 - cmu_fsys1, which provides clocks for MMC, UFS and PCIE - cmu_peric0, which provides clocks for UART_DBG, USI00 ~ USI03 - cmu_peric1, which provides clocks for SPI_CAM0/1, UART_BT, USI04 ~ USI13 Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos8895.dtsi | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi index 223ebd482..802e135c4 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2024, Ivaylo Ivanov */ +#include #include / { @@ -159,6 +160,15 @@ chipid@10000000 { reg = <0x10000000 0x24>; }; + cmu_peris: clock-controller@10010000 { + compatible = "samsung,exynos8895-cmu-peris"; + reg = <0x10010000 0x8000>; + #clock-cells = <1>; + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIS_BUS>; + clock-names = "oscclk", "bus"; + }; + gic: interrupt-controller@10201000 { compatible = "arm,gic-400"; reg = <0x10201000 0x1000>, @@ -173,24 +183,93 @@ gic: interrupt-controller@10201000 { #size-cells = <1>; }; + cmu_peric0: clock-controller@10400000 { + compatible = "samsung,exynos8895-cmu-peric0"; + reg = <0x10400000 0x8000>; + #clock-cells = <1>; + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC0_UART_DBG>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI00>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI01>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI02>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI03>; + clock-names = "oscclk", "bus", "uart_dbg", "usi00", + "usi01", "usi02", "usi03"; + }; + pinctrl_peric0: pinctrl@104d0000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x104d0000 0x1000>; interrupts = ; }; + cmu_peric1: clock-controller@10800000 { + compatible = "samsung,exynos8895-cmu-peric1"; + reg = <0x10800000 0x8000>; + #clock-cells = <1>; + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC1_SPEEDY2>, + <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM0>, + <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM1>, + <&cmu_top CLK_DOUT_CMU_PERIC1_UART_BT>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI04>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI05>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI06>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI07>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI08>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI09>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI10>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI11>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI12>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI13>; + clock-names = "oscclk", "bus", "speedy2", "cam0", + "cam1", "uart_bt", "usi04", "usi05", + "usi06", "usi07", "usi08", "usi09", + "usi10", "usi11", "usi12", "usi13"; + }; + pinctrl_peric1: pinctrl@10980000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x10980000 0x1000>; interrupts = ; }; + cmu_fsys0: clock-controller@11000000 { + compatible = "samsung,exynos8895-cmu-fsys0"; + reg = <0x11000000 0x8000>; + #clock-cells = <1>; + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_FSYS0_BUS>, + <&cmu_top CLK_DOUT_CMU_FSYS0_DPGTC>, + <&cmu_top CLK_DOUT_CMU_FSYS0_MMC_EMBD>, + <&cmu_top CLK_DOUT_CMU_FSYS0_UFS_EMBD>, + <&cmu_top CLK_DOUT_CMU_FSYS0_USBDRD30>; + clock-names = "oscclk", "bus", + "dpgtc", "mmc_embd", + "ufs_embd", "usbdrd30"; + }; + pinctrl_fsys0: pinctrl@11050000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x11050000 0x1000>; interrupts = ; }; + cmu_fsys1: clock-controller@11400000 { + compatible = "samsung,exynos8895-cmu-fsys1"; + reg = <0x11400000 0x8000>; + #clock-cells = <1>; + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_FSYS1_BUS>, + <&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>, + <&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>, + <&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>; + clock-names = "oscclk", "bus", "mmc_card", + "pcie", "ufs_card"; + }; + pinctrl_fsys1: pinctrl@11430000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x11430000 0x1000>; @@ -213,6 +292,14 @@ pinctrl_busc: pinctrl@15a30000 { interrupts = ; }; + cmu_top: clock-controller@15a80000 { + compatible = "samsung,exynos8895-cmu-top"; + reg = <0x15a80000 0x8000>; + #clock-cells = <1>; + clocks = <&oscclk>; + clock-names = "oscclk"; + }; + pmu_system_controller: system-controller@16480000 { compatible = "samsung,exynos8895-pmu", "samsung,exynos7-pmu", "syscon"; From patchwork Sun Oct 20 18:21:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivaylo Ivanov X-Patchwork-Id: 13843199 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE371198A03; Sun, 20 Oct 2024 18:22:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0a48903sm2276459f8f.37.2024.10.20.11.21.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 11:21:58 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/6] arm64: dts: exynos8895: Add Multi Core Timer (MCT) node Date: Sun, 20 Oct 2024 21:21:19 +0300 Message-ID: <20241020182121.377969-5-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> References: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 MCT has one global timer and 8 CPU local timers. The global timer can generate 4 interrupts, and each local timer can generate an interrupt making 12 interrupts in total. Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos8895.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi index 802e135c4..c95e4713a 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -169,6 +169,26 @@ cmu_peris: clock-controller@10010000 { clock-names = "oscclk", "bus"; }; + timer@10040000 { + compatible = "samsung,exynos8895-mct", + "samsung,exynos4210-mct"; + reg = <0x10040000 0x800>; + clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + }; + gic: interrupt-controller@10201000 { compatible = "arm,gic-400"; reg = <0x10201000 0x1000>, From patchwork Sun Oct 20 18:21:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivaylo Ivanov X-Patchwork-Id: 13843200 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C2B2198E63; Sun, 20 Oct 2024 18:22:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729448524; cv=none; b=OYNzWFGae+Dc+aKhogz5EEhDFjZ4Gi3C3bKedDVPXarx9KuRxK4mFEk2Cj1ttnKx4AWLGSavhAJHkmt8e+AvOgFmm+8K9h+YMvhF007WqqSYbGUxg+PN0vXNW1cm1xvvGu6Cdn7fRN8TfvPzP0i0lK0FW7IE+tPASwpxtzSMrBA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729448524; c=relaxed/simple; bh=AlHhXPUTaX7Z/aFRoI6MpFzKLTUW5hcy6mq+BW3Wl7Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YCGTBfhyh1+qV3BHjeVRAYa1eS3sq01dClKbESQqO9Sf1eTo3lDT2OIXPpngb6XvAuSRNz8cicR0CkkkIzdu0Sy+VTfeUzE7S6vInOz6X+n2gv537ua7k9xh8Y0xcSg9tCIOhiAbM8N4XRTQoD8CjINw8w2Xnz1APbaujK9lhLA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=AGhzaqNQ; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AGhzaqNQ" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-4314a26002bso40909185e9.0; Sun, 20 Oct 2024 11:22:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1729448521; x=1730053321; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vusWTnCz/1sObXYKY1keEPs26uHgXaV2tYOQstmgfG4=; b=AGhzaqNQmThR/rnAiWum5yNC/ZBkt27GkrB8lYj9O3NqKptVjfpzMlFA1ieLPKu3F1 YxMW4tSOSLFj8rQDJp9id7a5KV2FXuvS2+LL53UFx0Chx8LHOYM60/PAYEfRlY2JxxWB zMSNYVwjrr5MzkB21xrdTivGco6T/6FfSVvZfI267LuORe0+FUJqJKv82bV2CqIau+UV dmbcBjAqhCygejr43z+Z7r5AGT3p8L1ONF6O1huL1WdRooWpHM07Zp+12qMz6gKMik7V +fS/rVSR1m44q7iTpFBbqyWcTP2AW+noMR1CjoWnYXc0zncCFiP2GrrriReYzm+Dj8nn S3oA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1729448521; x=1730053321; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vusWTnCz/1sObXYKY1keEPs26uHgXaV2tYOQstmgfG4=; b=DfBd1RxdsrEckKcBsOoXSFleBqc4pEbQIyIKTD4kcTqRTg1PsSM1p4JWKBvk3eW5iN zqmA/GQWvYv4bBpGBxmhWY6FLfwFoaOkeBBfMTN8V8TQ8Sxm142giq1IjGc811T/sAd/ MzhvVJNsoe5YS+2y+QZyqIJLOqSEuNvP/7Fb1ahNDsRGeruVrqv0do3Crhv+VtqLsVjk ctrQHHD3JMnnM43E+5h6PszJWkp5UQVADe6ZgjCaG+0p4s7D1ZZmWa0Hy4ZJrIjcNdZu rUD3kpxtF+zH1vw1zPqsvQZdu7gXU7mXg/pn7sQCNPybPx/Zj7dtNBUdCuPVhMnGZdrq qSbg== X-Forwarded-Encrypted: i=1; AJvYcCVCO7dUoa/7wm+peysZVnbFmggtxwdnf958hgJAcnMZPa49ZP8gI1LKPFa7JlUkoy/HseTIqNjtpyBX@vger.kernel.org, AJvYcCVY4hjGCMsAb4Fbh+JCM8uptrsJ233Bv5Zpr2J1/Z9ZA1nfO3OsAZnPzcsqSFSesR8x9vt8TBINmwga4YXSfjNpiEY=@vger.kernel.org, AJvYcCWu0ZWAT/w5ZkAq7VbHN76bvwWyStUTcvGyfy1bgFnJL9iABNmC2eaAR5Sw9V92gES1OgSl1R6Qh3zZ41qK@vger.kernel.org X-Gm-Message-State: AOJu0YwfAKif8rntqptOoS5vQpSn7Q74hvgHed6TTjGT51wuoKe6rZJl hrsysmMBZKiPt0udv1jNLt0R+WZ+B/BeaoDDWfOv10+hIvDXH+zBwK2AGDiM X-Google-Smtp-Source: AGHT+IEVn1bgu6i8w+sQTRqs3eb30dA3LNaVp1FKzkemUXiHiVF+qKDmNgVm3K2iwD+2dK1ZsiInZg== X-Received: by 2002:adf:f209:0:b0:378:fe6e:50ef with SMTP id ffacd0b85a97d-37eab7272damr5381184f8f.5.1729448520680; Sun, 20 Oct 2024 11:22:00 -0700 (PDT) Received: from ivaylo-T580.. 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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0a48903sm2276459f8f.37.2024.10.20.11.21.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 11:21:59 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/6] arm64: dts: exynos8895: Add serial_0/1 nodes Date: Sun, 20 Oct 2024 21:21:20 +0300 Message-ID: <20241020182121.377969-6-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> References: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add nodes for serial_0 (UART_DBG) and serial_1 (UART_BT), which allows using them. Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos8895.dtsi | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi index c95e4713a..c57b7243d 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -218,6 +218,19 @@ cmu_peric0: clock-controller@10400000 { "usi01", "usi02", "usi03"; }; + serial_0: serial@10430000 { + compatible = "samsung,exynos8895-uart"; + reg = <0x10430000 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + pinctrl_peric0: pinctrl@104d0000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x104d0000 0x1000>; @@ -250,6 +263,19 @@ cmu_peric1: clock-controller@10800000 { "usi10", "usi11", "usi12", "usi13"; }; + serial_1: serial@10830000 { + compatible = "samsung,exynos8895-uart"; + reg = <0x10830000 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_EXT_UCLK>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_bus>; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + pinctrl_peric1: pinctrl@10980000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x10980000 0x1000>; From patchwork Sun Oct 20 18:21:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivaylo Ivanov X-Patchwork-Id: 13843201 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EE1D1990BB; Sun, 20 Oct 2024 18:22:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0a48903sm2276459f8f.37.2024.10.20.11.22.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Oct 2024 11:22:01 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 6/6] arm64: dts: exynos8895: Add spi_0/1 nodes Date: Sun, 20 Oct 2024 21:21:21 +0300 Message-ID: <20241020182121.377969-7-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> References: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add nodes for spi_0 (SPI_CAM0) and spi_1 (SPI_CAM1), which allows using them. Signed-off-by: Ivaylo Ivanov --- arch/arm64/boot/dts/exynos/exynos8895.dtsi | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi index c57b7243d..d936c7bc9 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -282,6 +282,36 @@ pinctrl_peric1: pinctrl@10980000 { interrupts = ; }; + spi_0: spi@109d0000 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x109d0000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM0_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM0_SPI_EXT_CLK>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi0_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + spi_1: spi@109e0000 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x109e0000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM1_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM1_SPI_EXT_CLK>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi1_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + cmu_fsys0: clock-controller@11000000 { compatible = "samsung,exynos8895-cmu-fsys0"; reg = <0x11000000 0x8000>;