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Add edma2, sai6, sai7, spdif device nodes in bus of per_bridge5. Signed-off-by: Shengjiu Wang --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 212 +++++++++++++++++++++ 1 file changed, 212 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index e32d5afcf4a9..9930bc1cd5ff 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -212,6 +212,70 @@ per_bridge3: bus@29000000 { #size-cells = <1>; ranges; + edma1: dma-controller@29010000 { + compatible = "fsl,imx8ulp-edma"; + reg = <0x29010000 0x210000>; + #dma-cells = <3>; + dma-channels = <32>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>, + <&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>, + <&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>, + <&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>, + <&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>, + <&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>, + <&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>, + <&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>, + <&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>, + <&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>, + <&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>, + <&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>, + <&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>, + <&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>, + <&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>, + <&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>, + <&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>; + clock-names = "dma", "ch00","ch01", "ch02", "ch03", + "ch04", "ch05", "ch06", "ch07", + "ch08", "ch09", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24", "ch25", "ch26", "ch27", + "ch28", "ch29", "ch30", "ch31"; + }; + mu: mailbox@29220000 { compatible = "fsl,imx8ulp-mu"; reg = <0x29220000 0x10000>; @@ -442,6 +506,36 @@ lpuart7: serial@29870000 { status = "disabled"; }; + sai4: sai@29880000 { + compatible = "fsl,imx8ulp-sai"; + reg = <0x29880000 0x10000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_SAI4>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 67 0 1>, <&edma1 68 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + fsl,dataline = <0 0x03 0x03>; + status = "disabled"; + }; + + sai5: sai@29890000 { + compatible = "fsl,imx8ulp-sai"; + reg = <0x29890000 0x10000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_SAI5>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 69 0 1>, <&edma1 70 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + fsl,dataline = <0 0x0f 0x0f>; + status = "disabled"; + }; + iomuxc1: pinctrl@298c0000 { compatible = "fsl,imx8ulp-iomuxc1"; reg = <0x298c0000 0x10000>; @@ -614,6 +708,70 @@ per_bridge5: bus@2d800000 { #size-cells = <1>; ranges; + edma2: dma-controller@2d800000 { + compatible = "fsl,imx8ulp-edma"; + reg = <0x2d800000 0x210000>; + #dma-cells = <3>; + dma-channels = <32>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>, + <&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>, + <&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>, + <&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>, + <&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>, + <&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>, + <&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>, + <&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>, + <&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>, + <&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>, + <&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>, + <&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>, + <&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>, + <&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>, + <&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>, + <&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>, + <&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>; + clock-names = "dma", "ch00","ch01", "ch02", "ch03", + "ch04", "ch05", "ch06", "ch07", + "ch08", "ch09", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24", "ch25", "ch26", "ch27", + "ch28", "ch29", "ch30", "ch31"; + }; + cgc2: clock-controller@2da60000 { compatible = "fsl,imx8ulp-cgc2"; reg = <0x2da60000 0x10000>; @@ -626,6 +784,60 @@ pcc5: clock-controller@2da70000 { #clock-cells = <1>; #reset-cells = <1>; }; + + sai6: sai@2da90000 { + compatible = "fsl,imx8ulp-sai"; + reg = <0x2da90000 0x10000>; + interrupts = ; + clocks = <&pcc5 IMX8ULP_CLK_SAI6>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 71 0 1>, <&edma2 72 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + fsl,dataline = <0 0x0f 0x0f>; + status = "disabled"; + }; + + sai7: sai@2daa0000 { + compatible = "fsl,imx8ulp-sai"; + reg = <0x2daa0000 0x10000>; + interrupts = ; + clocks = <&pcc5 IMX8ULP_CLK_SAI7>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 73 0 1>, <&edma2 74 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + fsl,dataline = <0 0x0f 0x0f>; + status = "disabled"; + }; + + spdif: spdif@2dab0000 { + compatible = "fsl,imx8ulp-spdif"; + reg = <0x2dab0000 0x10000>; + interrupts = ; + clocks = <&pcc5 IMX8ULP_CLK_SPDIF>, /* core */ + <&sosc>, /* 0, extal */ + <&cgc2 IMX8ULP_CLK_SPDIF_SEL>, /* 1, tx */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 2, tx1 */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 3, tx2 */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 4, tx3 */ + <&pcc5 IMX8ULP_CLK_SPDIF>, /* 5, sys */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 6, tx4 */ + <&cgc1 IMX8ULP_CLK_DUMMY>, /* 7, tx5 */ + <&cgc1 IMX8ULP_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; 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It supports wb profile as default Signed-off-by: Shengjiu Wang --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index e937e5f8fa8b..7d6d332fa779 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -11,6 +11,11 @@ / { model = "NXP i.MX8ULP EVK"; compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; + bt_sco_codec: bt-sco-codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + chosen { stdout-path = &lpuart5; }; @@ -83,6 +88,25 @@ clock_ext_ts: clock-ext-ts { clock-output-names = "ext_ts_clk"; #clock-cells = <0>; }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai5>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; }; &cm33 { @@ -153,6 +177,16 @@ ptn5150_2: typec@3d { }; }; +&sai5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai5>; + pinctrl-1 = <&pinctrl_sai5>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SAI5_SEL>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; + fsl,dataline = <1 0x08 0x01>; + status = "okay"; +}; + &usbotg1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; @@ -282,6 +316,15 @@ MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20 >; }; + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8ULP_PAD_PTF26__I2S5_TX_BCLK 0x43 + MX8ULP_PAD_PTF27__I2S5_TX_FS 0x43 + MX8ULP_PAD_PTF28__I2S5_TXD0 0x43 + MX8ULP_PAD_PTF24__I2S5_RXD3 0x43 + >; + }; + pinctrl_typec1: typec1grp { fsl,pins = < MX8ULP_PAD_PTF3__PTF3 0x3 From patchwork Tue Oct 22 05:29:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shengjiu Wang X-Patchwork-Id: 13845104 Received: from EUR03-VI1-obe.outbound.protection.outlook.com (mail-vi1eur03on2061.outbound.protection.outlook.com [40.107.103.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4853513B58F for ; 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This sound card supports only playback sound through HDMI interface. Signed-off-by: Shengjiu Wang --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 7d6d332fa779..290a49bea2f7 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -107,6 +107,18 @@ simple-audio-card,codec { sound-dai = <&bt_sco_codec 1>; }; }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + audio-cpu = <&spdif>; + audio-codec = <&spdif_out>; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; }; &cm33 { @@ -187,6 +199,15 @@ &sai5 { status = "okay"; }; +&spdif { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_spdif>; + pinctrl-1 = <&pinctrl_spdif>; + assigned-clocks = <&cgc2 IMX8ULP_CLK_SPDIF_SEL>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; + status = "okay"; +}; + &usbotg1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; @@ -325,6 +346,12 @@ MX8ULP_PAD_PTF24__I2S5_RXD3 0x43 >; }; + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX8ULP_PAD_PTF25__SPDIF_OUT1 0x43 + >; + }; + pinctrl_typec1: typec1grp { fsl,pins = < MX8ULP_PAD_PTF3__PTF3 0x3