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Wed, 23 Oct 2024 10:52:54 -0400 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Wed, 23 Oct 2024 10:52:53 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Wed, 23 Oct 2024 10:52:53 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Wed, 23 Oct 2024 10:52:53 -0400 Received: from [127.0.0.1] ([10.44.3.54]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 49NEqewX002884; Wed, 23 Oct 2024 10:52:48 -0400 From: Nuno Sa Date: Wed, 23 Oct 2024 16:56:54 +0200 Subject: [PATCH 1/2] dt-bindings: clock: axi-clkgen: include AXI clk Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241023-axi-clkgen-fix-axiclk-v1-1-980a42ba51c3@analog.com> References: <20241023-axi-clkgen-fix-axiclk-v1-0-980a42ba51c3@analog.com> In-Reply-To: <20241023-axi-clkgen-fix-axiclk-v1-0-980a42ba51c3@analog.com> To: , CC: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lars-Peter Clausen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729695419; l=2003; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=jcoVhTeiNKgBu1aR77LhfBqpwO0tnvNIDveD9ZBC8/g=; b=9JgADfv4yO/ALTiqMNvyXLdMjiyPY5V8TFBySFiattSeS2r/J9YZQ5SFjM7QxC0+sJTJkGlSf gtyIy2v+JyQAi6SHu87hMfTjxsLul9Q+k0F5HvFXSdf36UXPW1Tmwu5 X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: XK763ArH2IOPqIjkG-V-oltp3H1WC0qv X-Proofpoint-ORIG-GUID: XK763ArH2IOPqIjkG-V-oltp3H1WC0qv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 bulkscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 spamscore=0 priorityscore=1501 mlxscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410230090 In order to access the registers of the HW, we need to make sure that the AXI bus clock is enabled. Hence let's increase the number of clocks by one. In order to keep backward compatibility, the new axi clock must be the last phandle in the array. To make the intent clear, a non mandatory clock-names property is also being added. Fixes: 0e646c52cf0e ("clk: Add axi-clkgen driver") Signed-off-by: Nuno Sa Acked-by: Conor Dooley --- .../devicetree/bindings/clock/adi,axi-clkgen.yaml | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml index 5e942bccf27787d7029f76fc1a284232fb7f279d..f5f80e61c119b8a68cb6e7a26ed275764f8d200f 100644 --- a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml +++ b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml @@ -26,9 +26,21 @@ properties: description: Specifies the reference clock(s) from which the output frequency is derived. This must either reference one clock if only the first clock - input is connected or two if both clock inputs are connected. - minItems: 1 - maxItems: 2 + input is connected or two if both clock inputs are connected. The last + clock is the AXI bus clock that needs to be enabled so we can access the + core registers. + minItems: 2 + maxItems: 3 + + clock-names: + oneOf: + - items: + - const: clkin1 + - const: s_axi_aclk + - items: + - const: clkin1 + - const: clkin2 + - const: s_axi_aclk '#clock-cells': const: 0 @@ -50,5 +62,6 @@ examples: compatible = "adi,axi-clkgen-2.00.a"; #clock-cells = <0>; reg = <0xff000000 0x1000>; - clocks = <&osc 1>; + clocks = <&osc 1>, <&clkc 15>; + clock-names = "clkin1", "s_axi_aclk"; }; From patchwork Wed Oct 23 14:56:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nuno Sa X-Patchwork-Id: 13847237 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EC981C728E; Wed, 23 Oct 2024 14:53:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 23 Oct 2024 10:52:49 -0400 From: Nuno Sa Date: Wed, 23 Oct 2024 16:56:55 +0200 Subject: [PATCH 2/2] clk: clk-axi-clkgen: make sure to enable the AXI bus clock Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241023-axi-clkgen-fix-axiclk-v1-2-980a42ba51c3@analog.com> References: <20241023-axi-clkgen-fix-axiclk-v1-0-980a42ba51c3@analog.com> In-Reply-To: <20241023-axi-clkgen-fix-axiclk-v1-0-980a42ba51c3@analog.com> To: , CC: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lars-Peter Clausen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1729695419; l=2577; i=nuno.sa@analog.com; s=20231116; h=from:subject:message-id; bh=RzVlX88H7cb+6ZDvccxbbjBTkNbEap1Nd1RhwgPzGzU=; b=Zssdh8uYJAQp7UDtR98eV3iyj7ARjLCUpPKv7lQtMmYwNis7IaMc16P5yWdMf3NuHKChnEofc /YRUEpngR54BPpORpDUx79RPiMw7Ii5jvGep9E6+yWPzBHGJn8qez0s X-Developer-Key: i=nuno.sa@analog.com; a=ed25519; pk=3NQwYA013OUYZsmDFBf8rmyyr5iQlxV/9H4/Df83o1E= X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: KfGMmDLgxX3TYNl48FsvZ__y9vfJkgCI X-Proofpoint-ORIG-GUID: KfGMmDLgxX3TYNl48FsvZ__y9vfJkgCI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 adultscore=0 bulkscore=0 mlxscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 mlxlogscore=773 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410230090 In order to access the registers of the HW, we need to make sure that the AXI bus clock is enabled. Hence let's increase the number of clocks by one. In order to keep backward compatibility, the new axi clock must be the last phandle in the array. On top of that, it's not an actual parent of the axi-clkgen. Fixes: 0e646c52cf0e ("clk: Add axi-clkgen driver") Signed-off-by: Nuno Sa --- drivers/clk/clk-axi-clkgen.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index bf4d8ddc93aea1d4509a9ae50fa69fdb3f707a29..6403f0e321b4f8fb74852cae2d13507d8cad82df 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -505,6 +506,16 @@ static const struct clk_ops axi_clkgen_ops = { .get_parent = axi_clkgen_get_parent, }; +static void axi_clk_put(void *clk) +{ + clk_put(clk); +} + +static void axi_clk_disable(void *clk) +{ + clk_disable_unprepare(clk); +} + static int axi_clkgen_probe(struct platform_device *pdev) { const struct axi_clkgen_limits *dflt_limits; @@ -512,6 +523,7 @@ static int axi_clkgen_probe(struct platform_device *pdev) struct clk_init_data init; const char *parent_names[2]; const char *clk_name; + struct clk *axi_clk; unsigned int i; int ret; @@ -528,9 +540,30 @@ static int axi_clkgen_probe(struct platform_device *pdev) return PTR_ERR(axi_clkgen->base); init.num_parents = of_clk_get_parent_count(pdev->dev.of_node); - if (init.num_parents < 1 || init.num_parents > 2) + if (init.num_parents < 2 || init.num_parents > 3) return -EINVAL; + /* + * The last clock is the axi bus clock that needs to be enabled so we + * can access the IP core registers. + */ + axi_clk = of_clk_get(pdev->dev.of_node, init.num_parents - 1); + if (IS_ERR(axi_clk)) + return PTR_ERR(axi_clk); + + ret = devm_add_action_or_reset(&pdev->dev, axi_clk_put, axi_clk); + if (ret) + return ret; + + ret = clk_prepare_enable(axi_clk); + if (ret) + return ret; + + ret = devm_add_action_or_reset(&pdev->dev, axi_clk_disable, axi_clk); + if (ret) + return ret; + + init.num_parents -= 1; for (i = 0; i < init.num_parents; i++) { parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i); if (!parent_names[i])