From patchwork Wed Oct 23 16:12:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nemesa Garg X-Patchwork-Id: 13847391 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 304CCCFA451 for ; Wed, 23 Oct 2024 16:11:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5EF6310E821; Wed, 23 Oct 2024 16:11:27 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Wi4OiJzo"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2B11B10E81C; Wed, 23 Oct 2024 16:11:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729699883; x=1761235883; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gnHhq6rJNr1mxIWCk4bWKW7aoRwI1tsZWp4Y4OJwvpM=; b=Wi4OiJzot52plMlmOleMNovqo3cvscrU1bNmNbrW8/EMAgsInm8qTNGa sCoR0BM8BcVx6qE70Eq8WQF+gFTNjMsp7eJNAhCiHxZmy5/diLvCyKqD1 6GwvW0kEFi80PIv0ikvLpoRQA7zXKaZF8OHGMb6qmlTNOiP1N7ngp1G6g kfJGt0R+XRRLZvMtct/FFYoeo1fmKk8glvC0RVIpZ2GOAm3yfSBuSXgIw Z+RQ1ECmyRaKvhTBM5qOYu0W4d9h8MJ5Shmm+uFk4JhcuO93gGjEAtIv3 AscUZJT/ODNib6tt2i0IMwYhKLPKDgwhmALyCWsTKeSbigNP7FRQnSNe/ g==; X-CSE-ConnectionGUID: qlKxI53fRtiabfzM56E2UQ== X-CSE-MsgGUID: Y6j/dQxmQIiA4VU+hB8bhw== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="39847529" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="39847529" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2024 09:11:23 -0700 X-CSE-ConnectionGUID: 0u9YOUNFS4WX4GSKHDOM5w== X-CSE-MsgGUID: viPMFIMTQjamKkltmclclA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,226,1725346800"; d="scan'208";a="79941173" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa007.fm.intel.com with ESMTP; 23 Oct 2024 09:11:21 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 1/5] drm: Introduce sharpness strength property Date: Wed, 23 Oct 2024 21:42:02 +0530 Message-Id: <20241023161206.1113519-2-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241023161206.1113519-1-nemesa.garg@intel.com> References: <20241023161206.1113519-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Introduces the new crtc property "SHARPNESS_STRENGTH" that allows the user to set the intensity so as to get the sharpness effect. The value of this property can be set from 0-255. It is useful in scenario when the output is blurry and user want to sharpen the pixels. User can increase/decrease the sharpness level depending on the content displayed. v2: Rename crtc property variable [Arun] Add modeset detail in uapi doc[Uma] Signed-off-by: Nemesa Garg --- drivers/gpu/drm/drm_atomic_uapi.c | 4 ++++ drivers/gpu/drm/drm_crtc.c | 35 +++++++++++++++++++++++++++++++ include/drm/drm_crtc.h | 17 +++++++++++++++ 3 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 370dc676e3aa..b482bc2b5d0a 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -417,6 +417,8 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, set_out_fence_for_crtc(state->state, crtc, fence_ptr); } else if (property == crtc->scaling_filter_property) { state->scaling_filter = val; + } else if (property == crtc->sharpness_strength_property) { + state->sharpness_strength = val; } else if (crtc->funcs->atomic_set_property) { return crtc->funcs->atomic_set_property(crtc, state, property, val); } else { @@ -454,6 +456,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val = 0; else if (property == crtc->scaling_filter_property) *val = state->scaling_filter; + else if (property == crtc->sharpness_strength_property) + *val = state->sharpness_strength; else if (crtc->funcs->atomic_get_property) return crtc->funcs->atomic_get_property(crtc, state, property, val); else { diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 3488ff067c69..c4a267fa3402 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -229,6 +229,25 @@ struct dma_fence *drm_crtc_create_fence(struct drm_crtc *crtc) * Driver's default scaling filter * Nearest Neighbor: * Nearest Neighbor scaling filter + * SHARPNESS_STRENGTH: + * Atomic property for setting the sharpness strength/intensity by userspace. + * + * The value of this property is set as an integer value ranging + * from 0 - 255 where: + * + * 0 means feature is disabled. + * + * 1 means minimum sharpness. + * + * 255 means maximum sharpness. + * + * User can gradually increase or decrease the sharpness level and can + * set the optimum value depending on content and this value will be + * passed to kernel through the Uapi. + * The setting of this property does not require modeset. + * The sharpness effect takes place post blending on the final composed output. + * If the feature is disabled, the content remains same without any sharpening effect + * and when this feature is applied, it enhances the clarity of the content. */ __printf(6, 0) @@ -939,3 +958,19 @@ int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc, return 0; } EXPORT_SYMBOL(drm_crtc_create_scaling_filter_property); + +int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_property *prop = + drm_property_create_range(dev, 0, "SHARPNESS_STRENGTH", 0, 255); + + if (!prop) + return -ENOMEM; + + crtc->sharpness_strength_property = prop; + drm_object_attach_property(&crtc->base, prop, 0); + + return 0; +} +EXPORT_SYMBOL(drm_crtc_create_sharpness_strength_property); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 8b48a1974da3..37a879350b4e 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -317,6 +317,16 @@ struct drm_crtc_state { */ enum drm_scaling_filter scaling_filter; + /** + * @sharpness_strength + * + * Used by the user to set the sharpness intensity. + * The value ranges from 0-255. + * Any value greater than 0 means enabling the featuring + * along with setting the value for sharpness. + */ + u8 sharpness_strength; + /** * @event: * @@ -1088,6 +1098,12 @@ struct drm_crtc { */ struct drm_property *scaling_filter_property; + /** + * @sharpness_strength_prop: property to apply + * the intensity of the sharpness requested. + */ + struct drm_property *sharpness_strength_property; + /** * @state: * @@ -1324,4 +1340,5 @@ static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev, int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc, unsigned int supported_filters); +int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc); #endif /* __DRM_CRTC_H__ */ From patchwork Wed Oct 23 16:12:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nemesa Garg X-Patchwork-Id: 13847392 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43669CFA44F for ; Wed, 23 Oct 2024 16:11:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A99E710E820; Wed, 23 Oct 2024 16:11:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MWdBzVJ/"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id CA2E510E820; Wed, 23 Oct 2024 16:11:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729699887; x=1761235887; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UL6JpLVHpODv0r1MEL0QFfF7Xmu3TXQ1JZrn3UtSAmg=; b=MWdBzVJ/hmRTR5oUE0Od7eVTfuS0rooBhAT4PIGDzrDLmM/rN3nbuzfe LA5++s9P93jRcLDWu2umygIOai9VMRHlRdPGryQ/FOY9OgK29b0FVnsDA rsREz0xM/SEdMGKa8vxYuI/+av8hTKkRRseITSiU1MYS5zOrHIumf1HmB IrOFmGNVNfg9172on0KSzHxQBgAw0BLCAtCvZ0y+dCcWh0QfaH6QWbIU5 M5M2Isz5SjhhdtZBubSu6SVOrvyPnxPEBFSt+EnejoW0if5BjUfqO8/Wz +rbgP4LCO7uj3x80THbgIbfb9BFqDjmsHCe6UF/BRNmadqcjebNNZYHf7 Q==; X-CSE-ConnectionGUID: bzYS0LzoQf6B7cfviIYDEA== X-CSE-MsgGUID: o3l4UqvRQgaQIcxh+JGrtg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="39847538" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="39847538" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2024 09:11:27 -0700 X-CSE-ConnectionGUID: l1O0nYVjTSWb4ed2oQEgvg== X-CSE-MsgGUID: RlQpJl8ZRiO+SVnVCYJhuA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,226,1725346800"; d="scan'208";a="79941211" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa007.fm.intel.com with ESMTP; 23 Oct 2024 09:11:24 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 2/5] drm/i915/display: Compute the scaler filter coefficients Date: Wed, 23 Oct 2024 21:42:03 +0530 Message-Id: <20241023161206.1113519-3-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241023161206.1113519-1-nemesa.garg@intel.com> References: <20241023161206.1113519-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The sharpness property requires the use of one of the scaler so need to set the sharpness scaler coefficient values. These values are based on experiments and vary for different tap value/win size. These values are normalized by taking the sum of all values and then dividing each value with a sum. v2: Fix ifndef header naming issue reported by kernel test robot v3: Rename file name[Arun] Replace array size number with macro[Arun] v4: Correct the register format[Jani] Add brief comment and expalin about file[Jani] Remove coefficient value from crtc_state[Jani] Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_casf.c | 128 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_casf.h | 16 +++ .../gpu/drm/i915/display/intel_casf_regs.h | 19 +++ drivers/gpu/drm/i915/display/intel_display.c | 3 + .../drm/i915/display/intel_display_types.h | 14 ++ drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/xe/Makefile | 1 + 8 files changed, 184 insertions(+) create mode 100644 drivers/gpu/drm/i915/display/intel_casf.c create mode 100644 drivers/gpu/drm/i915/display/intel_casf.h create mode 100644 drivers/gpu/drm/i915/display/intel_casf_regs.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index e033bcaef4f3..9af345c5fc16 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -283,6 +283,7 @@ i915-y += \ display/intel_pmdemand.o \ display/intel_psr.o \ display/intel_quirks.o \ + display/intel_casf.o \ display/intel_sprite.o \ display/intel_sprite_uapi.o \ display/intel_tc.o \ diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c new file mode 100644 index 000000000000..d186dea75cbf --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_casf.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Intel Corporation + * + */ +#include "i915_reg.h" +#include "intel_de.h" +#include "intel_display_types.h" +#include "intel_casf.h" +#include "intel_casf_regs.h" +#include "skl_scaler.h" + +#define FILTER_COEFF_0_125 125 +#define FILTER_COEFF_0_25 250 +#define FILTER_COEFF_0_5 500 +#define FILTER_COEFF_1_0 1000 +#define FILTER_COEFF_0_0 0 +#define SET_POSITIVE_SIGN(x) ((x) & (~SIGN)) + +/** + * DOC: Content Adaptive Sharpness Filter (CASF) + * + * From LNL onwards the display engine based adaptive + * sharpening filter is supported. This helps in + * improving the image quality. The display hardware + * uses one of the pipe scaler for implementing casf. + * It works on a region of pixels depending on the + * tap size. The coefficients are used to generate an + * alpha value which is used to blend the sharpened image + * to original image. + */ + +const u16 filtercoeff_1[] = {FILTER_COEFF_0_0, FILTER_COEFF_0_0, +FILTER_COEFF_0_5, FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_0, FILTER_COEFF_0_0}; + +const u16 filtercoeff_2[] = {FILTER_COEFF_0_0, FILTER_COEFF_0_25, +FILTER_COEFF_0_5, FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25, FILTER_COEFF_0_0}; + +const u16 filtercoeff_3[] = {FILTER_COEFF_0_125, FILTER_COEFF_0_25, +FILTER_COEFF_0_5, FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25, FILTER_COEFF_0_125}; + +static int casf_coef_tap(int i) +{ + return i % 7; +} + +static u16 casf_coef(struct intel_crtc_state *crtc_state, int t) +{ + struct scaler_filter_coeff value; + u16 coeff; + + value = crtc_state->hw.casf_params.coeff[t]; + coeff = SET_POSITIVE_SIGN(0) | EXPONENT(value.exp) | MANTISSA(value.mantissa); + + return coeff; +} + +void intel_casf_enable(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + int id = crtc_state->scaler_state.scaler_id; + int i; + + intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 0), + PS_COEF_INDEX_AUTO_INC); + + intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 1), + PS_COEF_INDEX_AUTO_INC); + + for (i = 0; i < 17 * 7; i += 2) { + u32 tmp; + int t; + + t = casf_coef_tap(i); + tmp = casf_coef(crtc_state, t); + + t = casf_coef_tap(i + 1); + tmp |= casf_coef(crtc_state, t) << 16; + + intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 0), + tmp); + intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 1), + tmp); + } +} + +static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff, + u16 coefficient) +{ + if (coefficient < 25) { + coeff->mantissa = (coefficient * 2048) / 100; + coeff->exp = 3; + } else if (coefficient < 50) { + coeff->mantissa = (coefficient * 1024) / 100; + coeff->exp = 2; + } else if (coefficient < 100) { + coeff->mantissa = (coefficient * 512) / 100; + coeff->exp = 1; + } else { + coeff->mantissa = (coefficient * 256) / 100; + coeff->exp = 0; + } +} + +void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state) +{ + const u16 *filtercoeff; + u16 filter_coeff[SCALER_FILTER_NUM_TAPS]; + u16 sumcoeff = 0; + u8 i; + + if (crtc_state->hw.casf_params.win_size == 0) + filtercoeff = filtercoeff_1; + else if (crtc_state->hw.casf_params.win_size == 1) + filtercoeff = filtercoeff_2; + else + filtercoeff = filtercoeff_3; + + for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++) + sumcoeff += *(filtercoeff + i); + + for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++) { + filter_coeff[i] = (*(filtercoeff + i) * 100 / sumcoeff); + convert_sharpness_coef_binary(&crtc_state->hw.casf_params.coeff[i], + filter_coeff[i]); + } +} diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h new file mode 100644 index 000000000000..8e0b67a2fd99 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_casf.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_CASF_H__ +#define __INTEL_CASF_H__ + +#include + +struct intel_crtc_state; + +void intel_casf_enable(struct intel_crtc_state *crtc_state); +void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state); + +#endif /* __INTEL_CASF_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h new file mode 100644 index 000000000000..0b3fcdb22c0c --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_CASF_REGS_H__ +#define __INTEL_CASF_REGS_H__ + +#include "intel_display_reg_defs.h" + +/* Scaler Coefficient structure */ +#define SIGN REG_BIT(15) +#define EXPONENT_MASK REG_GENMASK(13, 12) +#define EXPONENT(x) REG_FIELD_PREP(EXPONENT_MASK, (x)) +#define MANTISSA_MASK REG_GENMASK(11, 3) +#define MANTISSA(x) REG_FIELD_PREP(MANTISSA_MASK, (x)) + +#endif /* __INTEL_CASF_REGS__ */ + diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ef1436146325..777677a1d342 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -111,6 +111,7 @@ #include "intel_psr.h" #include "intel_psr_regs.h" #include "intel_sdvo.h" +#include "intel_casf.h" #include "intel_snps_phy.h" #include "intel_tc.h" #include "intel_tdf.h" @@ -6187,6 +6188,8 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state) if (ret) return ret; + intel_casf_scaler_compute_config(new_crtc_state); + /* * On some platforms the number of active planes affects * the planes' minimum cdclk calculation. Add such planes diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 2bb1fa64da2f..d765d7ec2d66 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -909,6 +909,19 @@ struct intel_csc_matrix { u16 postoff[3]; }; +struct scaler_filter_coeff { + u16 sign; + u16 exp; + u16 mantissa; +}; + +struct intel_casf { +#define SCALER_FILTER_NUM_TAPS 7 + struct scaler_filter_coeff coeff[SCALER_FILTER_NUM_TAPS]; + u8 win_size; + bool need_scaler; +}; + void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val); typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val); @@ -949,6 +962,7 @@ struct intel_crtc_state { struct drm_property_blob *degamma_lut, *gamma_lut, *ctm; struct drm_display_mode mode, pipe_mode, adjusted_mode; enum drm_scaling_filter scaling_filter; + struct intel_casf casf_params; } hw; /* actual state of LUTs */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 405f409e9761..34febbe358b3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2250,6 +2250,8 @@ #define PS_VERT_INT_INVERT_FIELD REG_BIT(20) #define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */ #define PS_PWRUP_PROGRESS REG_BIT(17) +#define PS_BYPASS_ARMING REG_BIT(10) +#define PS_DB_STALL REG_BIT(9) #define PS_V_FILTER_BYPASS REG_BIT(8) #define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */ #define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */ diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index da80c29aa363..f2a03f40e6ab 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -257,6 +257,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-display/intel_psr.o \ i915-display/intel_qp_tables.o \ i915-display/intel_quirks.o \ + i915-display/intel_casf.o \ i915-display/intel_snps_phy.o \ i915-display/intel_tc.o \ i915-display/intel_vblank.o \ From patchwork Wed Oct 23 16:12:04 2024 Content-Type: text/plain; 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d="scan'208";a="79941423" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa007.fm.intel.com with ESMTP; 23 Oct 2024 09:11:50 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 3/5] drm/i915/display: Enable the second scaler for sharpness Date: Wed, 23 Oct 2024 21:42:04 +0530 Message-Id: <20241023161206.1113519-4-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241023161206.1113519-1-nemesa.garg@intel.com> References: <20241023161206.1113519-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" As only second scaler can be used for sharpness check if it is available and also check if panel fitting is also not enabled, then set the sharpness. Panel fitting will have the preference over sharpness property. v2: Add the panel fitting check before enabling sharpness v3: Reframe commit message[Arun] v4: Replace string based comparison with plane_state[Jani] v5: Rebase Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_casf.c | 10 +++ drivers/gpu/drm/i915/display/intel_casf.h | 1 + drivers/gpu/drm/i915/display/intel_display.c | 10 ++- .../drm/i915/display/intel_modeset_verify.c | 2 + drivers/gpu/drm/i915/display/intel_panel.c | 7 ++ drivers/gpu/drm/i915/display/skl_scaler.c | 79 ++++++++++++++++--- drivers/gpu/drm/i915/display/skl_scaler.h | 1 + 7 files changed, 96 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c index d186dea75cbf..fce0b997ae62 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.c +++ b/drivers/gpu/drm/i915/display/intel_casf.c @@ -83,6 +83,16 @@ void intel_casf_enable(struct intel_crtc_state *crtc_state) intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 1), tmp); } + + skl_scaler_setup_casf(crtc_state); +} + +int intel_casf_compute_config(struct intel_crtc_state *crtc_state) +{ + if (!crtc_state->pch_pfit.enabled) + crtc_state->hw.casf_params.need_scaler = true; + + return 0; } static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff, diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h index 8e0b67a2fd99..568e0f8083eb 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.h +++ b/drivers/gpu/drm/i915/display/intel_casf.h @@ -12,5 +12,6 @@ struct intel_crtc_state; void intel_casf_enable(struct intel_crtc_state *crtc_state); void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state); +int intel_casf_compute_config(struct intel_crtc_state *crtc_state); #endif /* __INTEL_CASF_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 777677a1d342..1f4a1e9df1d3 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2136,7 +2136,7 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); if (crtc_state->pch_pfit.enabled || - crtc_state->pch_pfit.force_thru) + crtc_state->pch_pfit.force_thru || crtc_state->hw.casf_params.need_scaler) set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); drm_for_each_encoder_mask(encoder, &dev_priv->drm, @@ -2385,7 +2385,7 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) * PF-ID we'll need to adjust the pixel_rate here. */ - if (!crtc_state->pch_pfit.enabled) + if (!crtc_state->pch_pfit.enabled || crtc_state->hw.casf_params.need_scaler) return pixel_rate; drm_rect_init(&src, 0, 0, @@ -4575,7 +4575,8 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, if (DISPLAY_VER(dev_priv) >= 9) { if (intel_crtc_needs_modeset(crtc_state) || - intel_crtc_needs_fastset(crtc_state)) { + intel_crtc_needs_fastset(crtc_state) || + crtc_state->hw.casf_params.need_scaler) { ret = skl_update_scaler_crtc(crtc_state); if (ret) return ret; @@ -5763,6 +5764,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(cmrr.enable); } + if (pipe_config->uapi.sharpness_strength > 0) + PIPE_CONF_CHECK_BOOL(hw.casf_params.need_scaler); + #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I #undef PIPE_CONF_CHECK_LLI diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index 3491db5cad31..1cb5da45a1d2 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -177,9 +177,11 @@ verify_crtc_state(struct intel_atomic_state *state, crtc->base.name); hw_crtc_state->hw.enable = sw_crtc_state->hw.enable; + hw_crtc_state->hw.casf_params.need_scaler = sw_crtc_state->hw.casf_params.need_scaler; intel_crtc_get_pipe_config(hw_crtc_state); + hw_crtc_state->scaler_state.scaler_id = sw_crtc_state->scaler_state.scaler_id; /* we keep both pipes enabled on 830 */ if (IS_I830(i915) && hw_crtc_state->hw.active) hw_crtc_state->hw.active = sw_crtc_state->hw.active; diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 71454ddef20f..6ed13245bdc8 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -389,6 +389,9 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state, { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); int pipe_src_h = drm_rect_height(&crtc_state->pipe_src); int x, y, width, height; @@ -399,6 +402,9 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state, crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420) return 0; + if (old_crtc_state->hw.casf_params.need_scaler) + return -EINVAL; + switch (conn_state->scaling_mode) { case DRM_MODE_SCALE_CENTER: width = pipe_src_w; @@ -451,6 +457,7 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state, drm_rect_init(&crtc_state->pch_pfit.dst, x, y, width, height); + crtc_state->pch_pfit.enabled = true; return 0; diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index baa601d27815..1cd2f7d6c080 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -97,7 +97,12 @@ static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited) #define MTL_MAX_DST_H 8192 #define SKL_MIN_YUV_420_SRC_W 16 #define SKL_MIN_YUV_420_SRC_H 16 - +#define SCALER_FILTER_SELECT \ + (PS_FILTER_PROGRAMMED | \ + PS_Y_VERT_FILTER_SELECT(1) | \ + PS_Y_HORZ_FILTER_SELECT(0) | \ + PS_UV_VERT_FILTER_SELECT(1) | \ + PS_UV_HORZ_FILTER_SELECT(0)) static int skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, unsigned int scaler_user, int *scaler_id, @@ -253,7 +258,8 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) drm_rect_width(&crtc_state->pipe_src), drm_rect_height(&crtc_state->pipe_src), width, height, NULL, 0, - crtc_state->pch_pfit.enabled); + crtc_state->pch_pfit.enabled || + crtc_state->hw.casf_params.need_scaler); } /** @@ -353,9 +359,10 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat int num_scalers_need, struct intel_crtc *intel_crtc, const char *name, int idx, struct intel_plane_state *plane_state, - int *scaler_id) + int *scaler_id, bool casf_scaler) { struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); + struct intel_crtc_state *crtc_state = to_intel_crtc_state(intel_crtc->base.state); int j; u32 mode; @@ -365,6 +372,11 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat if (scaler_state->scalers[j].in_use) continue; + if (!plane_state) { + if (casf_scaler && j != 1) + continue; + } + *scaler_id = j; scaler_state->scalers[*scaler_id].in_use = 1; break; @@ -375,6 +387,10 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat "Cannot find scaler for %s:%d\n", name, idx)) return -EINVAL; + if (crtc_state->hw.casf_params.need_scaler) { + mode = SKL_PS_SCALER_MODE_HQ; + } + /* set scaler mode */ if (plane_state && plane_state->hw.fb && plane_state->hw.fb->format->is_yuv && @@ -557,7 +573,6 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, /* plane scaler case: assign as a plane scaler */ /* find the plane that set the bit as scaler_user */ plane = drm_state->planes[i].ptr; - /* * to enable/disable hq mode, add planes that are using scaler * into this transaction @@ -598,7 +613,8 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need, intel_crtc, name, idx, - plane_state, scaler_id); + plane_state, scaler_id, + crtc_state->hw.casf_params.need_scaler); if (ret < 0) return ret; } @@ -705,6 +721,44 @@ static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe } } +void skl_scaler_setup_casf(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_display *display = to_intel_display(crtc); + struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + struct intel_crtc_scaler_state *scaler_state = + &crtc_state->scaler_state; + struct drm_rect src, dest; + int id, width, height; + int x, y; + enum pipe pipe = crtc->pipe; + u32 ps_ctrl; + + width = adjusted_mode->crtc_hdisplay; + height = adjusted_mode->crtc_vdisplay; + + x = y = 0; + drm_rect_init(&dest, x, y, width, height); + + width = drm_rect_width(&dest); + height = drm_rect_height(&dest); + id = scaler_state->scaler_id; + + drm_rect_init(&src, 0, 0, + drm_rect_width(&crtc_state->pipe_src) << 16, + drm_rect_height(&crtc_state->pipe_src) << 16); + + ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode | + PS_BYPASS_ARMING | PS_DB_STALL | SCALER_FILTER_SELECT; + + intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl); + intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id), + PS_WIN_XPOS(x) | PS_WIN_YPOS(y)); + intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id), + PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height)); +} + void skl_pfit_enable(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -875,16 +929,19 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state) continue; id = i; - crtc_state->pch_pfit.enabled = true; + + if (!crtc_state->hw.casf_params.need_scaler) + crtc_state->pch_pfit.enabled = true; pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); - drm_rect_init(&crtc_state->pch_pfit.dst, - REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), - REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), - REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), - REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); + if (!crtc_state->hw.casf_params.need_scaler) + drm_rect_init(&crtc_state->pch_pfit.dst, + REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), + REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), + REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), + REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); scaler_state->scalers[i].in_use = true; break; diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h index 63f93ca03c89..fbca98a79ad5 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.h +++ b/drivers/gpu/drm/i915/display/skl_scaler.h @@ -33,5 +33,6 @@ void skl_detach_scalers(const struct intel_crtc_state *crtc_state); void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state); void skl_scaler_get_config(struct intel_crtc_state *crtc_state); +void skl_scaler_setup_casf(struct intel_crtc_state *crtc_state); #endif From patchwork Wed Oct 23 16:12:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nemesa Garg X-Patchwork-Id: 13847394 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52097CFA450 for ; Wed, 23 Oct 2024 16:11:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B942610E827; Wed, 23 Oct 2024 16:11:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="lG86Iq0X"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id A05E810E826; Wed, 23 Oct 2024 16:11:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729699916; x=1761235916; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XXo1Y34iqC1IU0a8Fq8aJGYi3MrIzx2IdaGMRvPo56Y=; b=lG86Iq0X1xOR9QvR7VL3EZiTNjAwC3wOmwCMxa1uqVbUusgcfE61x57h R983Vx+l3lssTndMjx3bt1KPbBasYlP4mZTZaghjSXqHNNoconu1JIyiF sIPgOzK/Dg2C3WPhuhlYdm01hYycvr/xhZb10sa/zCZWsK1OHZbR4erRw /s7jhUSXBHKP7BSCFuIb27vmFyGDvt3EYsGIKUvyRzuqc0kY3zVd9uJSy /QcHBECKL75s97/0bku+ImsSzRQdvmIG1lpenCn0SRcJxoBvNusaqUPGH /YHE5oViWCR3dPnDEJQm9xScYf1i+nnfWAJWGEQiJ/4MBm8erqzvL/17X Q==; X-CSE-ConnectionGUID: zpLfNkRoSHKB9iqp9H1Agg== X-CSE-MsgGUID: 0qYDE2wJRqSenFR/rEVfNw== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="39847632" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="39847632" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2024 09:11:56 -0700 X-CSE-ConnectionGUID: qoDUmg6PSkW2maBxD3/OfA== X-CSE-MsgGUID: LE+CnLabR1y30Xno4GANkQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,226,1725346800"; d="scan'208";a="79941431" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa007.fm.intel.com with ESMTP; 23 Oct 2024 09:11:54 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 4/5] drm/i915/display: Add registers and compute the strength Date: Wed, 23 Oct 2024 21:42:05 +0530 Message-Id: <20241023161206.1113519-5-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241023161206.1113519-1-nemesa.garg@intel.com> References: <20241023161206.1113519-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add new registers and related bits. Compute the strength value and tap value based on display mode. v2: Replace i915/dev_priv with display[Jani] v3: Create separate file for defining register[Jani] Add display->drm in debug prints[Jani] v4: Rebase Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_casf.c | 112 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_casf.h | 7 ++ .../gpu/drm/i915/display/intel_casf_regs.h | 17 +++ drivers/gpu/drm/i915/display/intel_display.c | 7 +- 4 files changed, 142 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c index fce0b997ae62..cac1b9e7c92b 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.c +++ b/drivers/gpu/drm/i915/display/intel_casf.c @@ -17,6 +17,9 @@ #define FILTER_COEFF_0_0 0 #define SET_POSITIVE_SIGN(x) ((x) & (~SIGN)) +#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080) +#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160) + /** * DOC: Content Adaptive Sharpness Filter (CASF) * @@ -55,12 +58,90 @@ static u16 casf_coef(struct intel_crtc_state *crtc_state, int t) return coeff; } +/* Default LUT values to be loaded one time. */ +static const u16 lut_data[] = { + 4095, 2047, 1364, 1022, 816, 678, 579, + 504, 444, 397, 357, 323, 293, 268, 244, 224, + 204, 187, 170, 154, 139, 125, 111, 98, 85, + 73, 60, 48, 36, 24, 12, 0 +}; + +void intel_filter_lut_load(struct intel_crtc *crtc, + const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + int i; + + intel_de_write(display, SHRPLUT_INDEX(display, cpu_transcoder), INDEX_AUTO_INCR | INDEX_VALUE(0)); + + for (i = 0; i < ARRAY_SIZE(lut_data); i++) + intel_de_write(display, SHRPLUT_DATA(display, cpu_transcoder), lut_data[i]); +} + +static void intel_casf_size_compute(struct intel_crtc_state *crtc_state) +{ + const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode; + u16 total_pixels = mode->hdisplay * mode->vdisplay; + + if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER) + crtc_state->hw.casf_params.win_size = 0; + else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER) + crtc_state->hw.casf_params.win_size = 1; + else + crtc_state->hw.casf_params.win_size = 2; +} + +bool intel_casf_strength_changed(struct intel_atomic_state *state) +{ + int i; + struct intel_crtc_state *old_crtc_state, *new_crtc_state; + struct intel_crtc *crtc; + + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + if (new_crtc_state->uapi.sharpness_strength != + old_crtc_state->uapi.sharpness_strength) + return true; + } + + return false; +} + void intel_casf_enable(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); int id = crtc_state->scaler_state.scaler_id; int i; + u32 sharpness_ctl; + u8 val; + + if (crtc_state->uapi.sharpness_strength == 0 || + crtc_state->pch_pfit.enabled) { + intel_casf_disable(crtc_state); + + return; + } + + /* + * HW takes a value in form (1.0 + strength) in 4.4 fixed format. + * Strength is from 0.0-14.9375 ie from 0-239. + * User can give value from 0-255 but is clamped to 239. + * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125. + * 6.3125 in 4.4 format is 01100101 which is equal to 101. + * Also 85 + 16 = 101. + */ + val = min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10; + + drm_dbg(display->drm, "Filter strength value: %d\n", val); + + sharpness_ctl = FILTER_EN | FILTER_STRENGTH(val) | + FILTER_SIZE(crtc_state->hw.casf_params.win_size); + + intel_de_write(display, SHARPNESS_CTL(display, cpu_transcoder), + sharpness_ctl); intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 0), PS_COEF_INDEX_AUTO_INC); @@ -89,9 +170,23 @@ void intel_casf_enable(struct intel_crtc_state *crtc_state) int intel_casf_compute_config(struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); + + if (crtc_state->uapi.sharpness_strength == 0) { + crtc_state->hw.casf_params.need_scaler = false; + return 0; + } + + if (crtc_state->pch_pfit.enabled) + return -EINVAL; + if (!crtc_state->pch_pfit.enabled) crtc_state->hw.casf_params.need_scaler = true; + intel_casf_size_compute(crtc_state); + drm_dbg(display->drm, "Tap Size: %d\n", + crtc_state->hw.casf_params.win_size); + return 0; } @@ -136,3 +231,20 @@ void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state) filter_coeff[i]); } } + +void intel_casf_disable(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + intel_de_write(display, SHARPNESS_CTL(display, cpu_transcoder), 0); + drm_dbg(display->drm, "Filter strength value: %d\n", 0); +} + +bool intel_casf_compute(struct intel_crtc_state *crtc_state) +{ + if (!(FILTER_EN & 1) && crtc_state->uapi.sharpness_strength != 0) + return true; + + return false; +} diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h index 568e0f8083eb..05b0abddd917 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.h +++ b/drivers/gpu/drm/i915/display/intel_casf.h @@ -9,9 +9,16 @@ #include struct intel_crtc_state; +struct intel_atomic_state; +struct intel_crtc; void intel_casf_enable(struct intel_crtc_state *crtc_state); void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state); int intel_casf_compute_config(struct intel_crtc_state *crtc_state); +void intel_filter_lut_load(struct intel_crtc *crtc, + const struct intel_crtc_state *crtc_state); +bool intel_casf_strength_changed(struct intel_atomic_state *state); +void intel_casf_disable(struct intel_crtc_state *crtc_state); +bool intel_casf_compute(struct intel_crtc_state *crtc_state); #endif /* __INTEL_CASF_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h index 0b3fcdb22c0c..fb92978e386a 100644 --- a/drivers/gpu/drm/i915/display/intel_casf_regs.h +++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h @@ -15,5 +15,22 @@ #define MANTISSA_MASK REG_GENMASK(11, 3) #define MANTISSA(x) REG_FIELD_PREP(MANTISSA_MASK, (x)) +#define _SHARPNESS_CTL_A 0x682B0 +#define SHARPNESS_CTL(display, trans) _MMIO_PIPE2(display, trans, _SHARPNESS_CTL_A) +#define FILTER_EN REG_BIT(31) +#define FILTER_STRENGTH_MASK REG_GENMASK(15, 8) +#define FILTER_STRENGTH(x) REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x)) +#define FILTER_SIZE_MASK REG_GENMASK(1, 0) +#define FILTER_SIZE(x) REG_FIELD_PREP(FILTER_SIZE_MASK, (x)) + +#define _SHRPLUT_DATA_A 0x682B8 +#define SHRPLUT_DATA(display, trans) _MMIO_PIPE2(display, trans, _SHRPLUT_DATA_A) + +#define _SHRPLUT_INDEX_A 0x682B4 +#define SHRPLUT_INDEX(display, trans) _MMIO_PIPE2(display, trans, _SHRPLUT_INDEX_A) +#define INDEX_AUTO_INCR REG_BIT(10) +#define INDEX_VALUE_MASK REG_GENMASK(4, 0) +#define INDEX_VALUE(x) REG_FIELD_PREP(INDEX_VALUE_MASK, (x)) + #endif /* __INTEL_CASF_REGS__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1f4a1e9df1d3..275853067378 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6192,7 +6192,12 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state) if (ret) return ret; - intel_casf_scaler_compute_config(new_crtc_state); + if (intel_casf_compute(new_crtc_state)) { + intel_casf_scaler_compute_config(new_crtc_state); + ret = intel_casf_compute_config(new_crtc_state); + if (ret) + return ret; + } /* * On some platforms the number of active planes affects From patchwork Wed Oct 23 16:12:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nemesa Garg X-Patchwork-Id: 13847395 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9019DCFA44F for ; Wed, 23 Oct 2024 16:12:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E94A910E81C; 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X-CSE-ConnectionGUID: U8qQHIyiRia/4E6O143qQw== X-CSE-MsgGUID: AJ7JdIz3SzK7vpxtEPyikQ== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="39847640" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="39847640" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2024 09:11:59 -0700 X-CSE-ConnectionGUID: JoMfPW9pRdGej2hAA+W3eQ== X-CSE-MsgGUID: M/B/AoLIT1OO/kNXfLefrw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,226,1725346800"; d="scan'208";a="79941440" Received: from nemesa.iind.intel.com ([10.190.239.22]) by fmviesa007.fm.intel.com with ESMTP; 23 Oct 2024 09:11:57 -0700 From: Nemesa Garg To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Nemesa Garg Subject: [PATCH 5/5] drm/i915/display: Load the lut values and enable sharpness Date: Wed, 23 Oct 2024 21:42:06 +0530 Message-Id: <20241023161206.1113519-6-nemesa.garg@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241023161206.1113519-1-nemesa.garg@intel.com> References: <20241023161206.1113519-1-nemesa.garg@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Load the lut values during pipe enable. v2: Add the display version check Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_crtc.c | 3 +++ drivers/gpu/drm/i915/display/intel_display.c | 6 ++++++ .../gpu/drm/i915/display/intel_display_types.h | 2 ++ drivers/gpu/drm/i915/display/skl_scaler.c | 16 +++++++++++++++- 4 files changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 3c9168a57f38..140006a7c55d 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -388,6 +388,9 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe); + if (DISPLAY_VER(dev_priv) >= 20) + drm_crtc_create_sharpness_strength_property(&crtc->base); + return 0; fail: diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 275853067378..fc233330c2a9 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1880,6 +1880,9 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_crtc_wait_for_next_vblank(wa_crtc); } } + + if (new_crtc_state->hw.casf_params.strength_changed) + intel_filter_lut_load(crtc, new_crtc_state); } void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) @@ -7197,6 +7200,9 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, intel_vrr_set_transcoder_timings(new_crtc_state); } + if (intel_casf_strength_changed(state)) + intel_casf_enable(new_crtc_state); + intel_fbc_update(state, crtc); drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF)); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index d765d7ec2d66..d7a529c92cb0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -920,6 +920,8 @@ struct intel_casf { struct scaler_filter_coeff coeff[SCALER_FILTER_NUM_TAPS]; u8 win_size; bool need_scaler; + bool strength_changed; + u8 strength; }; void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val); diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index 1cd2f7d6c080..4ee2f6e67d97 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -7,6 +7,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_fb.h" +#include "intel_casf_regs.h" #include "skl_scaler.h" #include "skl_universal_plane.h" @@ -914,15 +915,17 @@ void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state) void skl_scaler_get_config(struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; int id = -1; int i; /* find scaler attached to this pipe */ for (i = 0; i < crtc->num_scalers; i++) { - u32 ctl, pos, size; + u32 ctl, pos, size, sharp; ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE)) @@ -930,6 +933,17 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state) id = i; + if (DISPLAY_VER(dev_priv) >= 20) { + sharp = intel_de_read(dev_priv, SHARPNESS_CTL(display, cpu_transcoder)); + if (sharp & FILTER_EN) { + crtc_state->hw.casf_params.strength = + REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) - 16; + crtc_state->hw.casf_params.need_scaler = true; + crtc_state->hw.casf_params.win_size = + REG_FIELD_GET(FILTER_SIZE_MASK, sharp); + } + } + if (!crtc_state->hw.casf_params.need_scaler) crtc_state->pch_pfit.enabled = true;