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Adds bootph to mcu_timer0 instead of mcu_timer1. Signed-off-by: Manorit Chawdhry --- arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi index cba8d0e64f2e6336cfb6f356c879aecc6d49880a..9899da73a905a517a8561f09515aa8303f8d6b5d 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi @@ -172,13 +172,13 @@ mcu_timer0: timer@40400000 { assigned-clocks = <&k3_clks 35 2>; assigned-clock-parents = <&k3_clks 35 3>; power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-all; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; }; mcu_timer1: timer@40410000 { - bootph-all; compatible = "ti,am654-timer"; reg = <0x00 0x40410000 0x00 0x400>; interrupts = ; From patchwork Thu Oct 24 05:20:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manorit Chawdhry X-Patchwork-Id: 13848310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 16086D0BB60 for ; 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Thu, 24 Oct 2024 00:21:17 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 24 Oct 2024 00:21:17 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49O5L4lA090467; Thu, 24 Oct 2024 00:21:13 -0500 From: Manorit Chawdhry Date: Thu, 24 Oct 2024 10:50:59 +0530 Subject: [PATCH v6 02/12] arm64: dts: ti: k3-j784s4-j742s2-mcu-wakeup: Remove parent nodes bootph-* MIME-Version: 1.0 Message-ID: <20241024-b4-upstream-bootph-all-v6-2-2af90e3a4fe7@ti.com> References: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> In-Reply-To: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adding bootph properties on leaf nodes imply that they are applicable to the parent nodes as well. Bootloaders can derive the parent nodes when bootph is available in the leaf nodes. Remove the bootph-* properties from parent nodes as they are redundant. Reviewed-by: Aniket Limaye Signed-off-by: Manorit Chawdhry --- Notes: It wasn't existing previously in U-boot but the following patch fixes it [0] [0]: https://lore.kernel.org/u-boot/20231217163627.2339802-10-sjg@chromium.org/ R-by picked up in v5 ( Aniket ) arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi index 9899da73a905a517a8561f09515aa8303f8d6b5d..46bc2a3e4aea68415f7bb54f401b81e81d45134f 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi @@ -7,7 +7,6 @@ &cbass_mcu_wakeup { sms: system-controller@44083000 { - bootph-all; compatible = "ti,k2g-sci"; ti,host-id = <12>; @@ -39,7 +38,6 @@ k3_reset: reset-controller { }; wkup_conf: bus@43000000 { - bootph-all; compatible = "simple-bus"; #address-cells = <1>; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The following nodes are being used in the bootloaders. Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to - secure_proxy_sa3/secure_proxy_main mboxes for communication with System Controller - wkup_vtm for enabling Adaptive voltage scaling(AVS) support Signed-off-by: Manorit Chawdhry --- arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi index 46bc2a3e4aea68415f7bb54f401b81e81d45134f..9638130caece5cafa0a944c3d44471be7cb2bdbd 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi @@ -57,6 +57,8 @@ secure_proxy_sa3: mailbox@43600000 { reg = <0x00 0x43600000 0x00 0x10000>, <0x00 0x44880000 0x00 0x20000>, <0x00 0x44860000 0x00 0x20000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -512,6 +514,8 @@ secure_proxy_mcu: mailbox@2a480000 { reg = <0x00 0x2a480000 0x00 0x80000>, <0x00 0x2a380000 0x00 0x80000>, <0x00 0x2a400000 0x00 0x80000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -629,6 +633,7 @@ wkup_vtm0: temperature-sensor@42040000 { <0x00 0x42050000 0x00 0x350>; power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; + bootph-pre-ram; }; tscadc0: tscadc@40200000 { From patchwork Thu Oct 24 05:21:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manorit Chawdhry X-Patchwork-Id: 13848312 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC5C3D0BB48 for ; Thu, 24 Oct 2024 05:29:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; 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Thu, 24 Oct 2024 00:21:26 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49O5L4lC090467; Thu, 24 Oct 2024 00:21:22 -0500 From: Manorit Chawdhry Date: Thu, 24 Oct 2024 10:51:01 +0530 Subject: [PATCH v6 04/12] arm64: dts: ti: k3-j721s2: Add bootph-* properties MIME-Version: 1.0 Message-ID: <20241024-b4-upstream-bootph-all-v6-4-2af90e3a4fe7@ti.com> References: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> In-Reply-To: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729747264; l=4130; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=2BDHihROVg8eztkArItUGNLASEwXMBXatnAsVyQgE+A=; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to - System controller nodes that allow controlling power domain, clocks, etc. - secure_proxy_sa3/secure_proxy_main mboxes for communication with System Controller - mcu_ringacc/mcu_udmap for DMA to SMS - chipid for detection soc information. - mcu_timer0 for bootloader tick-timer. - wkup_vtm for enabling Adaptive voltage scaling(AVS) support Reviewed-by: Andrew Davis Signed-off-by: Manorit Chawdhry --- Notes: R-by picked up in v3 ( Andrew ) arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 9ed6949b40e9dfafdaf6861944b0b128b053a44f..9889144d665a832e5346e13daa7887c9c968fbcd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -816,6 +816,7 @@ secure_proxy_main: mailbox@32c00000 { <0x00 0x32800000 0x00 0x100000>; interrupt-names = "rx_011"; interrupts = ; + bootph-all; }; hwspinlock: spinlock@30e00000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 9d96b19d0e7cf5bb86b50c73f4ec1a6b43b8bf83..c36888c455316774a07d69326262465ac958a6fc 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -21,16 +21,19 @@ sms: system-controller@44083000 { k3_pds: power-controller { compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; + bootph-all; }; k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; + bootph-all; }; k3_reset: reset-controller { compatible = "ti,sci-reset"; #reset-cells = <2>; + bootph-all; }; }; @@ -43,6 +46,7 @@ wkup_conf: bus@43000000 { chipid: chipid@14 { compatible = "ti,am654-chipid"; reg = <0x14 0x4>; + bootph-all; }; }; @@ -53,6 +57,8 @@ secure_proxy_sa3: mailbox@43600000 { reg = <0x00 0x43600000 0x00 0x10000>, <0x00 0x44880000 0x00 0x20000>, <0x00 0x44860000 0x00 0x20000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -167,6 +173,7 @@ mcu_timer0: timer@40400000 { assigned-clocks = <&k3_clks 35 1>; assigned-clock-parents = <&k3_clks 35 2>; power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-pre-ram; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; @@ -361,6 +368,7 @@ wkup_i2c0: i2c@42120000 { clocks = <&k3_clks 223 1>; clock-names = "fck"; power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; + bootph-all; status = "disabled"; }; @@ -469,6 +477,7 @@ mcu_ringacc: ringacc@2b800000 { <0x0 0x2a500000 0x0 0x40000>, <0x0 0x28440000 0x0 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + bootph-all; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; ti,sci = <&sms>; @@ -488,6 +497,7 @@ mcu_udmap: dma-controller@285c0000 { "tchan", "rchan", "rflow"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; + bootph-all; ti,sci = <&sms>; ti,sci-dev-id = <273>; @@ -507,6 +517,8 @@ secure_proxy_mcu: mailbox@2a480000 { reg = <0x00 0x2a480000 0x00 0x80000>, <0x00 0x2a380000 0x00 0x80000>, <0x00 0x2a400000 0x00 0x80000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -667,6 +679,7 @@ wkup_vtm0: temperature-sensor@42040000 { <0x00 0x42050000 0x0 0x350>; power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; + bootph-pre-ram; }; mcu_r5fss0: r5fss@41000000 { From patchwork Thu Oct 24 05:21:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manorit Chawdhry X-Patchwork-Id: 13848313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD290D0BB48 for ; Thu, 24 Oct 2024 05:30:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; 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Thu, 24 Oct 2024 00:21:30 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49O5L4lD090467; Thu, 24 Oct 2024 00:21:27 -0500 From: Manorit Chawdhry Date: Thu, 24 Oct 2024 10:51:02 +0530 Subject: [PATCH v6 05/12] arm64: dts: ti: k3-j721e: Add bootph-* properties MIME-Version: 1.0 Message-ID: <20241024-b4-upstream-bootph-all-v6-5-2af90e3a4fe7@ti.com> References: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> In-Reply-To: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729747264; l=4152; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=3YPkWzNT9VXGLmRRyS4UdXPVZFEI1W9pLphosiqRsPQ=; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to - System controller nodes that allow controlling power domain, clocks, etc. - secure_proxy_sa3/secure_proxy_main mboxes for communication with System Controller - mcu_ringacc/mcu_udmap for DMA to SMS - chipid for detection soc information. - mcu_timer0 for bootloader tick-timer. - hbmc_mux for enabling Hyperflash support - ESM nodes for enabling ESM support. - wkup_vtm for enabling Adaptive voltage scaling(AVS) support Reviewed-by: Neha Malcom Francis Signed-off-by: Manorit Chawdhry --- Notes: R-by picked up in v5 ( Neha ) arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 10 ++++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 0da785be80ff476a89ff5108db566c0f7099a6dc..af3d730154ac542d1b6cb53da602660dafa605cd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -226,6 +226,7 @@ secure_proxy_main: mailbox@32c00000 { <0x00 0x32800000 0x00 0x100000>; interrupt-names = "rx_011"; interrupts = ; + bootph-all; }; smmu0: iommu@36600000 { @@ -2853,6 +2854,7 @@ main_spi7: spi@2170000 { main_esm: esm@700000 { compatible = "ti,j721e-esm"; reg = <0x0 0x700000 0x0 0x1000>; + bootph-pre-ram; ti,esm-pins = <344>, <345>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 3731ffb4a5c9630c06c5dd5f954af8c68704df2c..cf5fb1160ada5e8cf815f119a76f5793851883cc 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -21,16 +21,19 @@ dmsc: system-controller@44083000 { k3_pds: power-controller { compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; + bootph-all; }; k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; + bootph-all; }; k3_reset: reset-controller { compatible = "ti,sci-reset"; #reset-cells = <2>; + bootph-all; }; }; @@ -61,6 +64,7 @@ wkup_conf: bus@43000000 { chipid: chipid@14 { compatible = "ti,am654-chipid"; reg = <0x14 0x4>; + bootph-all; }; }; @@ -112,6 +116,7 @@ mcu_timer0: timer@40400000 { assigned-clocks = <&k3_clks 35 1>; assigned-clock-parents = <&k3_clks 35 2>; power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-pre-ram; ti,timer-pwm; /* Non-MPU Firmware usage */ status = "reserved"; @@ -362,6 +367,7 @@ hbmc_mux: mux-controller@47000004 { reg = <0x00 0x47000004 0x00 0x4>; #mux-control-cells = <1>; mux-reg-masks = <0x0 0x2>; /* HBMC select */ + bootph-all; }; hbmc: hyperbus@47034000 { @@ -470,6 +476,7 @@ mcu_ringacc: ringacc@2b800000 { <0x0 0x2a500000 0x0 0x40000>, <0x0 0x28440000 0x0 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + bootph-all; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; @@ -489,6 +496,7 @@ mcu_udmap: dma-controller@285c0000 { "tchan", "rchan", "rflow"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; + bootph-all; ti,sci = <&dmsc>; ti,sci-dev-id = <236>; @@ -509,6 +517,7 @@ secure_proxy_mcu: mailbox@2a480000 { reg = <0x0 0x2a480000 0x0 0x80000>, <0x0 0x2a380000 0x0 0x80000>, <0x0 0x2a400000 0x0 0x80000>; + bootph-pre-ram; /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -687,6 +696,7 @@ wkup_vtm0: temperature-sensor@42040000 { <0x00 0x43000300 0x00 0x10>; power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; + bootph-pre-ram; }; mcu_esm: esm@40800000 { From patchwork Thu Oct 24 05:21:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manorit Chawdhry X-Patchwork-Id: 13848314 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D72B9D0BB5E for ; Thu, 24 Oct 2024 05:32:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to - System controller nodes that allow controlling power domain, clocks, etc. - secure_proxy_sa3/secure_proxy_main mboxes for communication with System Controller - mcu_ringacc/mcu_udmap for DMA to SMS - chipid for detection soc information. - mcu_timer0 for bootloader tick-timer. - hbmc_mux for enabling Hyperflash support - ESM nodes for enabling ESM support. - wkup_vtm for enabling Adaptive voltage scaling(AVS) support Reviewed-by: Aniket Limaye Signed-off-by: Manorit Chawdhry --- Notes: R-by picked up in v5 ( Aniket ) arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 9386bf3ef9f684474c817e22f0bbf657185b192d..ac9c0a9394615c23ca153c8ae9996e009ec2cf38 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -136,6 +136,7 @@ secure_proxy_main: mailbox@32c00000 { <0x00 0x32800000 0x00 0x100000>; interrupt-names = "rx_011"; interrupts = ; + bootph-all; }; hwspinlock: spinlock@30e00000 { @@ -1527,6 +1528,7 @@ main_r5fss0_core1: r5f@5d00000 { main_esm: esm@700000 { compatible = "ti,j721e-esm"; reg = <0x0 0x700000 0x0 0x1000>; + bootph-pre-ram; ti,esm-pins = <656>, <657>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 5097d192c2b208ffa702a38631d096995b4b53d5..7e9ad230193771e051ec0902cd826440280546b0 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -21,16 +21,19 @@ dmsc: system-controller@44083000 { k3_pds: power-controller { compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; + bootph-all; }; k3_clks: clock-controller { compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; + bootph-all; }; k3_reset: reset-controller { compatible = "ti,sci-reset"; #reset-cells = <2>; + bootph-all; }; }; @@ -44,6 +47,7 @@ mcu_timer0: timer@40400000 { assigned-clocks = <&k3_clks 35 1>; assigned-clock-parents = <&k3_clks 35 2>; power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + bootph-pre-ram; ti,timer-pwm; }; @@ -191,6 +195,7 @@ wkup_conf: bus@43000000 { chipid: chipid@14 { compatible = "ti,am654-chipid"; reg = <0x14 0x4>; + bootph-all; }; }; @@ -344,6 +349,7 @@ mcu_ringacc: ringacc@2b800000 { <0x00 0x28440000 0x00 0x40000>; reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + bootph-all; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; @@ -363,6 +369,7 @@ mcu_udmap: dma-controller@285c0000 { "tchan", "rchan", "rflow"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; + bootph-all; ti,sci = <&dmsc>; ti,sci-dev-id = <236>; @@ -383,6 +390,8 @@ secure_proxy_mcu: mailbox@2a480000 { reg = <0x0 0x2a480000 0x0 0x80000>, <0x0 0x2a380000 0x0 0x80000>, <0x0 0x2a400000 0x0 0x80000>; + bootph-pre-ram; + /* * Marked Disabled: * Node is incomplete as it is meant for bootloaders and @@ -534,6 +543,7 @@ hbmc_mux: mux-controller@47000004 { reg = <0x00 0x47000004 0x00 0x4>; #mux-control-cells = <1>; mux-reg-masks = <0x0 0x2>; /* HBMC select */ + bootph-all; }; hbmc: hyperbus@47034000 { @@ -652,6 +662,7 @@ wkup_vtm0: temperature-sensor@42040000 { <0x00 0x42050000 0x00 0x350>; power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; + bootph-pre-ram; }; mcu_esm: esm@40800000 { From patchwork Thu Oct 24 05:21:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manorit Chawdhry X-Patchwork-Id: 13848320 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4084ED0BB5E for ; Thu, 24 Oct 2024 05:34:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; 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Thu, 24 Oct 2024 00:21:39 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49O5L4lF090467; Thu, 24 Oct 2024 00:21:35 -0500 From: Manorit Chawdhry Date: Thu, 24 Oct 2024 10:51:04 +0530 Subject: [PATCH v6 07/12] arm64: dts: ti: k3-j784s4-j742s2-evm-common: Remove parent nodes bootph-* MIME-Version: 1.0 Message-ID: <20241024-b4-upstream-bootph-all-v6-7-2af90e3a4fe7@ti.com> References: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> In-Reply-To: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729747264; l=2443; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=9iGWhy2bJ0M0XUaJJe5iD1g+ItxzMy6MMTq9OU0rsI4=; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adding bootph properties on leaf nodes imply that they are applicable to the parent nodes as well. Bootloaders can derive the parent nodes when bootph is available in the leaf nodes. Remove the bootph-* properties from parent nodes as they are redundant. Reviewed-by: Aniket Limaye Signed-off-by: Manorit Chawdhry --- Notes: R-by picked up in v5 ( Aniket ) arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index 98453171a1790cd605d25ad939f556127519524a..b2e2b9f507a9828d49b1eb94d098b2c6682cef0e 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -305,7 +305,6 @@ &wkup_gpio0 { }; &main_pmx0 { - bootph-all; main_cpsw2g_default_pins: main-cpsw2g-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ @@ -432,7 +431,6 @@ J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */ }; &wkup_pmx2 { - bootph-all; wkup_uart0_pins_default: wkup-uart0-default-pins { bootph-all; pinctrl-single,pins = < @@ -548,7 +546,6 @@ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) }; &wkup_pmx0 { - bootph-all; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { bootph-all; pinctrl-single,pins = < @@ -568,7 +565,6 @@ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ }; &wkup_pmx1 { - bootph-all; mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { bootph-all; pinctrl-single,pins = < @@ -740,18 +736,15 @@ &ufs_wrapper { }; &fss { - bootph-all; status = "okay"; }; &ospi0 { - bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; flash@0 { - bootph-all; compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -808,13 +801,11 @@ partition@3fc0000 { }; &ospi1 { - bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; flash@0 { - bootph-all; compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; From patchwork Thu Oct 24 05:21:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manorit Chawdhry X-Patchwork-Id: 13848321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17ECCD0BB5E for ; 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Thu, 24 Oct 2024 00:21:43 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 24 Oct 2024 00:21:43 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49O5L4lG090467; Thu, 24 Oct 2024 00:21:40 -0500 From: Manorit Chawdhry Date: Thu, 24 Oct 2024 10:51:05 +0530 Subject: [PATCH v6 08/12] arm64: dts: ti: k3-j721s2-evm*: Add bootph-* properties MIME-Version: 1.0 Message-ID: <20241024-b4-upstream-bootph-all-v6-8-2af90e3a4fe7@ti.com> References: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> In-Reply-To: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; 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Following adds bootph-* to: - pmic regulator for enabling AVS Support - main_uart8, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc0, mmc1, usb0, ospi0, ospi1 for enabling various bootmodes. Reviewed-by: Andrew Davis Signed-off-by: Manorit Chawdhry --- Notes: R-by picked up in v3 ( Andrew ) arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 3 +++ 2 files changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index c5a0b7cbb14f8866bbb06e337f1242455aeeea4e..e2fc1288ed07664591c2d645dc949f182dd71df7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -138,6 +138,7 @@ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */ J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ >; + bootph-all; }; main_i2c3_pins_default: main-i2c3-default-pins { @@ -165,6 +166,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ >; + bootph-all; }; vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { @@ -177,6 +179,7 @@ main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ >; + bootph-all; }; main_mcan3_pins_default: main-mcan3-default-pins { @@ -200,6 +203,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; + bootph-all; }; mcu_uart0_pins_default: mcu-uart0-default-pins { @@ -209,6 +213,7 @@ J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ >; + bootph-all; }; mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -301,6 +306,7 @@ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ >; + bootph-all; }; }; @@ -316,12 +322,14 @@ &wkup_uart0 { status = "reserved"; pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; + bootph-all; }; &mcu_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; + bootph-all; }; &main_uart8 { @@ -330,6 +338,7 @@ &main_uart8 { pinctrl-0 = <&main_uart8_pins_default>; /* Shared with TFA on this platform */ power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; + bootph-all; }; &main_i2c0 { @@ -383,6 +392,7 @@ &main_sdhci0 { /* eMMC */ status = "okay"; non-removable; + bootph-all; ti,driver-strength-ohm = <50>; disable-wp; }; @@ -395,6 +405,7 @@ &main_sdhci1 { disable-wp; vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv>; + bootph-all; }; &mcu_cpsw { @@ -444,6 +455,7 @@ &usbss0 { status = "okay"; pinctrl-0 = <&main_usbss0_pins_default>; pinctrl-names = "default"; + bootph-all; ti,vbus-divider; ti,usb2-only; }; @@ -451,6 +463,7 @@ &usbss0 { &usb0 { dr_mode = "otg"; maximum-speed = "high-speed"; + bootph-all; }; &ospi1 { @@ -464,6 +477,7 @@ flash@0 { spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; + bootph-all; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index 89252e4a5f1bc2472b2464faf2fb727c9eedab4e..b3a0385ed3d86cc6e63fe88a554364325fd7967c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -170,6 +170,7 @@ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ >; + bootph-all; }; }; @@ -188,6 +189,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ >; + bootph-pre-ram; }; }; @@ -440,6 +442,7 @@ flash@0 { spi-tx-bus-width = <8>; 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Thu, 24 Oct 2024 00:21:44 -0500 From: Manorit Chawdhry Date: Thu, 24 Oct 2024 10:51:06 +0530 Subject: [PATCH v6 09/12] arm64: dts: ti: k3-am68-sk*: Add bootph-* properties MIME-Version: 1.0 Message-ID: <20241024-b4-upstream-bootph-all-v6-9-2af90e3a4fe7@ti.com> References: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> In-Reply-To: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729747264; l=3955; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=DIvjMla05HLiI1/XLCDUNxF0kf/gSNM5WoACMqNNNxE=; b=156ZjYMbc3oyJNYzbnhEhndJie2LnzTfXGQcJXxKDohtChyrzYci09QT2ywgMoIADjTn+RXmn 6spVbFMro3dD8xac/3GmHBAQlolt5S9quLjlM66V5CyRJBVd65tvHZA X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241023_222151_527994_C4130A52 X-CRM114-Status: GOOD ( 11.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to: - main_uart8, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc1, ospi0 for enabling various bootmodes. - eeprom for board detection Reviewed-by: Udit Kumar Signed-off-by: Manorit Chawdhry --- Notes: R-by picked up in v4 ( Udit ) arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 5 +++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index d5ceab79536ca45fb1421a2a2e133db6a458b518..11522b36e0cece248571b27819c8a87e0ffe06e2 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -184,6 +184,7 @@ main_uart8_pins_default: main-uart8-default-pins { J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ >; + bootph-all; }; main_i2c0_pins_default: main-i2c0-default-pins { @@ -211,6 +212,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ >; + bootph-all; }; vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { @@ -313,6 +315,7 @@ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ >; + bootph-all; }; mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -372,6 +375,7 @@ mcu_uart0_pins_default: mcu-uart0-default-pins { J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ >; + bootph-all; }; mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { @@ -413,6 +417,7 @@ &wkup_uart0 { status = "reserved"; pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; + bootph-all; }; &wkup_i2c0 { @@ -495,6 +500,7 @@ &mcu_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; + bootph-all; }; &main_uart8 { @@ -503,6 +509,7 @@ &main_uart8 { pinctrl-0 = <&main_uart8_pins_default>; /* Shared with TFA on this platform */ power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; + bootph-all; }; &main_i2c0 { @@ -597,6 +604,7 @@ &main_sdhci1 { disable-wp; vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv>; + bootph-all; }; &mcu_cpsw { diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi index 5bc0d2fb4b8f3969d6f372a374be91e5b5cbd821..4ca2d4e2fb9b063086b4bec2a184e01dfab11f24 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -156,6 +156,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ >; + bootph-all; }; }; @@ -169,6 +170,7 @@ eeprom@51 { /* AT24C512C-MAHM-T */ compatible = "atmel,24c512"; reg = <0x51>; + bootph-all; }; }; @@ -190,7 +192,6 @@ flash@0 { cdns,read-delay = <4>; partitions { - bootph-all; compatible = "fixed-partitions"; #address-cells = <1>; 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Thu, 24 Oct 2024 00:21:52 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49O5L4lI090467; Thu, 24 Oct 2024 00:21:48 -0500 From: Manorit Chawdhry Date: Thu, 24 Oct 2024 10:51:07 +0530 Subject: [PATCH v6 10/12] arm64: dts: ti: k3-j721e-evm*: Add bootph-* properties MIME-Version: 1.0 Message-ID: <20241024-b4-upstream-bootph-all-v6-10-2af90e3a4fe7@ti.com> References: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> In-Reply-To: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729747264; l=6136; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=YkoYsB9z0kCB3W0pfDiofnKczI4z+KXwjVWI+BKRyS8=; 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Following adds bootph-* to: - main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc0, mmc1, usb0, ospi0, ospi1, hbmc for enabling various bootmodes. Reviewed-by: Neha Malcom Francis Signed-off-by: Manorit Chawdhry --- Notes: R-by picked up in v5 ( Neha ) arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 5 +++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 8230d53cd69609d44b4a832cf214afdc2ee90e02..4c1e02a4e7a25c8fc6f55f06fe27d0f2b41483d7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -193,6 +193,7 @@ J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; + bootph-all; }; main_uart1_pins_default: main-uart1-default-pins { @@ -234,6 +235,7 @@ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ >; + bootph-all; }; vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { @@ -247,6 +249,7 @@ main_usbss0_pins_default: main-usbss0-default-pins { J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; + bootph-all; }; main_usbss1_pins_default: main-usbss1-default-pins { @@ -342,6 +345,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ >; + bootph-all; }; mcu_uart0_pins_default: mcu-uart0-default-pins { @@ -351,6 +355,7 @@ J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ >; + bootph-all; }; sw11_button_pins_default: sw11-button-default-pins { @@ -370,6 +375,7 @@ J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ >; + bootph-all; }; mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -435,12 +441,14 @@ &wkup_uart0 { status = "reserved"; pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; + bootph-all; }; &mcu_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; + bootph-all; }; &main_uart0 { @@ -449,6 +457,7 @@ &main_uart0 { pinctrl-0 = <&main_uart0_pins_default>; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; + bootph-all; }; &main_uart1 { @@ -487,6 +496,7 @@ &main_sdhci0 { /* eMMC */ status = "okay"; non-removable; + bootph-all; ti,driver-strength-ohm = <50>; disable-wp; }; @@ -498,12 +508,14 @@ &main_sdhci1 { vqmmc-supply = <&vdd_sd_dv_alt>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; + bootph-all; ti,driver-strength-ohm = <50>; disable-wp; }; &usb_serdes_mux { idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ + bootph-all; }; &serdes_ln_ctrl { @@ -513,6 +525,7 @@ &serdes_ln_ctrl { , , , , , ; + bootph-all; }; &serdes_wiz3 { @@ -533,6 +546,7 @@ serdes3_usb_link: phy@0 { &usbss0 { pinctrl-names = "default"; pinctrl-0 = <&main_usbss0_pins_default>; + bootph-all; ti,vbus-divider; }; @@ -541,6 +555,7 @@ &usb0 { maximum-speed = "super-speed"; phys = <&serdes3_usb_link>; phy-names = "cdns3,usb3-phy"; + bootph-all; }; &usbss1 { @@ -613,6 +628,7 @@ partition@800000 { partition@3fe0000 { label = "qspi.phypattern"; reg = <0x3fe0000 0x20000>; + bootph-all; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index cef47c67493fcc24f56f3cbd409a0268aaa5176f..0722f6361cc8b0bfd2c666cc5a9f1b70e3070859 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -151,6 +151,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; + bootph-all; }; pmic_irq_pins_default: pmic-irq-default-pins { @@ -173,6 +174,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ >; + bootph-all; }; mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { @@ -192,6 +194,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */ >; + bootph-all; }; }; @@ -422,6 +425,7 @@ partition@800000 { partition@3fe0000 { label = "ospi.phypattern"; reg = <0x3fe0000 0x20000>; + bootph-all; }; }; }; @@ -440,6 +444,7 @@ &hbmc { flash@0,0 { compatible = "cypress,hyperflash", "cfi-flash"; reg = <0x00 0x00 0x4000000>; + bootph-all; partitions { compatible = "fixed-partitions"; From patchwork Thu Oct 24 05:21:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manorit Chawdhry X-Patchwork-Id: 13848324 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2288D0BB5E for ; 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Thu, 24 Oct 2024 00:21:57 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 24 Oct 2024 00:21:56 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49O5L4lJ090467; Thu, 24 Oct 2024 00:21:53 -0500 From: Manorit Chawdhry Date: Thu, 24 Oct 2024 10:51:08 +0530 Subject: [PATCH v6 11/12] arm64: dts: ti: k3-j721e-sk*: Add bootph-* properties MIME-Version: 1.0 Message-ID: <20241024-b4-upstream-bootph-all-v6-11-2af90e3a4fe7@ti.com> References: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> In-Reply-To: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to: - main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc1, usb0, usb1, ospi0 for enabling various bootmodes. Reviewed-by: Neha Malcom Francis Signed-off-by: Manorit Chawdhry --- Notes: R-by picked up in v5 ( Neha ) arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 6285e8d94ddeb75003468176bfbad7150c77facf..69b3d1ed8a21c26916721be6d10af1ba63ded156 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -346,6 +346,7 @@ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ >; + bootph-all; }; main_uart0_pins_default: main-uart0-default-pins { @@ -355,6 +356,7 @@ J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; + bootph-all; }; main_uart1_pins_default: main-uart1-default-pins { @@ -390,12 +392,14 @@ main_usbss0_pins_default: main-usbss0-default-pins { J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; + bootph-all; }; main_usbss1_pins_default: main-usbss1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; + bootph-all; }; main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { @@ -594,6 +598,7 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ >; + bootph-all; }; vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins { @@ -622,6 +627,7 @@ J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ >; + bootph-all; }; wkup_i2c0_pins_default: wkup-i2c0-default-pins { @@ -629,6 +635,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; + bootph-all; }; mcu_mcan0_pins_default: mcu-mcan0-default-pins { @@ -657,6 +664,7 @@ &wkup_uart0 { status = "reserved"; pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; + bootph-all; }; &wkup_i2c0 { @@ -821,6 +829,7 @@ &mcu_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; + bootph-all; }; &main_uart0 { @@ -829,6 +838,7 @@ &main_uart0 { pinctrl-0 = <&main_uart0_pins_default>; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; + bootph-all; }; &main_uart1 { @@ -844,6 +854,7 @@ &main_sdhci1 { vqmmc-supply = <&vdd_sd_dv_alt>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; + bootph-all; ti,driver-strength-ohm = <50>; disable-wp; }; @@ -908,6 +919,7 @@ partition@800000 { partition@3fc0000 { label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; + bootph-all; }; }; }; @@ -1003,6 +1015,7 @@ &wkup_gpio0 { &usb_serdes_mux { idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ + bootph-all; }; &serdes_ln_ctrl { @@ -1012,6 +1025,7 @@ &serdes_ln_ctrl { , , , , , ; + bootph-all; }; &serdes_wiz3 { @@ -1050,6 +1064,7 @@ &mhdp { &usbss0 { pinctrl-names = "default"; pinctrl-0 = <&main_usbss0_pins_default>; + bootph-all; ti,vbus-divider; }; @@ -1058,6 +1073,7 @@ &usb0 { maximum-speed = "super-speed"; phys = <&serdes3_usb_link>; phy-names = "cdns3,usb3-phy"; + bootph-all; }; &serdes2 { @@ -1073,6 +1089,7 @@ serdes2_usb_link: phy@1 { &usbss1 { pinctrl-names = "default"; pinctrl-0 = <&main_usbss1_pins_default>; + bootph-all; ti,vbus-divider; }; @@ -1081,6 +1098,7 @@ &usb1 { maximum-speed = "super-speed"; phys = <&serdes2_usb_link>; phy-names = "cdns3,usb3-phy"; + bootph-all; }; &mcu_cpsw { From patchwork Thu Oct 24 05:21:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manorit Chawdhry X-Patchwork-Id: 13848328 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8D2DD0BB45 for ; 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Thu, 24 Oct 2024 00:22:01 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 24 Oct 2024 00:22:01 -0500 Received: from [127.0.1.1] (uda0497581.dhcp.ti.com [10.24.68.185]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49O5L4lK090467; Thu, 24 Oct 2024 00:21:57 -0500 From: Manorit Chawdhry Date: Thu, 24 Oct 2024 10:51:09 +0530 Subject: [PATCH v6 12/12] arm64: dts: ti: k3-j7200-evm*: Add bootph-* properties MIME-Version: 1.0 Message-ID: <20241024-b4-upstream-bootph-all-v6-12-2af90e3a4fe7@ti.com> References: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> In-Reply-To: <20241024-b4-upstream-bootph-all-v6-0-2af90e3a4fe7@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Neha Malcom Francis , Aniket Limaye , Udit Kumar , Beleswar Padhi , Siddharth Vadapalli , Andrew Davis , Manorit Chawdhry X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1729747264; l=5351; i=m-chawdhry@ti.com; s=20231127; h=from:subject:message-id; bh=46PvWcO1Y+g4FOBZ8tCATYLmz+1G6stPwizRvVFOk0w=; b=CVBTPby0nz1ySFr7EBcoQzKOm1TgU/bQUmapYyjxDelG5ShEod8v/kLaV078b45+r4EB0eZVM v3is5falx6xDCgPhzfvWwNinxKF5PzcC1IQ/sOZaR0b5/S/V4tpryni X-Developer-Key: i=m-chawdhry@ti.com; a=ed25519; pk=fsr6Tm39TvsTgfyfFQLk+nnqIz2sBA1PthfqqfiiYSs= X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241023_222204_596467_E7997405 X-CRM114-Status: UNSURE ( 9.86 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds bootph-* properties to the leaf nodes to enable bootloaders to utilise them. Following adds bootph-* to: - pmic regulator for enabling AVS Support - main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces - mmc0, mmc1, usb0, ospi0, hbmc for enabling various bootmodes. Reviewed-by: Aniket Limaye Signed-off-by: Manorit Chawdhry --- Notes: R-by picked up in v5 ( Aniket ) arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 13 +++++++++++++ arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 6 ++++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 6593c5da82c06463c2d7cbbe01d6fa481be1aa1a..d03690b8d65230d22b3630770a6bc819409837c1 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -129,6 +129,7 @@ J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ >; + bootph-all; }; wkup_uart0_pins_default: wkup-uart0-default-pins { @@ -136,6 +137,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ >; + bootph-all; }; mcu_cpsw_pins_default: mcu-cpsw-default-pins { @@ -204,6 +206,7 @@ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ >; + bootph-all; }; main_uart1_pins_default: main-uart1-default-pins { @@ -238,6 +241,7 @@ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ >; + bootph-all; }; vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { @@ -259,6 +263,7 @@ main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ >; + bootph-all; }; }; @@ -267,12 +272,14 @@ &wkup_uart0 { status = "reserved"; pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; + bootph-all; }; &mcu_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; + bootph-all; }; &main_uart0 { @@ -281,6 +288,7 @@ &main_uart0 { power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + bootph-all; }; &main_uart1 { @@ -379,6 +387,7 @@ &main_sdhci0 { /* eMMC */ status = "okay"; non-removable; + bootph-all; ti,driver-strength-ohm = <50>; disable-wp; }; @@ -390,6 +399,7 @@ &main_sdhci1 { pinctrl-names = "default"; vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv>; + bootph-all; ti,driver-strength-ohm = <50>; disable-wp; }; @@ -401,11 +411,13 @@ &serdes_ln_ctrl { &usb_serdes_mux { idle-states = <1>; /* USB0 to SERDES lane 3 */ + bootph-all; }; &usbss0 { pinctrl-names = "default"; pinctrl-0 = <&main_usbss0_pins_default>; + bootph-all; ti,vbus-divider; ti,usb2-only; }; @@ -413,6 +425,7 @@ &usbss0 { &usb0 { dr_mode = "otg"; maximum-speed = "high-speed"; + bootph-all; }; &tscadc0 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index e78b4622a7d1ff320259b17850e8f1735508f7dd..291ab9bb414d7883f102101035b19fd324767306 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -121,6 +121,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ >; + bootph-all; }; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { @@ -137,6 +138,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ >; + bootph-all; }; }; @@ -146,6 +148,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins { J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ >; + bootph-all; }; }; @@ -186,6 +189,7 @@ &hbmc { flash@0,0 { compatible = "cypress,hyperflash", "cfi-flash"; reg = <0x00 0x00 0x4000000>; + bootph-all; partitions { compatible = "fixed-partitions"; @@ -347,6 +351,7 @@ bucka1: buck1 { regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + bootph-all; }; bucka2: buck2 { @@ -520,6 +525,7 @@ partition@800000 { partition@3fc0000 { label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; + bootph-all; }; }; };