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Thu, 24 Oct 2024 17:53:38 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Oct 2024 10:53:35 -0700 From: Taniya Das Date: Thu, 24 Oct 2024 23:22:55 +0530 Subject: [PATCH v2] arm64: defconfig: Enable sa8775p clock controllers MIME-Version: 1.0 Message-ID: <20241024-defconfig_sa8775p_clock_controllers-v2-1-a9e1cdaed785@quicinc.com> X-B4-Tracking: v=1; b=H4sIAHaJGmcC/5WQS26EMBBEr4K8Tkf+ADYoinKPaIRM0x6s4Rebo EQj7h4PZJFtllWLek91Z5GCp8jq7M4CbT76eUpBPmUMeztdCXyXMpNc5oJLCR05nCfnr020Rut iaXCY8dakcg3zMFCIoDjnVOS8KHnL0tISyPmvg/J+OXOgj88EW8+StTYS4DyOfq2zUrXKOa66S lgyzujCkdG5Rm2ELaRw2mBHQj+mR4rRHpZ19nJKCgG/ajCOsOUQKNLUwWJX7CnCVgCH3FZO6A5 Lo+xbUkE/4XMSeGUPwd7HdQ7fxyubOAz/dcAmQAC2qqparnKJ5i+CXfZ9/wG/b2XZeQEAAA== X-Change-ID: 20241022-defconfig_sa8775p_clock_controllers-3000e540560b To: Bjorn Andersson , Catalin Marinas , Will Deacon , CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: a7vv6e-6NNWOfdrg8zTm4haucIyWtrq8 X-Proofpoint-GUID: a7vv6e-6NNWOfdrg8zTm4haucIyWtrq8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 impostorscore=0 spamscore=0 phishscore=0 mlxlogscore=750 lowpriorityscore=0 clxscore=1015 malwarescore=0 bulkscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410240147 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241024_105347_013427_06C88241 X-CRM114-Status: GOOD ( 10.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable the SA8775P video, camera and display clock controllers to enable the video, camera and display functionalities on Qualcomm QCS9100 ride and ride rev3 boards. Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov --- Changes in v2: - Update the board names for QCS9100 [Dmitry]. - Link to v1: https://lore.kernel.org/r/20241022-defconfig_sa8775p_clock_controllers-v1-1-cb399b0342c8@quicinc.com --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) --- base-commit: 63b3ff03d91ae8f875fe8747c781a521f78cde17 change-id: 20241022-defconfig_sa8775p_clock_controllers-3000e540560b prerequisite-message-id: <20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com> prerequisite-patch-id: c405247d3558175ea16e723e36ccba87b51da3e6 prerequisite-patch-id: 2f421e48713add52f17b6e0a95a1e4cb410322e0 prerequisite-patch-id: 037cc7f8c1c9f690bea1976550616e661f48c53a prerequisite-patch-id: 930db8201718c0a66286d85418c7bac1719a76d1 prerequisite-patch-id: 79dc8594844768685144c302eaf404b0d6cb7ebd prerequisite-patch-id: 836d46d2d006bdaae12b8a8aaed2eb786fd636ce prerequisite-patch-id: 096e89f063b35a70bbd8f92c4eb5a32c850bd927 prerequisite-patch-id: 5a49926d1dfada78038f963d5de23a558d9dd19b Best regards, diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 36b33b9f17042128f5bef96f58667b5807b712c2..6197934b38e08b7294ec897e451af6e96fd63cda 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1324,10 +1324,12 @@ CONFIG_QCM_GCC_2290=y CONFIG_QCM_DISPCC_2290=m CONFIG_QCS_GCC_404=y CONFIG_SC_CAMCC_7280=m +CONFIG_SA_CAMCC_8775P=m CONFIG_QDU_GCC_1000=y CONFIG_SC_CAMCC_8280XP=m CONFIG_SC_DISPCC_7280=m CONFIG_SC_DISPCC_8280XP=m +CONFIG_SA_DISPCC_8775P=m CONFIG_SA_GCC_8775P=y CONFIG_SA_GPUCC_8775P=m CONFIG_SC_GCC_7180=y @@ -1366,6 +1368,7 @@ CONFIG_SM_GPUCC_8550=m CONFIG_SM_GPUCC_8650=m CONFIG_SM_TCSRCC_8550=y CONFIG_SM_TCSRCC_8650=y +CONFIG_SA_VIDEOCC_8775P=m CONFIG_SM_VIDEOCC_8250=y CONFIG_QCOM_HFPLL=y CONFIG_CLK_GFM_LPASS_SM8250=m