From patchwork Fri Oct 25 02:45:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13849968 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 112EF12B143; Fri, 25 Oct 2024 03:09:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729825790; cv=none; b=VfwPjsCoK0vdyGVeT2ADnTtCn2Zb4KTMZgMS53c4HqT8QBm/auNQBZsOmhsyxARBxXthFCvJJJeBJacG3hr3agzf9nzTauU6WBHhvBqKspRUvdBSbfZv6TjxWsaqsxWBBajBVGrUHlLwT7bYYbYzqn/BtNpSmxeKD0Qi6zTyD7w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729825790; c=relaxed/simple; bh=0uEOgm/q4BVQvk6tMSgZrhriA8QBf3GJlomzmqz2PLU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=IXhrsJt/gCKu7xSSa96EGRlYNmvfl/rDshK+6HbZ4aUSL5yrLvNlZlm0tfgq6UARiR5TfrS5jpakDd9Id8cRv5OtVFlCdl5aLIIGwZWKGUAXSCo6KkiczG6XZ7yckVqe/yO2277y6WP0tsY2Bup7SlBjbsKaUzDRwWPo16118FU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Cux4YTx2; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Cux4YTx2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729825788; x=1761361788; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=0uEOgm/q4BVQvk6tMSgZrhriA8QBf3GJlomzmqz2PLU=; b=Cux4YTx2oeIV4CPNxw9cng/6FccMPNBk1FhaW+R5olKSmrZN1ufS8ENs Pj+AgfzLCzZx5uuhrwy7H62UhEuam1lJ7b/8cBFWgWYPNl3dHeijS0Xr8 Mx4gfwlfw2oytGMpRp+Q59FEslHx3+62VFJprRiM8HVFU87hcqy/UnS3I SbQQO+BzOCbz+XPD0ze3B+FhOCucLTP1+5XwPUd3yQe3UXiqJCL9w/y8f 3aqKDbjX4XGkrMixQI/oMzZzWMPwdFjR+D4R2puksJxyS5d1WtwxWQ4t2 v8z2b8/694CqIACfhEGfYC2UK/rRlCaPgqwh1sEfWsypcuuaE3TyoaQmJ w==; X-CSE-ConnectionGUID: d5LRwnVqR0CvypabEu5L3Q== X-CSE-MsgGUID: pxf7dSFqQY6f5jOTU5Y6Og== X-IronPort-AV: E=McAfee;i="6700,10204,11235"; a="29385518" X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="29385518" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:09:48 -0700 X-CSE-ConnectionGUID: cZWjJfduT8qZtsLzYsBT8w== X-CSE-MsgGUID: 8TqFGheqQbOTRxTug3zgmw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="80449138" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:09:44 -0700 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v3 01/10] x86/mce/dev-mcelog: Use xchg() to get and clear the flags Date: Fri, 25 Oct 2024 10:45:53 +0800 Message-Id: <20241025024602.24318-2-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241025024602.24318-1-qiuxu.zhuo@intel.com> References: <20241016123036.21366-1-qiuxu.zhuo@intel.com> <20241025024602.24318-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Using xchg() to atomically get and clear the MCE log buffer flags, streamlines the code and reduces the text size by 20 bytes. $ size dev-mcelog.o.* text data bss dec hex filename 3013 360 160 3533 dcd dev-mcelog.o.old 2993 360 160 3513 db9 dev-mcelog.o.new No functional changes intended. Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo --- Changes in v3: - Collect "Reviewed-by:" from Nikolay & Sohil. Changes in v2: - Collect "Reviewed-by:" from Tony. arch/x86/kernel/cpu/mce/dev-mcelog.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/dev-mcelog.c b/arch/x86/kernel/cpu/mce/dev-mcelog.c index af44fd5dbd7c..8d023239ce18 100644 --- a/arch/x86/kernel/cpu/mce/dev-mcelog.c +++ b/arch/x86/kernel/cpu/mce/dev-mcelog.c @@ -264,15 +264,8 @@ static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, return put_user(sizeof(struct mce), p); case MCE_GET_LOG_LEN: return put_user(mcelog->len, p); - case MCE_GETCLEAR_FLAGS: { - unsigned flags; - - do { - flags = mcelog->flags; - } while (cmpxchg(&mcelog->flags, flags, 0) != flags); - - return put_user(flags, p); - } + case MCE_GETCLEAR_FLAGS: + return put_user(xchg(&mcelog->flags, 0), p); default: return -ENOTTY; } From patchwork Fri Oct 25 02:45:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13849969 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60FB018BBA3; Fri, 25 Oct 2024 03:10:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729825818; cv=none; b=EdV4ss0TUrmFzAS4UO/ky9TbiZtcZpxtdU2+kVtW6PbCzaj7OZEhLpD3nDfE85pN2HlH20/1G2knSitCSKDfYANt2DkLzrkcrqtbgQD/1qFbxtWFgMg7gihi+i5CzCfJyqjK2W9tpDDRANCNLw+GukpJfum9ZU07BJpkjVRnHdI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729825818; c=relaxed/simple; bh=/U8+xKHaCdvK3vMq4oDINx7J29Rm28/W5b4lYt8uNgs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=QGvLawT9phIGuKHMzpSyVlNiVy7toPIFs//aVZzBoGuLXoAcjOfFh0CHoJFdRUlMwvrcOzY43dVe9erO8Ha9EiAEnxUgSSRban/eVjhVSe45wkgiN4A0K651WUpRj9XdEfewv0nQP3g+Fgh/KiStChaUHuSqGmz5zdpOZu8XjVs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=h2/NUHer; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="h2/NUHer" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729825816; x=1761361816; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=/U8+xKHaCdvK3vMq4oDINx7J29Rm28/W5b4lYt8uNgs=; b=h2/NUHercz0J/OGfA2OJlRy+rcHvKfOMmN9TYIHXIoDvx1lWEOyzVu2B UPZBn7Wyu3K07RqOKyd79JjxtXno6RaafmGWHVZ4zDgHjLEdeDpvWraVg 9lClEuKpaQP3msqB9SiDn2loK8vNDHWtZthge6qbCVXyGFl8H4xQzcVoL B/COTNJ7b36I+F/IbbcPzlQhYfpOygxPZZqmbo0dktw2hBBiwiRK9LmLL ptawqoyx/pa7ud28mXoi944nNyjixscAjK97qR/pUBmToGpENJaveomU9 0anN1OU3AR0iQhkYlLZG+RnL8QR+c9YoY42gFXgBlywvU8NeEp3B63rGP g==; X-CSE-ConnectionGUID: OQMJ9K/2SW2czhnXga4qrg== X-CSE-MsgGUID: HDx+IxNwSzesleS2wL/hLA== X-IronPort-AV: E=McAfee;i="6700,10204,11235"; a="29385546" X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="29385546" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:10:16 -0700 X-CSE-ConnectionGUID: +5DF61YLQSqMz1RYJrcG7Q== X-CSE-MsgGUID: bpdk+8vvT+eHZrwL3TiPtA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="80449506" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:10:14 -0700 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v3 02/10] x86/mce/intel: Use MCG_BANKCNT_MASK instead of 0xff Date: Fri, 25 Oct 2024 10:45:54 +0800 Message-Id: <20241025024602.24318-3-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241025024602.24318-1-qiuxu.zhuo@intel.com> References: <20241016123036.21366-1-qiuxu.zhuo@intel.com> <20241025024602.24318-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Use the predefined MCG_BANKCNT_MASK macro instead of the hardcoded 0xff to mask the bank number bits. No functional changes intended. Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo --- Changes in v3: - Collect "Reviewed-by:" from Nikolay & Sohil. Changes in v2: - Collect "Reviewed-by:" from Tony. arch/x86/kernel/cpu/mce/intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index f6103e6bf69a..b3cd2c61b11d 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -94,7 +94,7 @@ static int cmci_supported(int *banks) if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) return 0; rdmsrl(MSR_IA32_MCG_CAP, cap); - *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff); + *banks = min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK); return !!(cap & MCG_CMCI_P); } From patchwork Fri Oct 25 02:45:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13849970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DDD618A6AA; Fri, 25 Oct 2024 03:10:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729825839; cv=none; b=Nj8LK8Woz4eY9IcbDltd2/Bedn9WpvnEhIUg5BufS4tudVvLp3KcUC456aHhGOLTaSkZsYi+xUyx2t2b4KkHrvedfgitZ+oIkQUUs3lcPb7pZil0bytpmaT2gKn++G5a3OEGI5kyZ4ywSrZIryw0AVrsM8RcJKjRFt3kgq8g5bc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729825839; c=relaxed/simple; bh=A4SBIMSGcxsT9XLkRRfk4vh3jBOWwIDqBVxBwq+7jUA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=a+eYacFOEs0AshSjbeaAjqM2JtzAwH4GSwTISNPjQhUgRguU05YVtAOXeyg9ixGqf2+Dd0iJt/ZWYKJ6efG3siQ08068C8j367b4vHfi4llwb+7syC5mMWYOmJ4fjv8NpUwa6jgtKYkNR+d6Q/mQXiVTodtBt/8qXon4t/C/UV4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=b8Knrw/B; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="b8Knrw/B" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729825837; x=1761361837; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=A4SBIMSGcxsT9XLkRRfk4vh3jBOWwIDqBVxBwq+7jUA=; b=b8Knrw/BcjLT1jiAwe8KKpBd1NV74mAYFXtUrUa5r4WBhu5JAJXmP1+R 02rIu/hV0nx2GckhzZjzwV3X+XNPqoWIEWqXhf7R1RDDDqjYM4oJviekQ bT/9N/05WVsI2w/JD6eWFkWYnSJHNP10NSaDPptfAMPvY3drIHFlqx+CR 7ST/eT3DRRLpU6OyBDLXkNtw49IZNpcOPNGR0XDovLv/2hfzta98Gej9a tTjWw8glCFrckJmPuwfGtchf+qV2CBefBFs12DIhgcMsKJ25hBm9R+z2p Ct88e7+0MxxPtKmAU5PLmDlAYn5GkzKozXViK5RtdMDGdB7xxUFTuhH6U g==; X-CSE-ConnectionGUID: yS/iIPesTg2bACvAA8ggYw== X-CSE-MsgGUID: BSm03hfwTr2+X2boA8ZR7Q== X-IronPort-AV: E=McAfee;i="6700,10204,11235"; a="29385582" X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="29385582" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:10:36 -0700 X-CSE-ConnectionGUID: 8u2917jSRgmKcYChSg9wAQ== X-CSE-MsgGUID: vic9Un7ISwWtDZ01Up00Bw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="80449711" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:10:35 -0700 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v3 03/10] x86/mce: Make several functions return bool and rename a function Date: Fri, 25 Oct 2024 10:45:55 +0800 Message-Id: <20241025024602.24318-4-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241025024602.24318-1-qiuxu.zhuo@intel.com> References: <20241016123036.21366-1-qiuxu.zhuo@intel.com> <20241025024602.24318-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Make several functions that return 0 or 1 return a boolean value for better readability. Additionally, mce_notify_irq() is about whether notifying the user and is not IRQ relevant. Rename it to mce_notify_user() to better reflect its purpose. No functional changes are intended. Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo Signed-off-by: Qiuxu Zhuo --- Changes in v3: - Collect "Reviewed-by:" from Nikolay & Sohil. - Rename mce_notify_irq() to mce_notify_user() (Sohil). Changes in v2: - Collect "Reviewed-by:" from Tony. arch/x86/include/asm/mce.h | 4 ++-- arch/x86/kernel/cpu/mce/amd.c | 10 +++++----- arch/x86/kernel/cpu/mce/core.c | 28 ++++++++++++++-------------- arch/x86/kernel/cpu/mce/inject.c | 2 +- arch/x86/kernel/cpu/mce/intel.c | 9 +++++---- 5 files changed, 27 insertions(+), 26 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 3b9970117a0f..dd9effd7c8b5 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -244,7 +244,7 @@ static inline void cmci_rediscover(void) {} static inline void cmci_recheck(void) {} #endif -int mce_available(struct cpuinfo_x86 *c); +bool mce_available(struct cpuinfo_x86 *c); bool mce_is_memory_error(struct mce *m); bool mce_is_correctable(struct mce *m); bool mce_usable_address(struct mce *m); @@ -264,7 +264,7 @@ enum mcp_flags { void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); -int mce_notify_irq(void); +bool mce_notify_user(void); DECLARE_PER_CPU(struct mce, injectm); diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 14bf8c232e45..4dae9841ee38 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -381,7 +381,7 @@ static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) return msr_high_bits & BIT(28); } -static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) +static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) { int msr = (hi & MASK_LVTOFF_HI) >> 20; @@ -389,7 +389,7 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, b->bank, b->block, b->address, hi, lo); - return 0; + return false; } if (apic != msr) { @@ -399,15 +399,15 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) * was set is reserved. Return early here: */ if (mce_flags.smca) - return 0; + return false; pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, apic, b->bank, b->block, b->address, hi, lo); - return 0; + return false; } - return 1; + return true; }; /* Reprogram MCx_MISC MSR behind this threshold bank. */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 2a938f429c4d..57c05015f984 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -479,10 +479,10 @@ static noinstr void mce_gather_info(struct mce *m, struct pt_regs *regs) } } -int mce_available(struct cpuinfo_x86 *c) +bool mce_available(struct cpuinfo_x86 *c) { if (mca_cfg.disabled) - return 0; + return false; return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); } @@ -584,7 +584,7 @@ static int mce_early_notifier(struct notifier_block *nb, unsigned long val, set_bit(0, &mce_need_notify); - mce_notify_irq(); + mce_notify_user(); return NOTIFY_DONE; } @@ -1704,7 +1704,7 @@ static void mce_timer_fn(struct timer_list *t) * Alert userspace if needed. If we logged an MCE, reduce the polling * interval, otherwise increase the polling interval. */ - if (mce_notify_irq()) + if (mce_notify_user()) iv = max(iv / 2, (unsigned long) HZ/100); else iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); @@ -1748,7 +1748,7 @@ static void mce_timer_delete_all(void) * Can be called from interrupt context, but not from machine check/NMI * context. */ -int mce_notify_irq(void) +bool mce_notify_user(void) { /* Not more than two messages every minute */ static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); @@ -1759,11 +1759,11 @@ int mce_notify_irq(void) if (__ratelimit(&ratelimit)) pr_info(HW_ERR "Machine check events logged\n"); - return 1; + return true; } - return 0; + return false; } -EXPORT_SYMBOL_GPL(mce_notify_irq); +EXPORT_SYMBOL_GPL(mce_notify_user); static void __mcheck_cpu_mce_banks_init(void) { @@ -1985,25 +1985,25 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) return 0; } -static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) +static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) { if (c->x86 != 5) - return 0; + return false; switch (c->x86_vendor) { case X86_VENDOR_INTEL: intel_p5_mcheck_init(c); mce_flags.p5 = 1; - return 1; + return true; case X86_VENDOR_CENTAUR: winchip_mcheck_init(c); mce_flags.winchip = 1; - return 1; + return true; default: - return 0; + return false; } - return 0; + return false; } /* diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index 49ed3428785d..f5a7dae385c6 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -229,7 +229,7 @@ static int raise_local(void) } else if (m->status) { pr_info("Starting machine check poll CPU %d\n", cpu); raise_poll(m); - mce_notify_irq(); + mce_notify_user(); pr_info("Machine check poll done on CPU %d\n", cpu); } else m->finished = 0; diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index b3cd2c61b11d..f863df0ff42c 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -75,12 +75,12 @@ static u16 cmci_threshold[MAX_NR_BANKS]; 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a="29385601" X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="29385601" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:10:47 -0700 X-CSE-ConnectionGUID: 5Qw8aU1KSryf8eZL3hSdUw== X-CSE-MsgGUID: rIiwAbl1R76GWnpkf1UVBw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="80449756" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:10:46 -0700 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v3 04/10] x86/mce/threshold: Remove the redundant this_cpu_dec_return() Date: Fri, 25 Oct 2024 10:45:56 +0800 Message-Id: <20241025024602.24318-5-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241025024602.24318-1-qiuxu.zhuo@intel.com> References: <20241016123036.21366-1-qiuxu.zhuo@intel.com> <20241025024602.24318-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The 'storm' variable points to this_cpu_ptr(&storm_desc). Access the 'stormy_bank_count' field through the 'storm' to avoid calling this_cpu_*() on the same per-CPU variable twice. This minor optimization reduces the text size by 16 bytes. $ size threshold.o.* text data bss dec hex filename 1395 1664 0 3059 bf3 threshold.o.old 1379 1664 0 3043 be3 threshold.o.new No functional changes intended. Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo --- Changes in v3: - Collect "Reviewed-by:" from Nikolay & Sohil. Changes in v2: - Collect "Reviewed-by:" from Tony. arch/x86/kernel/cpu/mce/threshold.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/threshold.c b/arch/x86/kernel/cpu/mce/threshold.c index 89e31e1e5c9c..f4a007616468 100644 --- a/arch/x86/kernel/cpu/mce/threshold.c +++ b/arch/x86/kernel/cpu/mce/threshold.c @@ -90,7 +90,7 @@ void cmci_storm_end(unsigned int bank) storm->banks[bank].in_storm_mode = false; /* If no banks left in storm mode, stop polling. */ - if (!this_cpu_dec_return(storm_desc.stormy_bank_count)) + if (!--storm->stormy_bank_count) mce_timer_kick(false); } From patchwork Fri Oct 25 02:45:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13849972 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C31C5C8DF; Fri, 25 Oct 2024 03:10:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729825858; cv=none; b=bnbcvIasm9bf23rdiYMvqLWQvflE9IqhVFVZ3Wr17g4ftcGNkcGv37an7uvzBc1SXyUfQ7ccX335KpAP6Cjm8ymj5xG11zgFWebymimn+0lZ4hKjvcRa38uN1k38xfC+PbmcvgHXLyKnR4VClY47vdzCccAoqhF980fEMt8w/0Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729825858; c=relaxed/simple; bh=QPS8iz5o7zWCv87loTsZLqJ/0UfTu8ebHTHlpIi1YaM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=b5ahnXu4tLEUouqdrMGCyY3NbAT12JiHxWSD8cNg0C3xjyCP7OR03eaPVCBWoaueP5Z9KhiBpWWHPLcWRUOo86paPkGH3/bf80wSXE7RfcjjkiZimakCbLNm+RFBcH1cVBnuKWaGcJwZGtZ7Qsbi69M94xeYz0+RZpKYydM3p4o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NwASJNJE; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NwASJNJE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729825857; x=1761361857; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=QPS8iz5o7zWCv87loTsZLqJ/0UfTu8ebHTHlpIi1YaM=; b=NwASJNJEvE6diNPCF4qcm5AKgmv8g2pUpUMGDQ290n3+MlelI4iFvwpK QoXaOT+92yVV8KZ3Mrm1JqXUdkE0waGwvgK63rF12M36UBYBAKM+6s1kF Mx/LjjguI4fV3NlbXoa5DdTnFtobNAVgGXzavwHkeNUYxNyDJwyF/PsZj 6YGUWM5LJ5Fsb4Szpw8rPblU4+hbdtMlIZuqwmw66qMzYYAVTB/Ptqb27 GwST83sIJD93UIqpXF0UnxvoAHVmuEUenWeLt6S+9YsfpouMMg2FSgq78 3mzxAiP6bFkSVfDZe09qJd8omHupUz9iLeqh/JdVt8Yos5A19IiRUQDVm w==; X-CSE-ConnectionGUID: npknmYukTnCzRLAnHx6B4g== X-CSE-MsgGUID: 5iC6/d33QsiEyXKL+qNBOg== X-IronPort-AV: E=McAfee;i="6700,10204,11235"; a="29385618" X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="29385618" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:10:57 -0700 X-CSE-ConnectionGUID: 3/nurZceRAuQhUuaq4zaLA== X-CSE-MsgGUID: q9FQiKN1T2+rzO1dDLtZaw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="80449801" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:10:54 -0700 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v3 05/10] x86/mce/genpool: Make mce_gen_pool_create() return explicit error codes Date: Fri, 25 Oct 2024 10:45:57 +0800 Message-Id: <20241025024602.24318-6-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241025024602.24318-1-qiuxu.zhuo@intel.com> References: <20241016123036.21366-1-qiuxu.zhuo@intel.com> <20241025024602.24318-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Make mce_gen_pool_create() return explicit error codes for better readability. No functional changes intended. Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo --- Changes in v3: - Collect "Reviewed-by:" from Nikolay & Sohil. - Move the 'int ret' along with the other int variables (Sohil). Changes in v2: - Collect "Reviewed-by:" from Tony. arch/x86/kernel/cpu/mce/genpool.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/genpool.c b/arch/x86/kernel/cpu/mce/genpool.c index 4284749ec803..64dffb50335a 100644 --- a/arch/x86/kernel/cpu/mce/genpool.c +++ b/arch/x86/kernel/cpu/mce/genpool.c @@ -118,22 +118,21 @@ int mce_gen_pool_add(struct mce *mce) static int mce_gen_pool_create(void) { - int mce_numrecords, mce_poolsz, order; + int mce_numrecords, mce_poolsz, order, ret; struct gen_pool *gpool; - int ret = -ENOMEM; void *mce_pool; order = order_base_2(sizeof(struct mce_evt_llist)); gpool = gen_pool_create(order, -1); if (!gpool) - return ret; + return -ENOMEM; mce_numrecords = max(MCE_MIN_ENTRIES, num_possible_cpus() * MCE_PER_CPU); mce_poolsz = mce_numrecords * (1 << order); mce_pool = kmalloc(mce_poolsz, GFP_KERNEL); if (!mce_pool) { gen_pool_destroy(gpool); - return ret; + return -ENOMEM; } ret = gen_pool_add(gpool, (unsigned long)mce_pool, mce_poolsz, -1); if (ret) { @@ -144,7 +143,7 @@ static int mce_gen_pool_create(void) mce_evt_pool = gpool; - return ret; + return 0; } int mce_gen_pool_init(void) From patchwork Fri Oct 25 02:45:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13849973 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02FCC12B143; Fri, 25 Oct 2024 03:11:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729825878; cv=none; b=ZGnfpdma3T52fkuZ1w5QqWzaQyQn545tPic4a9907wKruNV5Y2lfO4HT9+wfDFd4shMDXBMavAgAmuCbQbmnOXtMgy57TapOlkqLFoT7RQL32Lti4dnl4ZnJsS+ifuB75JnwK1v4YjOMkBt5gU5i+M0inGwzGOw6E9bPR/p/NfE= ARC-Message-Signature: i=1; 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d="scan'208";a="80449845" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:11:06 -0700 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v3 06/10] x86/mce: Break up __mcheck_cpu_apply_quirks() Date: Fri, 25 Oct 2024 10:45:58 +0800 Message-Id: <20241025024602.24318-7-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241025024602.24318-1-qiuxu.zhuo@intel.com> References: <20241016123036.21366-1-qiuxu.zhuo@intel.com> <20241025024602.24318-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: From: Tony Luck Split each vendor specific part into its own helper function. Tested-by: Qiuxu Zhuo Signed-off-by: Tony Luck Signed-off-by: Qiuxu Zhuo --- Changes in v3: - Newly added. arch/x86/kernel/cpu/mce/core.c | 194 ++++++++++++++++++--------------- 1 file changed, 106 insertions(+), 88 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 57c05015f984..bb8b1000fa0a 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1880,101 +1880,119 @@ static void __mcheck_cpu_check_banks(void) } } +static void apply_quirks_amd(struct cpuinfo_x86 *c) +{ + struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); + struct mca_config *cfg = &mca_cfg; + + /* This should be disabled by the BIOS, but isn't always */ + if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { + /* + * disable GART TBL walk error reporting, which + * trips off incorrectly with the IOMMU & 3ware + * & Cerberus: + */ + clear_bit(10, (unsigned long *)&mce_banks[4].ctl); + } + if (c->x86 < 0x11 && cfg->bootlog < 0) { + /* + * Lots of broken BIOS around that don't clear them + * by default and leave crap in there. Don't log: + */ + cfg->bootlog = 0; + } + /* + * Various K7s with broken bank 0 around. Always disable + * by default. + */ + if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0) + mce_banks[0].ctl = 0; + + /* + * overflow_recov is supported for F15h Models 00h-0fh + * even though we don't have a CPUID bit for it. + */ + if (c->x86 == 0x15 && c->x86_model <= 0xf) + mce_flags.overflow_recov = 1; + + if (c->x86 >= 0x17 && c->x86 <= 0x1A) + mce_flags.zen_ifu_quirk = 1; +} + +static void apply_quirks_intel(struct cpuinfo_x86 *c) +{ + struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); + struct mca_config *cfg = &mca_cfg; + + /* + * SDM documents that on family 6 bank 0 should not be written + * because it aliases to another special BIOS controlled + * register. + * But it's not aliased anymore on model 0x1a+ + * Don't ignore bank 0 completely because there could be a + * valid event later, merely don't write CTL0. + */ + if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) + mce_banks[0].init = false; + + /* + * All newer Intel systems support MCE broadcasting. Enable + * synchronization with a one second timeout. + */ + if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && + cfg->monarch_timeout < 0) + cfg->monarch_timeout = USEC_PER_SEC; + + /* + * There are also broken BIOSes on some Pentium M and + * earlier systems: + */ + if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) + cfg->bootlog = 0; + + if (c->x86_vfm == INTEL_SANDYBRIDGE_X) + mce_flags.snb_ifu_quirk = 1; + + /* + * Skylake, Cascacde Lake and Cooper Lake require a quirk on + * rep movs. + */ + if (c->x86_vfm == INTEL_SKYLAKE_X) + mce_flags.skx_repmov_quirk = 1; +} + +static void apply_quirks_zhaoxin(struct cpuinfo_x86 *c) +{ + struct mca_config *cfg = &mca_cfg; + + /* + * All newer Zhaoxin CPUs support MCE broadcasting. Enable + * synchronization with a one second timeout. + */ + if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) { + if (cfg->monarch_timeout < 0) + cfg->monarch_timeout = USEC_PER_SEC; + } +} + /* Add per CPU specific workarounds here */ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) { - struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); struct mca_config *cfg = &mca_cfg; - if (c->x86_vendor == X86_VENDOR_UNKNOWN) { + switch (c->x86_vendor) { + case X86_VENDOR_UNKNOWN: pr_info("unknown CPU type - not enabling MCE support\n"); return -EOPNOTSUPP; - } - - /* This should be disabled by the BIOS, but isn't always */ - if (c->x86_vendor == X86_VENDOR_AMD) { - if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { - /* - * disable GART TBL walk error reporting, which - * trips off incorrectly with the IOMMU & 3ware - * & Cerberus: - */ - clear_bit(10, (unsigned long *)&mce_banks[4].ctl); - } - if (c->x86 < 0x11 && cfg->bootlog < 0) { - /* - * Lots of broken BIOS around that don't clear them - * by default and leave crap in there. Don't log: - */ - cfg->bootlog = 0; - } - /* - * Various K7s with broken bank 0 around. Always disable - * by default. - */ - if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0) - mce_banks[0].ctl = 0; - - /* - * overflow_recov is supported for F15h Models 00h-0fh - * even though we don't have a CPUID bit for it. - */ - if (c->x86 == 0x15 && c->x86_model <= 0xf) - mce_flags.overflow_recov = 1; - - if (c->x86 >= 0x17 && c->x86 <= 0x1A) - mce_flags.zen_ifu_quirk = 1; - - } - - if (c->x86_vendor == X86_VENDOR_INTEL) { - /* - * SDM documents that on family 6 bank 0 should not be written - * because it aliases to another special BIOS controlled - * register. - * But it's not aliased anymore on model 0x1a+ - * Don't ignore bank 0 completely because there could be a - * valid event later, merely don't write CTL0. - */ - - if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) - mce_banks[0].init = false; - - /* - * All newer Intel systems support MCE broadcasting. Enable - * synchronization with a one second timeout. - */ - if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && - cfg->monarch_timeout < 0) - cfg->monarch_timeout = USEC_PER_SEC; - - /* - * There are also broken BIOSes on some Pentium M and - * earlier systems: - */ - if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) - cfg->bootlog = 0; - - if (c->x86_vfm == INTEL_SANDYBRIDGE_X) - mce_flags.snb_ifu_quirk = 1; - - /* - * Skylake, Cascacde Lake and Cooper Lake require a quirk on - * rep movs. - */ - if (c->x86_vfm == INTEL_SKYLAKE_X) - mce_flags.skx_repmov_quirk = 1; - } - - if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { - /* - * All newer Zhaoxin CPUs support MCE broadcasting. Enable - * synchronization with a one second timeout. - */ - if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) { - if (cfg->monarch_timeout < 0) - cfg->monarch_timeout = USEC_PER_SEC; - } + case X86_VENDOR_AMD: + apply_quirks_amd(c); + break; + case X86_VENDOR_INTEL: + apply_quirks_intel(c); + break; + case X86_VENDOR_ZHAOXIN: + apply_quirks_zhaoxin(c); + break; } if (cfg->monarch_timeout < 0) From patchwork Fri Oct 25 02:45:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13849974 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7745318A6AA; Fri, 25 Oct 2024 03:11:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729825880; cv=none; b=R4RXskBGyOEQnBTKryjUKDlzOij9juw7vvm+wPcRGbxccMoTlQh028N8cddo06K0i7XA31Ik98zFViNXYtZMytYH1WY66CWXoxQdeqPQ+90IJy+VMz2LD7pWE2fr7eB3TcBcXWGmCg6Scm6a0rWaeGe6ytZGtUzGXZi3D5KQKt4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729825880; c=relaxed/simple; bh=riRYIu549TqQL9NAjo3bdoB4DBxCVvJ1sN5Z8POMX/I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=RNzbeYIS1PEBoicTUgSGHsLtkFQNf4E18zT6GokzVnZyacLqvC0zr5HpTglTx3DttLEH3e+nxZCy//fZ/+aF57AD9M+RDpRJL3FoI9kzvsEPAC8aQlr6ldcc0ul2dyvrH5yj0GNkCwlqX1bIvz9lyC3C0F4H19avClV9W0VJNGo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=km19rUW3; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="km19rUW3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729825879; x=1761361879; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=riRYIu549TqQL9NAjo3bdoB4DBxCVvJ1sN5Z8POMX/I=; b=km19rUW3BMKOmvuno6Q5AnClEcHv/cNH1wN4x45fiLbIQR3eLATaJiGr M7DBRDcPv0Ba7AwZaiJwwadgWa8o5DE1U7cKzSS5nyCBsCN255aWMsPC9 w4rx32zcfGsJfvvtOm3kaDM5alnPBoKy3pjJxmsz12RdYjfzzQMWVSUas ZInv5VFaEyoD+QqdzaOuudhxCygyg2cEl9NDc8swehvjk1w7TwLhFBqJQ WGHSyRSgu1m2jQ+7j+8IQwozsnrF1MoMOIDb1AsHHNQD3B4p3zKcXGBj2 zuFRQ7We8P1sjsjPJozWqsStebw2mm13B1y8QaYHmCeZZAqzmZD9IQeJH A==; X-CSE-ConnectionGUID: boM+MZDoQVeDKN4nJjx9Hw== X-CSE-MsgGUID: ETQ6LGUTQqC1650PZ5788A== X-IronPort-AV: E=McAfee;i="6700,10204,11235"; a="29385658" X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="29385658" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:11:18 -0700 X-CSE-ConnectionGUID: uOVQgan8TyaIhyG0wZVa6A== X-CSE-MsgGUID: oFUtcQ34TdKSqEaYpoP2ZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="80449860" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:11:17 -0700 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v3 07/10] x86/mce: Convert family/model mixed checks to VFM-based checks Date: Fri, 25 Oct 2024 10:45:59 +0800 Message-Id: <20241025024602.24318-8-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241025024602.24318-1-qiuxu.zhuo@intel.com> References: <20241016123036.21366-1-qiuxu.zhuo@intel.com> <20241025024602.24318-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Convert family/model mixed checks to VFM-based checks to make the code more compact. Suggested-by: Sohil Mehta Suggested-by: Dave Hansen Reviewed-by: Tony Luck Signed-off-by: Qiuxu Zhuo --- Changes in v3: - Newly added. arch/x86/kernel/cpu/mce/core.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index bb8b1000fa0a..936804a5a0b9 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1924,6 +1924,10 @@ static void apply_quirks_intel(struct cpuinfo_x86 *c) struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); struct mca_config *cfg = &mca_cfg; + /* Older CPUs (prior to family 6) don't need quirks. */ + if (c->x86_vfm < INTEL_PENTIUM_PRO) + return; + /* * SDM documents that on family 6 bank 0 should not be written * because it aliases to another special BIOS controlled @@ -1932,22 +1936,21 @@ static void apply_quirks_intel(struct cpuinfo_x86 *c) * Don't ignore bank 0 completely because there could be a * valid event later, merely don't write CTL0. */ - if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) + if (c->x86_vfm < INTEL_NEHALEM_EP && this_cpu_read(mce_num_banks) > 0) mce_banks[0].init = false; /* * All newer Intel systems support MCE broadcasting. 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Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo --- Changes in v3: - Collect "Reviewed-by:" from Nikolay & Sohil. Changes in v2: - Collect "Reviewed-by:" from Tony. arch/x86/kernel/cpu/mce/core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 936804a5a0b9..f57a68b53f29 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -2090,10 +2090,9 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) mce_intel_feature_init(c); break; - case X86_VENDOR_AMD: { + case X86_VENDOR_AMD: mce_amd_feature_init(c); break; - } case X86_VENDOR_HYGON: mce_hygon_feature_init(c); From patchwork Fri Oct 25 02:46:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13849976 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E01718BBB6; Fri, 25 Oct 2024 03:11:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729825896; cv=none; b=tP0kqbKyE56SL6eHozd9heiXwFQkYTPTK2lG/NTZYnaQ0/1CK0oqeuffVGv30p5k0y+qyPs1JOf4ujO3Kqm7Fb0lSzwS6VvSIoADpGFbXynUj10aedtDcDswmWjkNim/zjWRMEPtUbt14MLSA9WmuZ3DeY8x2C3G5L1G8yg0deA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729825896; c=relaxed/simple; bh=WpEKt+OyZ/LmeihHlVtlOKhimP5oOSakRNdbsOE9Yr8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=Td2L+fUrRUzvkpCu1rv0N7B+XLe1PQ8cUR92l7qkgMr3dzf5rPj3hntoZmQjjxCJmJEU786rCNH4DVhgSdJfKNGK72kr/0iZM9X7XSUx5qZHWjwQmQtPdD2WVTYnzUr+rJrZVGvcAUXd1tl1yzsILHyxJ5Spu1A5eVjnyDFCIDg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=M0VOmDdI; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="M0VOmDdI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729825894; x=1761361894; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=WpEKt+OyZ/LmeihHlVtlOKhimP5oOSakRNdbsOE9Yr8=; b=M0VOmDdItNB8pRMtv6paVjJ7X/8mCKi2+DrnzMKSADqDuyL7zHC2Ia5r kKHkytZYw6VM3ui+IteYVbBgE5Xv71P16WfXz5hr+j9EvtVjsS1Ar4yBt 3kH76jUAfwRoclbZ3eY6FTuCOIJvUa4B2em8+wWiwv5tNMc0nZHIwRGcK 0VmXGj7YTwfNrVZiWZR0m06Z7R316EFbCCSpUwxWrpIYTYdNStT28QjaD IWBmc3hsBdTcaGT1mlydc/2Xh0QuHquABsO7s09d/GYVaswEKCrSQwr69 IZkHER9h9macKA32KliEo9bygilkBNYyXxd1koevd3hcDKdtGnrXroPEb A==; X-CSE-ConnectionGUID: dTIGKB9dS1e4T0PMY4tszA== X-CSE-MsgGUID: 9aBJ9FkcSpOMpry1Yl0I6A== X-IronPort-AV: E=McAfee;i="6700,10204,11235"; a="29385698" X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="29385698" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:11:34 -0700 X-CSE-ConnectionGUID: 9etoNflWSE+jyiF50WDZsQ== X-CSE-MsgGUID: GE6JpLNdQKGWXJ3cLGND8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="80449894" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:11:32 -0700 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v3 09/10] x86/mce/amd: Remove unnecessary NULL pointer initializations Date: Fri, 25 Oct 2024 10:46:01 +0800 Message-Id: <20241025024602.24318-10-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241025024602.24318-1-qiuxu.zhuo@intel.com> References: <20241016123036.21366-1-qiuxu.zhuo@intel.com> <20241025024602.24318-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Remove unnecessary NULL pointer initializations from variables that are already initialized before use. Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo --- Changes in v3: - Collect "Reviewed-by:" Nikolay & Sohil. - Remove the variables' names from the commit message (Sohil). arch/x86/kernel/cpu/mce/amd.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 4dae9841ee38..aecea842dac2 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -917,8 +917,8 @@ static void log_and_reset_block(struct threshold_block *block) */ static void amd_threshold_interrupt(void) { - struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; struct threshold_bank **bp = this_cpu_read(threshold_banks); + struct threshold_block *first_block, *block, *tmp; unsigned int bank, cpu = smp_processor_id(); /* @@ -1197,8 +1197,7 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb static int __threshold_add_blocks(struct threshold_bank *b) { struct list_head *head = &b->blocks->miscj; - struct threshold_block *pos = NULL; - struct threshold_block *tmp = NULL; + struct threshold_block *pos, *tmp; int err = 0; err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); @@ -1308,8 +1307,7 @@ static void deallocate_threshold_blocks(struct threshold_bank *bank) static void __threshold_remove_blocks(struct threshold_bank *b) { - struct threshold_block *pos = NULL; - struct threshold_block *tmp = NULL; + struct threshold_block *pos, *tmp; kobject_put(b->kobj); From patchwork Fri Oct 25 02:46:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13849977 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9810F18BBB6; Fri, 25 Oct 2024 03:11:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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d="scan'208";a="29385719" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:11:43 -0700 X-CSE-ConnectionGUID: 94i8JjGsSQCes6WDUO6cgg== X-CSE-MsgGUID: FNjHbGCwTWWVLrjUzfpr2w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="80449907" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 20:11:42 -0700 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v3 10/10] x86/mce: Fix typos Date: Fri, 25 Oct 2024 10:46:02 +0800 Message-Id: <20241025024602.24318-11-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241025024602.24318-1-qiuxu.zhuo@intel.com> References: <20241016123036.21366-1-qiuxu.zhuo@intel.com> <20241025024602.24318-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Fix typos in comments. Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo --- Changes in v3: - Collect "Reviewed-by:" from Nikolay & Sohil. - Remove the detail typos from the commit message (Sohil). Changes in v2: - Collect "Reviewed-by:" from Tony. arch/x86/kernel/cpu/mce/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index f57a68b53f29..4c4558ed4736 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1120,7 +1120,7 @@ static noinstr int mce_start(int *no_way_out) } else { /* * Subject: Now start the scanning loop one by one in - * the original callin order. + * the original calling order. * This way when there are any shared banks it will be * only seen by one CPU before cleared, avoiding duplicates. */ @@ -1888,7 +1888,7 @@ static void apply_quirks_amd(struct cpuinfo_x86 *c) /* This should be disabled by the BIOS, but isn't always */ if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { /* - * disable GART TBL walk error reporting, which + * disable GART TLB walk error reporting, which * trips off incorrectly with the IOMMU & 3ware * & Cerberus: */