From patchwork Fri Oct 25 12:45:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 13850657 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36FEDD0C608 for ; Fri, 25 Oct 2024 12:58:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=nLKovh7m+yI60Zvb7nhvOgVEU7nNjBthucfKY5rYw+E=; b=VMwmzCYQ0XwoD2YxO/N2yQrUKt JYnYG3je4RSabbucsZD0Up1o72YYlbKZH5c4rztH4TUS6xuvELEbScW2qQTdKSWHN4KnZxr5cdJM+ 54MFis7tsvQjACETAlUguI6Q+qsakW/KJviIYQnuh7B34Y1CsWofoMVfEL4XwC1LJY2kzH2GgSQib qNygHdLU2DR96Wz8FcqKsaBUr+OZkoDJAD7qtA7AFnD5UpBiGOOtoVGWBBYYPsIFtumG+TXKhe7HK wX/eOq8f1jT6gYI9Rb/sf2a2Vhx5xRsYY54L5zM1NbnP6IahADITsOon6YfZTA3Nxql3QCFO0afF7 ZCqaM7rA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t4JtI-00000003k0f-0PJz; Fri, 25 Oct 2024 12:58:08 +0000 Received: from smtp-out2.suse.de ([195.135.223.131]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t4Jh5-00000003ht1-3yFo; Fri, 25 Oct 2024 12:45:36 +0000 Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 49D771FE0C; Fri, 25 Oct 2024 12:45:28 +0000 (UTC) Authentication-Results: smtp-out2.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 392F513B16; Fri, 25 Oct 2024 12:45:27 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id 0NqAC+eSG2fzOAAAD6G6ig (envelope-from ); Fri, 25 Oct 2024 12:45:27 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH v4 01/10] dt-bindings: interrupt-controller: Add bcm2712 MSI-X DT bindings Date: Fri, 25 Oct 2024 15:45:06 +0300 Message-ID: <20241025124515.14066-2-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241025124515.14066-1-svarbanov@suse.de> References: <20241025124515.14066-1-svarbanov@suse.de> MIME-Version: 1.0 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[]; TAGGED_RCPT(0.00)[dt]; ASN(0.00)[asn:25478, ipnet:::/0, country:RU] X-Rspamd-Queue-Id: 49D771FE0C X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241025_054532_207425_B8DB69EB X-CRM114-Status: GOOD ( 12.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds DT bindings for bcm2712 MSI-X interrupt peripheral controller. Signed-off-by: Stanimir Varbanov Reviewed-by: Rob Herring (Arm) --- v3 -> v4: - Added Reviewed-by. .../brcm,bcm2712-msix.yaml | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml new file mode 100644 index 000000000000..c84614663b5d --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2712-msix.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom bcm2712 MSI-X Interrupt Peripheral support + +maintainers: + - Stanimir Varbanov + +description: + This interrupt controller is used to provide interrupt vectors to the + generic interrupt controller (GIC) on bcm2712. It will be used as + external MSI-X controller for PCIe root complex. + +allOf: + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + const: brcm,bcm2712-mip + + reg: + items: + - description: Base register address + - description: PCIe message address + + "#msi-cells": + const: 0 + + brcm,msi-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Shift the allocated MSI's. + +unevaluatedProperties: false + +required: + - compatible + - reg + - msi-controller + - msi-ranges + +examples: + - | + #include + + axi { + #address-cells = <2>; + #size-cells = <2>; + + msi-controller@1000130000 { + compatible = "brcm,bcm2712-mip"; + reg = <0x10 0x00130000 0x00 0xc0>, + <0xff 0xfffff000 0x00 0x1000>; + msi-controller; + #msi-cells = <0>; + msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>; + }; + }; From patchwork Fri Oct 25 12:45:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 13850658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49A57D0C606 for ; Fri, 25 Oct 2024 12:59:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=c+uowGpwUz5NCg78o2YaCLio5zeWFG4cEvQGLiJUC+8=; b=Dd7eRLTDvwmBCl9Zg4GwMX0tG+ ryE6iWPSD9T1C9t7Z0KlOUtaCV3Id+JDyZM1pvlRuqHtedbMr/448whvtbQUiIJRHng98Iah5YMhc 5Jnk0WL/KTYCPzWTSS0j387EmWrcrTbhesge25N/szUXGcMMB64+Xbhx+0LCN1UFYdcQa19cm99s+ tuih0OHZgeKhv5+V+AMWRviMwrGarcuuRMDejYOI599VwOHJ/22tOkqIhRYmJ9gYb/hahffP9Mvzn DRWg/ATDueQIg/iyQG9kgiB0ENSPLZFGnl3p5uXhSiQXtmBtsRKsd52U5DRxviZSLnDEeYqCBWvJA e/ZfnNbg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t4Jup-00000003kDX-31Hg; Fri, 25 Oct 2024 12:59:43 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t4JhA-00000003hv2-3kdh; Fri, 25 Oct 2024 12:45:37 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=c+uowGpwUz5NCg78o2YaCLio5zeWFG4cEvQGLiJUC+8=; b=obDoRzj+hQCHma20syUqBcwTB2 UHBeT7Ky3pA1Dc0HtvISYomw2fjS/QSga3Cr/Fz00Eg7SFz9LKSBS1KP7isC8cKlt13OevVBYgmgm bClItgIB6gbEQ46s3YoNx6PDsFGSXfVo6zWQbt0mv1WmsxQ/fepUWFGipkA7wrwte94UzadCIBFma x7jKvwW7GD49Wqwg7GQZy67IdOrD9fabT4qMDxmgrECDGs5VSW5ha8dxY06W1SI8sTKNjcmRpqZFS pf5tS2YGt94IA0qqM7oSji9p9xj9YsFmjszwGOSD1JEiT5/oInvad9rJ6BWb2xpjCey3bRLh1kC+P 5StmJ5jQ==; Received: from smtp-out2.suse.de ([195.135.223.131]) by desiato.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t4Jh7-00000008uOz-275V; Fri, 25 Oct 2024 12:45:35 +0000 Received: from imap1.dmz-prg2.suse.org (unknown [10.150.64.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 238D81FE70; Fri, 25 Oct 2024 12:45:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1729860331; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c+uowGpwUz5NCg78o2YaCLio5zeWFG4cEvQGLiJUC+8=; b=fJLoP7nu8RvnLSMPOjuFFhjBS0/Auc5a2ZdCNFdYAVV2Sm0sLUpMXkEPUPtxuxmIsQm1pU mzETq6vwoxzoz8yOEy5NxJtfJ4U3p3hDKLqn9ND5nek75t+gTJegC+4q6Wz4+koLVukQlh wToHvgygOfjdPHhwBe5oVWHSZTwNd5M= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1729860331; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c+uowGpwUz5NCg78o2YaCLio5zeWFG4cEvQGLiJUC+8=; b=C1K/li4t+9hKT7sIMCkW4VRMhEH9Z3F2rYYIgY2SP46BfaSAc+oOodNQRiXO70bv3JmK0v YIS9vqZwmW7pTBDA== Authentication-Results: smtp-out2.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1729860331; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c+uowGpwUz5NCg78o2YaCLio5zeWFG4cEvQGLiJUC+8=; b=fJLoP7nu8RvnLSMPOjuFFhjBS0/Auc5a2ZdCNFdYAVV2Sm0sLUpMXkEPUPtxuxmIsQm1pU mzETq6vwoxzoz8yOEy5NxJtfJ4U3p3hDKLqn9ND5nek75t+gTJegC+4q6Wz4+koLVukQlh wToHvgygOfjdPHhwBe5oVWHSZTwNd5M= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1729860331; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=c+uowGpwUz5NCg78o2YaCLio5zeWFG4cEvQGLiJUC+8=; b=C1K/li4t+9hKT7sIMCkW4VRMhEH9Z3F2rYYIgY2SP46BfaSAc+oOodNQRiXO70bv3JmK0v YIS9vqZwmW7pTBDA== Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 625B213B16; Fri, 25 Oct 2024 12:45:29 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id YNGVFemSG2fzOAAAD6G6ig (envelope-from ); Fri, 25 Oct 2024 12:45:29 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH v4 03/10] irqchip: Add Broadcom bcm2712 MSI-X interrupt controller Date: Fri, 25 Oct 2024 15:45:08 +0300 Message-ID: <20241025124515.14066-4-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241025124515.14066-1-svarbanov@suse.de> References: <20241025124515.14066-1-svarbanov@suse.de> MIME-Version: 1.0 X-Spamd-Result: default: False [-5.30 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TAGGED_RCPT(0.00)[dt]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCPT_COUNT_TWELVE(0.00)[21]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; FREEMAIL_CC(0.00)[linutronix.de,kernel.org,broadcom.com,gmail.com,google.com,linux.com,pengutronix.de,suse.com,raspberrypi.com,suse.de]; FROM_HAS_DN(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.de:email,suse.de:mid,imap1.dmz-prg2.suse.org:helo]; RCVD_COUNT_TWO(0.00)[2]; RCVD_TLS_ALL(0.00)[]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; R_RATELIMIT(0.00)[to_ip_from(RL7mwea5a3cdyragbzqhrtit3y)]; FUZZY_BLOCKED(0.00)[rspamd.com]; FREEMAIL_ENVRCPT(0.00)[gmail.com] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241025_134533_834824_E46BB767 X-CRM114-Status: GOOD ( 25.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add an interrupt controller driver for MSI-X Interrupt Peripheral (MIP) hardware block found in bcm2712. The interrupt controller is used to handle MSI-X interrupts from peripherials behind PCIe endpoints like RP1 south bridge found in RPi5. There are two MIPs on bcm2712, the first has 64 consecutive SPIs assigned to 64 output vectors, and the second has 17 SPIs, but only 8 of them are consecutive starting at the 8th output vector. Signed-off-by: Stanimir Varbanov --- v3 -> v4: - Addressed the comments for wrongly used PCI/MSI flags (Thomas) drivers/irqchip/Kconfig | 16 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-bcm2712-mip.c | 310 ++++++++++++++++++++++++++++++ 3 files changed, 327 insertions(+) create mode 100644 drivers/irqchip/irq-bcm2712-mip.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 341cd9ca5a05..c9bd0a4f6871 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -116,6 +116,22 @@ config I8259 bool select IRQ_DOMAIN +config BCM2712_MIP + tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" + depends on ARCH_BRCMSTB || COMPILE_TEST + default m if ARCH_BRCMSTB + depends on ARM_GIC + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN_HIERARCHY + select GENERIC_MSI_IRQ + select IRQ_MSI_LIB + help + Enable support for the Broadcom BCM2712 MSI-X target peripheral + (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on + Raspberry Pi 5. + + If unsure say n. + config BCM6345_L1_IRQ bool select GENERIC_IRQ_CHIP diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e3679ec2b9f7..a11307b1b610 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o obj-$(CONFIG_XILINX_INTC) += irq-xilinx-intc.o obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o +obj-$(CONFIG_BCM2712_MIP) += irq-bcm2712-mip.o obj-$(CONFIG_BCM6345_L1_IRQ) += irq-bcm6345-l1.o obj-$(CONFIG_BCM7038_L1_IRQ) += irq-bcm7038-l1.o obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o diff --git a/drivers/irqchip/irq-bcm2712-mip.c b/drivers/irqchip/irq-bcm2712-mip.c new file mode 100644 index 000000000000..fd73f2d41279 --- /dev/null +++ b/drivers/irqchip/irq-bcm2712-mip.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024 Raspberry Pi Ltd., All Rights Reserved. + * Copyright (c) 2024 SUSE + */ + +#include +#include +#include +#include +#include +#include + +#include "irq-msi-lib.h" + +#define MIP_INT_RAISE 0x00 +#define MIP_INT_CLEAR 0x10 +#define MIP_INT_CFGL_HOST 0x20 +#define MIP_INT_CFGH_HOST 0x30 +#define MIP_INT_MASKL_HOST 0x40 +#define MIP_INT_MASKH_HOST 0x50 +#define MIP_INT_MASKL_VPU 0x60 +#define MIP_INT_MASKH_VPU 0x70 +#define MIP_INT_STATUSL_HOST 0x80 +#define MIP_INT_STATUSH_HOST 0x90 +#define MIP_INT_STATUSL_VPU 0xa0 +#define MIP_INT_STATUSH_VPU 0xb0 + +/** + * struct mip_priv - MSI-X interrupt controller data + * @lock: Used to protect bitmap alloc/free + * @base: Base address of MMIO area + * @msg_addr: PCIe MSI-X address + * @msi_base: MSI base + * @num_msis: Count of MSIs + * @msi_offset: MSI offset + * @bitmap: A bitmap for hwirqs + * @parent: Parent domain (GIC) + * @dev: A device pointer + */ +struct mip_priv { + spinlock_t lock; + void __iomem *base; + u64 msg_addr; + u32 msi_base; + u32 num_msis; + u32 msi_offset; + unsigned long *bitmap; + struct irq_domain *parent; + struct device *dev; +}; + +static void mip_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) +{ + struct mip_priv *mip = irq_data_get_irq_chip_data(d); + + msg->address_hi = upper_32_bits(mip->msg_addr); + msg->address_lo = lower_32_bits(mip->msg_addr); + msg->data = d->hwirq; +} + +static struct irq_chip mip_middle_irq_chip = { + .name = "MIP", + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_eoi = irq_chip_eoi_parent, + .irq_set_affinity = irq_chip_set_affinity_parent, + .irq_set_type = irq_chip_set_type_parent, + .irq_compose_msi_msg = mip_compose_msi_msg, +}; + +static int mip_alloc_hwirq(struct mip_priv *mip, unsigned int nr_irqs, + unsigned int *hwirq) +{ + int bit; + + spin_lock(&mip->lock); + bit = bitmap_find_free_region(mip->bitmap, mip->num_msis, + ilog2(nr_irqs)); + spin_unlock(&mip->lock); + + if (bit < 0) + return bit; + + if (hwirq) + *hwirq = bit; + + return 0; +} + +static void mip_free_hwirq(struct mip_priv *mip, unsigned int hwirq, + unsigned int nr_irqs) +{ + spin_lock(&mip->lock); + bitmap_release_region(mip->bitmap, hwirq, ilog2(nr_irqs)); + spin_unlock(&mip->lock); +} + +static int mip_middle_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + struct mip_priv *mip = domain->host_data; + struct irq_fwspec fwspec = {0}; + unsigned int hwirq, irq, i; + struct irq_data *irqd; + int ret; + + ret = mip_alloc_hwirq(mip, nr_irqs, &irq); + if (ret < 0) + return ret; + + hwirq = irq + mip->msi_offset; + + fwspec.fwnode = domain->parent->fwnode; + fwspec.param_count = 3; + fwspec.param[0] = 0; + fwspec.param[1] = hwirq + mip->msi_base; + fwspec.param[2] = IRQ_TYPE_EDGE_RISING; + + ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &fwspec); + if (ret) { + mip_free_hwirq(mip, irq, nr_irqs); + return ret; + } + + for (i = 0; i < nr_irqs; i++) { + irqd = irq_domain_get_irq_data(domain->parent, virq + i); + irqd->chip->irq_set_type(irqd, IRQ_TYPE_EDGE_RISING); + + ret = irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, + &mip_middle_irq_chip, mip); + if (ret) + goto err_free; + + irqd = irq_get_irq_data(virq + i); + irqd_set_single_target(irqd); + irqd_set_affinity_on_activate(irqd); + } + + return 0; + +err_free: + irq_domain_free_irqs_parent(domain, virq, nr_irqs); + mip_free_hwirq(mip, irq, nr_irqs); + return ret; +} + +static void mip_middle_domain_free(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs) +{ + struct irq_data *irqd = irq_domain_get_irq_data(domain, virq); + struct mip_priv *mip; + unsigned int hwirq; + + if (!irqd) + return; + + mip = irq_data_get_irq_chip_data(irqd); + hwirq = irqd_to_hwirq(irqd); + irq_domain_free_irqs_parent(domain, virq, nr_irqs); + mip_free_hwirq(mip, hwirq - mip->msi_offset, nr_irqs); +} + +static const struct irq_domain_ops mip_middle_domain_ops = { + .select = msi_lib_irq_domain_select, + .alloc = mip_middle_domain_alloc, + .free = mip_middle_domain_free, +}; + +#define MIP_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS | \ + MSI_FLAG_PCI_MSI_MASK_PARENT) + +#define MIP_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ + MSI_FLAG_MULTI_PCI_MSI | \ + MSI_FLAG_PCI_MSIX) + +static const struct msi_parent_ops mip_msi_parent_ops = { + .supported_flags = MIP_MSI_FLAGS_SUPPORTED, + .required_flags = MIP_MSI_FLAGS_REQUIRED, + .bus_select_token = DOMAIN_BUS_GENERIC_MSI, + .bus_select_mask = MATCH_PCI_MSI, + .prefix = "MIP-MSI-", + .init_dev_msi_info = msi_lib_init_dev_msi_info, +}; + +static int mip_init_domains(struct mip_priv *mip, struct device_node *np) +{ + struct irq_domain *middle; + + middle = irq_domain_add_hierarchy(mip->parent, 0, mip->num_msis, np, + &mip_middle_domain_ops, mip); + if (!middle) + return -ENOMEM; + + irq_domain_update_bus_token(middle, DOMAIN_BUS_GENERIC_MSI); + middle->dev = mip->dev; + middle->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; + middle->msi_parent_ops = &mip_msi_parent_ops; + + return 0; +} + +static int mip_parse_dt(struct mip_priv *mip, struct device_node *np) +{ + struct of_phandle_args args; + u64 size; + int ret; + + ret = of_property_read_u32(np, "brcm,msi-offset", &mip->msi_offset); + if (ret) + mip->msi_offset = 0; + + ret = of_parse_phandle_with_args(np, "msi-ranges", "#interrupt-cells", + 0, &args); + if (ret) + return ret; + + ret = of_property_read_u32_index(np, "msi-ranges", args.args_count + 1, + &mip->num_msis); + if (ret) + goto err_put; + + ret = of_property_read_reg(np, 1, &mip->msg_addr, &size); + if (ret) + goto err_put; + + mip->msi_base = args.args[1]; + + mip->parent = irq_find_host(args.np); + if (!mip->parent) + ret = -EINVAL; + +err_put: + of_node_put(args.np); + return ret; +} + +static int __init mip_of_msi_init(struct device_node *node, + struct device_node *parent) +{ + struct platform_device *pdev; + struct mip_priv *mip; + int ret; + + pdev = of_find_device_by_node(node); + of_node_put(node); + if (!pdev) + return -EPROBE_DEFER; + + mip = kzalloc(sizeof(*mip), GFP_KERNEL); + if (!mip) + return -ENOMEM; + + spin_lock_init(&mip->lock); + mip->dev = &pdev->dev; + + ret = mip_parse_dt(mip, node); + if (ret) + goto err_priv; + + mip->base = of_iomap(node, 0); + if (!mip->base) { + ret = -ENXIO; + goto err_priv; + } + + mip->bitmap = bitmap_zalloc(mip->num_msis, GFP_KERNEL); + if (!mip->bitmap) { + ret = -ENOMEM; + goto err_base; + } + + /* + * All MSI-X masked in for the host, masked out for the + * VPU, and edge-triggered. + */ + writel(0, mip->base + MIP_INT_MASKL_HOST); + writel(0, mip->base + MIP_INT_MASKH_HOST); + writel(~0, mip->base + MIP_INT_MASKL_VPU); + writel(~0, mip->base + MIP_INT_MASKH_VPU); + writel(~0, mip->base + MIP_INT_CFGL_HOST); + writel(~0, mip->base + MIP_INT_CFGH_HOST); + + ret = mip_init_domains(mip, node); + if (ret) + goto err_map; + + dev_dbg(&pdev->dev, + "MIP: MSI-X count: %u, base: %u, offset: %u, msg_addr: %llx\n", + mip->num_msis, mip->msi_base, mip->msi_offset, mip->msg_addr); + + return 0; + +err_map: + bitmap_free(mip->bitmap); +err_base: + iounmap(mip->base); +err_priv: + kfree(mip); + return ret; +} + +IRQCHIP_PLATFORM_DRIVER_BEGIN(mip_msi) +IRQCHIP_MATCH("brcm,bcm2712-mip", mip_of_msi_init) +IRQCHIP_PLATFORM_DRIVER_END(mip_msi) +MODULE_DESCRIPTION("Broadcom BCM2712 MSI interrupt controller"); +MODULE_AUTHOR("Phil Elwell "); +MODULE_AUTHOR("Stanimir Varbanov "); +MODULE_LICENSE("GPL"); From patchwork Fri Oct 25 12:45:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 13850656 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28292D0C606 for ; Fri, 25 Oct 2024 12:52:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=SUoecVArR0gU+CZkZ6/sQs7f+/bMYvuPi352qAGfjU8=; b=EMf3acxgOc9hlwC5717ZZRbQlc wy3kV7MjTW9Q8vpChRRgb/G5moswvdIS2fAsmonKWoX9Ani8w0iTnpIiKEZe4yVVf+7cd1TLguvCG exjO7ALTlk1a4V852dUcdpjJWzLB1Mf2+490N1zbX97qzxkVH7jyndhzPIr4uPwFF39ODxYirAOW2 Fy5d+EP8viAj+WYam88rcQgCPghLtEIklJayny1aeBSozGrnUr5II8EJtLR4Pm4TQwBYIxUmGWTWI VuDHfV5pRDKfrgz6vB8HHv0wxuh3NrN3DQy/FFyQOdg754q6LFnwf3Ax/MYQuOvfb83g+FLIRJ0oo sKPuD0DA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t4Jn9-00000003jLw-1Opy; Fri, 25 Oct 2024 12:51:47 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t4JhC-00000003hvt-26h4; Fri, 25 Oct 2024 12:45:39 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=SUoecVArR0gU+CZkZ6/sQs7f+/bMYvuPi352qAGfjU8=; b=leE/B+tSncVQcshx6Lxo6Fuo6X HNkda7++xmyAsjtlvjNLYT/gcWnQxIizATxUVOe+QtAJaN6de7nYMs+BcuQ3ensuyXbjGakLKd1oY Lzta/U3JDgNrtH8elcAKWbfOkDa2FSS/59JKNArQQgQF+SvZIy1K1ZwilJaHCI56gexqIsoxKu7pr MhIga033q60OJnnmF7oc4CiOpy5yVGJsksuIfVYlBivrr6xbAlrRFcAupN3lRy5TSnerC1jW1olk1 h7WvYqNzjnw/Uh4dEW6pycInMvvczUNe/LUYYm7Hvde3DfPP7+/XBo18nDI+y6gLyo4/77noM7G/I YFOD3SAQ==; Received: from smtp-out1.suse.de ([2a07:de40:b251:101:10:150:64:1]) by desiato.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t4Jh8-00000008uP0-1uY6; Fri, 25 Oct 2024 12:45:37 +0000 Received: from imap1.dmz-prg2.suse.org (unknown [10.150.64.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 3A48021D61; Fri, 25 Oct 2024 12:45:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1729860332; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SUoecVArR0gU+CZkZ6/sQs7f+/bMYvuPi352qAGfjU8=; b=0T3C3xrhynYFHGq8r3zXSnwn630N6EvAiTlSknFomGkeO2m9K3kA3x4Qt35nCjKVjYg8g+ +iqMSDWy95CBxb+AzZ2XDxX8aqCyDF2X6KYcwhB3CraBBCCCTFYg6u8B2bmAmUKtroe2EF oRz7YrAhMCxOdmAMrHLMLeG63tti7EU= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1729860332; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SUoecVArR0gU+CZkZ6/sQs7f+/bMYvuPi352qAGfjU8=; b=IwHEbaOu/CLO7XM8Ag39yPoVeOd1s1AkywbRrytJKCos+nQj1XIVMzdzcBlWLY1yq88nYW PQ9AmxL13U4ErQCw== Authentication-Results: smtp-out1.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1729860332; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SUoecVArR0gU+CZkZ6/sQs7f+/bMYvuPi352qAGfjU8=; b=0T3C3xrhynYFHGq8r3zXSnwn630N6EvAiTlSknFomGkeO2m9K3kA3x4Qt35nCjKVjYg8g+ +iqMSDWy95CBxb+AzZ2XDxX8aqCyDF2X6KYcwhB3CraBBCCCTFYg6u8B2bmAmUKtroe2EF oRz7YrAhMCxOdmAMrHLMLeG63tti7EU= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1729860332; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SUoecVArR0gU+CZkZ6/sQs7f+/bMYvuPi352qAGfjU8=; b=IwHEbaOu/CLO7XM8Ag39yPoVeOd1s1AkywbRrytJKCos+nQj1XIVMzdzcBlWLY1yq88nYW PQ9AmxL13U4ErQCw== Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 33CEB136F5; Fri, 25 Oct 2024 12:45:31 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id KB1CCuuSG2fzOAAAD6G6ig (envelope-from ); Fri, 25 Oct 2024 12:45:31 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH v4 04/10] PCI: brcmstb: Reuse config structure Date: Fri, 25 Oct 2024 15:45:09 +0300 Message-ID: <20241025124515.14066-5-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241025124515.14066-1-svarbanov@suse.de> References: <20241025124515.14066-1-svarbanov@suse.de> MIME-Version: 1.0 X-Spamd-Result: default: False [-5.30 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TAGGED_RCPT(0.00)[dt]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCPT_COUNT_TWELVE(0.00)[21]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; FREEMAIL_CC(0.00)[linutronix.de,kernel.org,broadcom.com,gmail.com,google.com,linux.com,pengutronix.de,suse.com,raspberrypi.com,suse.de]; FROM_HAS_DN(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.de:email,suse.de:mid]; RCVD_COUNT_TWO(0.00)[2]; RCVD_TLS_ALL(0.00)[]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; R_RATELIMIT(0.00)[to_ip_from(RL7mwea5a3cdyragbzqhrtit3y)]; FUZZY_BLOCKED(0.00)[rspamd.com]; FREEMAIL_ENVRCPT(0.00)[gmail.com] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241025_134535_734058_ED208A96 X-CRM114-Status: GOOD ( 20.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Instead of copying fields from pcie_cfg_data structure to brcm_pcie reference it directly. Signed-off-by: Stanimir Varbanov Reviewed-by: Florian Fainelil --- v3 -> v4: - no changes. drivers/pci/controller/pcie-brcmstb.c | 70 ++++++++++++--------------- 1 file changed, 31 insertions(+), 39 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 9321280f6edb..12bcc5919924 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -191,11 +191,11 @@ #define SSC_STATUS_PLL_LOCK_MASK 0x800 #define PCIE_BRCM_MAX_MEMC 3 -#define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX]) -#define DATA_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_DATA]) -#define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->reg_offsets[RGR1_SW_INIT_1]) -#define HARD_DEBUG(pcie) ((pcie)->reg_offsets[PCIE_HARD_DEBUG]) -#define INTR2_CPU_BASE(pcie) ((pcie)->reg_offsets[PCIE_INTR2_CPU_BASE]) +#define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX]) +#define DATA_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_DATA]) +#define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->cfg->offsets[RGR1_SW_INIT_1]) +#define HARD_DEBUG(pcie) ((pcie)->cfg->offsets[PCIE_HARD_DEBUG]) +#define INTR2_CPU_BASE(pcie) ((pcie)->cfg->offsets[PCIE_INTR2_CPU_BASE]) /* Rescal registers */ #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700 @@ -276,8 +276,6 @@ struct brcm_pcie { int gen; u64 msi_target_addr; struct brcm_msi *msi; - const int *reg_offsets; - enum pcie_soc_base soc_base; struct reset_control *rescal; struct reset_control *perst_reset; struct reset_control *bridge_reset; @@ -285,17 +283,14 @@ struct brcm_pcie { int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; - int (*perst_set)(struct brcm_pcie *pcie, u32 val); - int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); struct subdev_regulators *sr; bool ep_wakeup_capable; - bool has_phy; - u8 num_inbound_wins; + const struct pcie_cfg_data *cfg; }; static inline bool is_bmips(const struct brcm_pcie *pcie) { - return pcie->soc_base == BCM7435 || pcie->soc_base == BCM7425; + return pcie->cfg->soc_base == BCM7435 || pcie->cfg->soc_base == BCM7425; } /* @@ -855,7 +850,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, * security considerations, and is not implemented in our modern * SoCs. */ - if (pcie->soc_base != BCM7712) + if (pcie->cfg->soc_base != BCM7712) add_inbound_win(b++, &n, 0, 0, 0); resource_list_for_each_entry(entry, &bridge->dma_ranges) { @@ -872,10 +867,10 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, * That being said, each BARs size must still be a power of * two. */ - if (pcie->soc_base == BCM7712) + if (pcie->cfg->soc_base == BCM7712) add_inbound_win(b++, &n, size, cpu_start, pcie_start); - if (n > pcie->num_inbound_wins) + if (n > pcie->cfg->num_inbound_wins) break; } @@ -889,7 +884,7 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, * that enables multiple memory controllers. As such, it can return * now w/o doing special configuration. */ - if (pcie->soc_base == BCM7712) + if (pcie->cfg->soc_base == BCM7712) return n; ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, @@ -1012,7 +1007,7 @@ static void set_inbound_win_registers(struct brcm_pcie *pcie, * 7712: * All of their BARs need to be set. */ - if (pcie->soc_base == BCM7712) { + if (pcie->cfg->soc_base == BCM7712) { /* BUS remap register settings */ reg_offset = brcm_ubus_reg_offset(i); tmp = lower_32_bits(cpu_addr) & ~0xfff; @@ -1036,15 +1031,15 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) int memc, ret; /* Reset the bridge */ - ret = pcie->bridge_sw_init_set(pcie, 1); + ret = pcie->cfg->bridge_sw_init_set(pcie, 1); if (ret) return ret; /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ - if (pcie->soc_base == BCM2711) { - ret = pcie->perst_set(pcie, 1); + if (pcie->cfg->soc_base == BCM2711) { + ret = pcie->cfg->perst_set(pcie, 1); if (ret) { - pcie->bridge_sw_init_set(pcie, 0); + pcie->cfg->bridge_sw_init_set(pcie, 0); return ret; } } @@ -1052,7 +1047,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) usleep_range(100, 200); /* Take the bridge out of reset */ - ret = pcie->bridge_sw_init_set(pcie, 0); + ret = pcie->cfg->bridge_sw_init_set(pcie, 0); if (ret) return ret; @@ -1072,9 +1067,9 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) */ if (is_bmips(pcie)) burst = 0x1; /* 256 bytes */ - else if (pcie->soc_base == BCM2711) + else if (pcie->cfg->soc_base == BCM2711) burst = 0x0; /* 128 bytes */ - else if (pcie->soc_base == BCM7278) + else if (pcie->cfg->soc_base == BCM7278) burst = 0x3; /* 512 bytes */ else burst = 0x2; /* 512 bytes */ @@ -1199,7 +1194,7 @@ static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie) u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */ /* 7712 does not have this (RGR1) timer */ - if (pcie->soc_base == BCM7712) + if (pcie->cfg->soc_base == BCM7712) return; /* Each unit in timeout register is 1/216,000,000 seconds */ @@ -1277,7 +1272,7 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) int ret, i; /* Unassert the fundamental reset */ - ret = pcie->perst_set(pcie, 0); + ret = pcie->cfg->perst_set(pcie, 0); if (ret) return ret; @@ -1463,12 +1458,12 @@ static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) static inline int brcm_phy_start(struct brcm_pcie *pcie) { - return pcie->has_phy ? brcm_phy_cntl(pcie, 1) : 0; + return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 1) : 0; } static inline int brcm_phy_stop(struct brcm_pcie *pcie) { - return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0; + return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 0) : 0; } static int brcm_pcie_turn_off(struct brcm_pcie *pcie) @@ -1479,7 +1474,7 @@ static int brcm_pcie_turn_off(struct brcm_pcie *pcie) if (brcm_pcie_link_up(pcie)) brcm_pcie_enter_l23(pcie); /* Assert fundamental reset */ - ret = pcie->perst_set(pcie, 1); + ret = pcie->cfg->perst_set(pcie, 1); if (ret) return ret; @@ -1582,7 +1577,7 @@ static int brcm_pcie_resume_noirq(struct device *dev) goto err_reset; /* Take bridge out of reset so we can access the SERDES reg */ - pcie->bridge_sw_init_set(pcie, 0); + pcie->cfg->bridge_sw_init_set(pcie, 0); /* SERDES_IDDQ = 0 */ tmp = readl(base + HARD_DEBUG(pcie)); @@ -1803,12 +1798,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) pcie = pci_host_bridge_priv(bridge); pcie->dev = &pdev->dev; pcie->np = np; - pcie->reg_offsets = data->offsets; - pcie->soc_base = data->soc_base; - pcie->perst_set = data->perst_set; - pcie->bridge_sw_init_set = data->bridge_sw_init_set; - pcie->has_phy = data->has_phy; - pcie->num_inbound_wins = data->num_inbound_wins; + pcie->cfg = data; pcie->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pcie->base)) @@ -1843,7 +1833,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) if (ret) return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); - pcie->bridge_sw_init_set(pcie, 0); + pcie->cfg->bridge_sw_init_set(pcie, 0); if (pcie->swinit_reset) { ret = reset_control_assert(pcie->swinit_reset); @@ -1882,7 +1872,8 @@ static int brcm_pcie_probe(struct platform_device *pdev) goto fail; pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); - if (pcie->soc_base == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { + if (pcie->cfg->soc_base == BCM4908 && + pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); ret = -ENODEV; goto fail; @@ -1897,7 +1888,8 @@ static int brcm_pcie_probe(struct platform_device *pdev) } } - bridge->ops = pcie->soc_base == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; + bridge->ops = pcie->cfg->soc_base == BCM7425 ? + &brcm7425_pcie_ops : &brcm_pcie_ops; bridge->sysdata = pcie; platform_set_drvdata(pdev, pcie); From patchwork Fri Oct 25 12:45:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 13850655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E3EDD0C606 for ; Fri, 25 Oct 2024 12:50:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DVN1KgbHwAirdWM8cppFR/8JZmfTesnF2sbo8B7uvXA=; b=KJmFlxZNwjWqexPO8RHlMQNO2U slQKfHkkjJgc+sS4odfrtkOTSvETuLmx3i7AB/YSBx5JP8MS4oTDi9fKyJ22OZb9CDdw60d11SQA2 NOq4FBoMjv8JFS3Q7kWZE7aLt7hEszZ+68otXFbpYZY2f66MNckEEucCk4dLje1TFIofFO0T4vNvY QaQQg1ZpUaczTQ//7W168k3scm48Ewdj4TC5ah2sewlHN3RbsQi/c+mlRO9vlmunSZ+emiTJD4OP6 sZFB2relheDbxR+LzA9nVKla/P2CxWt0zGtCPya19wbWQ2V10yWXr7hLq3r8e48ncwl8JpxQ6N4O6 wGJRtDrQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t4JlQ-00000003j33-0Lt7; Fri, 25 Oct 2024 12:50:00 +0000 Received: from smtp-out1.suse.de ([2a07:de40:b251:101:10:150:64:1]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t4Jh9-00000003hu2-0Ot8; Fri, 25 Oct 2024 12:45:37 +0000 Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 4C1BD21DF5; Fri, 25 Oct 2024 12:45:33 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 49D2113B16; Fri, 25 Oct 2024 12:45:32 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id aKekD+ySG2fzOAAAD6G6ig (envelope-from ); Fri, 25 Oct 2024 12:45:32 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH v4 05/10] PCI: brcmstb: Expand inbound window size up to 64GB Date: Fri, 25 Oct 2024 15:45:10 +0300 Message-ID: <20241025124515.14066-6-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241025124515.14066-1-svarbanov@suse.de> References: <20241025124515.14066-1-svarbanov@suse.de> MIME-Version: 1.0 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[]; TAGGED_RCPT(0.00)[dt]; ASN(0.00)[asn:25478, ipnet:::/0, country:RU] X-Rspamd-Queue-Id: 4C1BD21DF5 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241025_054535_401729_22195E2E X-CRM114-Status: GOOD ( 12.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org BCM2712 memory map can support up to 64GB of system memory, thus expand the inbound window size in calculation helper function. The change is save for the currently supported SoCs that has smaller inbound window sizes. Signed-off-by: Stanimir Varbanov Reviewed-by: Florian Fainelli --- v3 -> v4: - Improved the subject and description of the patch (Bjorn) drivers/pci/controller/pcie-brcmstb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 12bcc5919924..c01462b07eea 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -304,8 +304,8 @@ static int brcm_pcie_encode_ibar_size(u64 size) if (log2_in >= 12 && log2_in <= 15) /* Covers 4KB to 32KB (inclusive) */ return (log2_in - 12) + 0x1c; - else if (log2_in >= 16 && log2_in <= 35) - /* Covers 64KB to 32GB, (inclusive) */ + else if (log2_in >= 16 && log2_in <= 36) + /* Covers 64KB to 64GB, (inclusive) */ return log2_in - 15; /* Something is awry so disable */ return 0; From patchwork Fri Oct 25 12:45:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 13850659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94CD5D0C608 for ; Fri, 25 Oct 2024 13:01:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ixXM31StPOmPL6wWzhyGTi6JqH2PwF3ZEziNbzNzSWI=; b=mkRerTHrxJV90ykjclXXY3OUon 1hS9mPdfJU5gv1YZpzATShPl3IKmgKYl5PW7Q+DlGJWkbkFxHOns9Lk4GQhZWYINIZBvStCVp25in 2xNtizEUmihu4796HBJbWxF/Icem/Jwg3hBw2O1v2Ga4QX4Poa09BWX6DA03oxRSO5PUYGVCPAhaS gDpZnU8u14woQ/e1ckshMJpjaB2GeJb8qGHbaIkJiFFU1+fXmq/14KF2ny953P5TA05A/v/bSr81a x2ErzOIwxHjMsYeOTx/MWQW7qqNbndWT3q7cRSCz0dYo2iN9pB96F5w0O2iMUm/hUqbJ/U6UafSZn 3GXoUybg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t4JwO-00000003kS9-0SHp; Fri, 25 Oct 2024 13:01:20 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t4JhC-00000003hvy-29DW; Fri, 25 Oct 2024 12:45:39 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=ixXM31StPOmPL6wWzhyGTi6JqH2PwF3ZEziNbzNzSWI=; b=IKyKu92d4lUJ7nUmonje2IV/RU K2vGIDz3JojuFuJzSozX++HVZCejMp+Q8pWiHTUGvM28Z4n6r1ZbTML/ZyWm57p8trYWe7BlxiclL SUDrQiXT0e+j5CG2IQ8liyxXdUZKelX6QEWB++Sil474n4Iu2Ja9mM3zB5gmqEI9YEuuui1UXnVmR rCoTgc1DiHtXab3G7K0gFZIwo9H9pDoAGGzC+6l73V0KbHdb7PUwtaI/YukqtMlNP880C3j70RWz6 zkBA8x5ZY0lVKAp2RHAV5SXkHWosS4rpJWFXVBLvaP7rGcny/LoPTxTkCRRv3LwfW9rNuDX/m2Z0W BCDO3NmA==; Received: from smtp-out1.suse.de ([2a07:de40:b251:101:10:150:64:1]) by desiato.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t4Jh9-00000008uPJ-2vzO; Fri, 25 Oct 2024 12:45:37 +0000 Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 6DD9021D74; Fri, 25 Oct 2024 12:45:34 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 5A04E136F5; Fri, 25 Oct 2024 12:45:33 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id 6MGSE+2SG2fzOAAAD6G6ig (envelope-from ); Fri, 25 Oct 2024 12:45:33 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH v4 06/10] PCI: brcmstb: Enable external MSI-X if available Date: Fri, 25 Oct 2024 15:45:11 +0300 Message-ID: <20241025124515.14066-7-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241025124515.14066-1-svarbanov@suse.de> References: <20241025124515.14066-1-svarbanov@suse.de> MIME-Version: 1.0 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[]; TAGGED_RCPT(0.00)[dt]; ASN(0.00)[asn:25478, ipnet:::/0, country:RU] X-Rspamd-Queue-Id: 6DD9021D74 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241025_134535_921549_902BD2D3 X-CRM114-Status: GOOD ( 13.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On RPi5 there is an external MIP MSI-X interrupt controller which can handle up to 64 interrupts. Signed-off-by: Stanimir Varbanov --- v3 -> v4: - no changes. drivers/pci/controller/pcie-brcmstb.c | 63 +++++++++++++++++++++++++-- 1 file changed, 59 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index c01462b07eea..af01a7915c94 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1318,6 +1318,52 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) return 0; } +static int brcm_pcie_enable_external_msix(struct brcm_pcie *pcie, + struct device_node *msi_np) +{ + struct inbound_win inbound_wins[PCIE_BRCM_MAX_INBOUND_WINS]; + u64 msi_pci_addr, msi_phys_addr; + struct resource r; + int mip_bar, ret; + u32 val, reg; + + ret = of_property_read_reg(msi_np, 1, &msi_pci_addr, NULL); + if (ret) + return ret; + + ret = of_address_to_resource(msi_np, 0, &r); + if (ret) + return ret; + + msi_phys_addr = r.start; + + /* Find free inbound window for MIP access */ + mip_bar = brcm_pcie_get_inbound_wins(pcie, inbound_wins); + if (mip_bar < 0) + return mip_bar; + + mip_bar += 1; + reg = brcm_bar_reg_offset(mip_bar); + + val = lower_32_bits(msi_pci_addr); + val |= brcm_pcie_encode_ibar_size(SZ_4K); + writel(val, pcie->base + reg); + + val = upper_32_bits(msi_pci_addr); + writel(val, pcie->base + reg + 4); + + reg = brcm_ubus_reg_offset(mip_bar); + + val = lower_32_bits(msi_phys_addr); + val |= PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK; + writel(val, pcie->base + reg); + + val = upper_32_bits(msi_phys_addr); + writel(val, pcie->base + reg + 4); + + return 0; +} + static const char * const supplies[] = { "vpcie3v3", "vpcie3v3aux", @@ -1879,11 +1925,20 @@ static int brcm_pcie_probe(struct platform_device *pdev) goto fail; } - msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); - if (pci_msi_enabled() && msi_np == pcie->np) { - ret = brcm_pcie_enable_msi(pcie); + if (pci_msi_enabled()) { + msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); + const char *str; + + if (msi_np == pcie->np) { + str = "internal MSI"; + ret = brcm_pcie_enable_msi(pcie); + } else { + str = "external MSI-X"; + ret = brcm_pcie_enable_external_msix(pcie, msi_np); + } + if (ret) { - dev_err(pcie->dev, "probe of internal MSI failed"); + dev_err(pcie->dev, "enable of %s failed\n", str); goto fail; } } From patchwork Fri Oct 25 12:45:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 13850662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 93B1BD0C608 for ; Fri, 25 Oct 2024 13:04:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Asyrs79reDImQyOzbVRw7HVB5RRZuAAIIzsrop58QWE=; b=ifVcR7eV0cij6frgZs6EFM7ZCn H+Wuhi0a/f7u+i1gsbVrf5FP15OD/Euqm4vGEWqNDDrtBUQxHXfi1tN0Dc++/LLAHhIUKTFOjicG6 6zG369d4+d0mPBTL6NXN0lMf6YAgUHVaH3Q7mJBY1SvdXI3mPpEUZ4zJpSAjQZiRLfUUr1GebbYq/ HXMWxLu7ENNXU/huR6aoUhu3nod4kmSY8zyuo2DE8cobMRpLP09/OSUgWbimTxFgeFc2lEqkcbG4J 21uGF97J2IDr464pZmtTfPKZFJ5Oy2Lg8mzH/MLjHnZ0r9rDGT+KaXMV3okK1duBzmISxFJkzmOOJ ykgQw7FQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t4Jyz-00000003kih-053H; Fri, 25 Oct 2024 13:04:01 +0000 Received: from smtp-out2.suse.de ([2a07:de40:b251:101:10:150:64:2]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t4JhB-00000003hv1-04lF; Fri, 25 Oct 2024 12:45:41 +0000 Received: from imap1.dmz-prg2.suse.org (unknown [10.150.64.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 911CD1FE16; Fri, 25 Oct 2024 12:45:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1729860335; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Asyrs79reDImQyOzbVRw7HVB5RRZuAAIIzsrop58QWE=; b=kWjJiNl1knw4BzVcDUgzsWbZCahyr/DeYk4rdLtkjEKNcBkWQa8bb0ssG07wIKT12T8mKk hfS6yaYpy1xgfiZOQsWFy0+5sao/JKybpepCNm96W96YgMKfAFEzW1LmUaP/Ho2Gew3Stj 8foBXxKU9EzsG40ApbnGNIWezqTTXhU= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1729860335; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Asyrs79reDImQyOzbVRw7HVB5RRZuAAIIzsrop58QWE=; b=q9qIxlQc6E94azrWokO3eBcp7oK8P5WRy9MfojL2I3OyhPC9lYViF34Oe/FnvH3gr9BDXH BdaqR4/li2ZFbWCw== Authentication-Results: smtp-out2.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1729860335; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Asyrs79reDImQyOzbVRw7HVB5RRZuAAIIzsrop58QWE=; b=kWjJiNl1knw4BzVcDUgzsWbZCahyr/DeYk4rdLtkjEKNcBkWQa8bb0ssG07wIKT12T8mKk hfS6yaYpy1xgfiZOQsWFy0+5sao/JKybpepCNm96W96YgMKfAFEzW1LmUaP/Ho2Gew3Stj 8foBXxKU9EzsG40ApbnGNIWezqTTXhU= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1729860335; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Asyrs79reDImQyOzbVRw7HVB5RRZuAAIIzsrop58QWE=; b=q9qIxlQc6E94azrWokO3eBcp7oK8P5WRy9MfojL2I3OyhPC9lYViF34Oe/FnvH3gr9BDXH BdaqR4/li2ZFbWCw== Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 7E867136F5; Fri, 25 Oct 2024 12:45:34 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id cPeAHO6SG2fzOAAAD6G6ig (envelope-from ); Fri, 25 Oct 2024 12:45:34 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH v4 07/10] PCI: brcmstb: Add bcm2712 support Date: Fri, 25 Oct 2024 15:45:12 +0300 Message-ID: <20241025124515.14066-8-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241025124515.14066-1-svarbanov@suse.de> References: <20241025124515.14066-1-svarbanov@suse.de> MIME-Version: 1.0 X-Spamd-Result: default: False [-5.30 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TAGGED_RCPT(0.00)[dt]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCPT_COUNT_TWELVE(0.00)[21]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; FREEMAIL_CC(0.00)[linutronix.de,kernel.org,broadcom.com,gmail.com,google.com,linux.com,pengutronix.de,suse.com,raspberrypi.com,suse.de]; FROM_HAS_DN(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.de:email,suse.de:mid,imap1.dmz-prg2.suse.org:helo]; RCVD_COUNT_TWO(0.00)[2]; RCVD_TLS_ALL(0.00)[]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; R_RATELIMIT(0.00)[to_ip_from(RL7mwea5a3cdyragbzqhrtit3y)]; FUZZY_BLOCKED(0.00)[rspamd.com]; FREEMAIL_ENVRCPT(0.00)[gmail.com] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241025_054537_361995_3A5BF048 X-CRM114-Status: GOOD ( 17.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add bare minimum amount of changes in order to support PCIe RC hardware IP found on RPi5. The PCIe controller on bcm2712 is based on bcm7712 and as such it inherits register offsets, perst, bridge_reset ops and inbound windows count. Although, the implementation for bcm2712 needs a workaround related to the control of the bridge_reset where turning off of the root port must not shutdown the bridge_reset and this must be avoided. To implement this workaround a quirks field is introduced in pcie_cfg_data struct. Signed-off-by: Stanimir Varbanov Reviewed-by: Florian Fainelli --- v3 -> v4: - Merged "PCI: brcmstb: Avoid turn off of bridge reset" from v3 here in this patch (Bjorn) drivers/pci/controller/pcie-brcmstb.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index af01a7915c94..d970a76aa9ef 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -234,10 +234,20 @@ struct inbound_win { u64 cpu_addr; }; +/* + * The RESCAL block is tied to PCIe controller #1, regardless of the number of + * controllers, and turning off PCIe controller #1 prevents access to the RESCAL + * register blocks, therefore no other controller can access this register + * space, and depending upon the bus fabric we may get a timeout (UBUS/GISB), + * or a hang (AXI). + */ +#define CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN BIT(0) + struct pcie_cfg_data { const int *offsets; const enum pcie_soc_base soc_base; const bool has_phy; + const u32 quirks; u8 num_inbound_wins; int (*perst_set)(struct brcm_pcie *pcie, u32 val); int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); @@ -1534,8 +1544,9 @@ static int brcm_pcie_turn_off(struct brcm_pcie *pcie) u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); writel(tmp, base + HARD_DEBUG(pcie)); - /* Shutdown PCIe bridge */ - ret = pcie->bridge_sw_init_set(pcie, 1); + if (!(pcie->cfg->quirks & CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN)) + /* Shutdown PCIe bridge */ + ret = pcie->cfg->bridge_sw_init_set(pcie, 1); return ret; } @@ -1745,6 +1756,15 @@ static const struct pcie_cfg_data bcm2711_cfg = { .num_inbound_wins = 3, }; +static const struct pcie_cfg_data bcm2712_cfg = { + .offsets = pcie_offsets_bcm7712, + .soc_base = BCM7712, + .perst_set = brcm_pcie_perst_set_7278, + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, + .quirks = CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN, + .num_inbound_wins = 10, +}; + static const struct pcie_cfg_data bcm4908_cfg = { .offsets = pcie_offsets, .soc_base = BCM4908, @@ -1796,6 +1816,7 @@ static const struct pcie_cfg_data bcm7712_cfg = { static const struct of_device_id brcm_pcie_match[] = { { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg }, + { .compatible = "brcm,bcm2712-pcie", .data = &bcm2712_cfg }, { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg }, { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg }, { .compatible = "brcm,bcm7216-pcie", .data = &bcm7216_cfg }, From patchwork Fri Oct 25 12:45:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 13850665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB3EFD0C609 for ; Fri, 25 Oct 2024 13:08:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=r16IVaWb/8WBkg1rKMR8vmVZEwzTIfOMUqMamTYZcpY=; b=uR2zaos9mZjM9TxVjXQ5vRH+eK /55NrlZVzeV7hLA/yuE2dGnyAme0tgGdjxIg3QSWqqJbPhy6srU4UW26WH749VK+oDd2p15ZdkPyd 2J0tKxUfITPUJ1ldbqs0UrdxzE3F/qBHj9xsUkljYSCu7zR6cd7bugWX1GCZUIBx+gF9cHSzNuYYK IkZyfnvg0Iuf6qbBf4/yMitC/vRrIZ63PRpbVVpSOnO3KofGBkYiebtK5SwXFleEblbHYPUeC7o3p PRFBTbfXxa/ALkXMFlNuk5vIKnFxzxLyJJVcuwXjPjPDMiCBPZEc5AcQG/7bTanRAW/DKbEzgHdJz mrQrbo0g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t4K3b-00000003lXn-192G; Fri, 25 Oct 2024 13:08:47 +0000 Received: from smtp-out2.suse.de ([195.135.223.131]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t4JhC-00000003hvM-1B0S; Fri, 25 Oct 2024 12:45:44 +0000 Received: from imap1.dmz-prg2.suse.org (unknown [10.150.64.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id A13381FE09; Fri, 25 Oct 2024 12:45:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1729860336; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=r16IVaWb/8WBkg1rKMR8vmVZEwzTIfOMUqMamTYZcpY=; b=xvU6Y2CghydzR8SpDr2X4VFFRRxeUQHHV+8XwQyNDfgBpommZ8yvNeqgn993PVSoicBnPU iLt/5kEFS4+cn3V4FAsobzRHDVDq/adKoIoxmUkAyrwQOCpsSX3wuUtZHS2yR3iINenbKO bGIkfeaRZAuGjh8fiRpod+xybAIy3Ao= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1729860336; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=r16IVaWb/8WBkg1rKMR8vmVZEwzTIfOMUqMamTYZcpY=; b=qYg9xfDj6oRM9FpHFer3XVH+abc6DMMoxCsN+pdC4jlKg9rhZk4hYxFJ2YTTn9woWa/j+v 2JBXX1/v0PDqa+CA== Authentication-Results: smtp-out2.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1729860336; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=r16IVaWb/8WBkg1rKMR8vmVZEwzTIfOMUqMamTYZcpY=; b=xvU6Y2CghydzR8SpDr2X4VFFRRxeUQHHV+8XwQyNDfgBpommZ8yvNeqgn993PVSoicBnPU iLt/5kEFS4+cn3V4FAsobzRHDVDq/adKoIoxmUkAyrwQOCpsSX3wuUtZHS2yR3iINenbKO bGIkfeaRZAuGjh8fiRpod+xybAIy3Ao= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1729860336; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=r16IVaWb/8WBkg1rKMR8vmVZEwzTIfOMUqMamTYZcpY=; b=qYg9xfDj6oRM9FpHFer3XVH+abc6DMMoxCsN+pdC4jlKg9rhZk4hYxFJ2YTTn9woWa/j+v 2JBXX1/v0PDqa+CA== Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id A0E7013B16; Fri, 25 Oct 2024 12:45:35 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id 8CLmJO+SG2fzOAAAD6G6ig (envelope-from ); Fri, 25 Oct 2024 12:45:35 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH v4 08/10] PCI: brcmstb: Adjust PHY PLL setup to use a 54MHz input refclk Date: Fri, 25 Oct 2024 15:45:13 +0300 Message-ID: <20241025124515.14066-9-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241025124515.14066-1-svarbanov@suse.de> References: <20241025124515.14066-1-svarbanov@suse.de> MIME-Version: 1.0 X-Spamd-Result: default: False [-5.30 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FREEMAIL_CC(0.00)[linutronix.de,kernel.org,broadcom.com,gmail.com,google.com,linux.com,pengutronix.de,suse.com,raspberrypi.com,suse.de]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCPT_COUNT_TWELVE(0.00)[21]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCVD_TLS_ALL(0.00)[]; TAGGED_RCPT(0.00)[dt]; FROM_EQ_ENVFROM(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.de:email,suse.de:mid]; FROM_HAS_DN(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; R_RATELIMIT(0.00)[to_ip_from(RL7mwea5a3cdyragbzqhrtit3y)]; FUZZY_BLOCKED(0.00)[rspamd.com]; FREEMAIL_ENVRCPT(0.00)[gmail.com] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241025_054538_526722_5E08C3DA X-CRM114-Status: GOOD ( 15.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The default input reference clock for the PHY PLL is 100Mhz, except for some devices where it is 54Mhz like bcm2712C1 and bcm2712D0. To implement this adjustments introduce a new .post_setup op in pcie_cfg_data and call it at the end of brcm_pcie_setup function. The bcm2712 .post_setup callback implements the required MDIO writes that switch the PLL refclk and also change PHY PM clock period. Without this RPi5 PCIex1 is unable to enumerate endpoint devices on the expansion connector. Signed-off-by: Stanimir Varbanov Reviewed-by: Florian Fainelli --- v3 -> v4: - Improved patch description (Florian) drivers/pci/controller/pcie-brcmstb.c | 42 +++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index d970a76aa9ef..2571dcc14560 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -55,6 +55,10 @@ #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 +#define PCIE_RC_PL_PHY_CTL_15 0x184c +#define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK 0x400000 +#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff + #define PCIE_MISC_MISC_CTRL 0x4008 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400 @@ -251,6 +255,7 @@ struct pcie_cfg_data { u8 num_inbound_wins; int (*perst_set)(struct brcm_pcie *pcie, u32 val); int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); + int (*post_setup)(struct brcm_pcie *pcie); }; struct subdev_regulators { @@ -826,6 +831,36 @@ static int brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) return 0; } +static int brcm_pcie_post_setup_bcm2712(struct brcm_pcie *pcie) +{ + const u16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, 0x5030, 0x0007 }; + const u8 regs[] = { 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e }; + int ret, i; + u32 tmp; + + /* Allow a 54MHz (xosc) refclk source */ + ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, 0x1600); + if (ret < 0) + return ret; + + for (i = 0; i < ARRAY_SIZE(regs); i++) { + ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]); + if (ret < 0) + return ret; + } + + usleep_range(100, 200); + + /* Fix for L1SS errata */ + tmp = readl(pcie->base + PCIE_RC_PL_PHY_CTL_15); + tmp &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK; + /* PM clock period is 18.52ns (round down) */ + tmp |= 0x12; + writel(tmp, pcie->base + PCIE_RC_PL_PHY_CTL_15); + + return 0; +} + static void add_inbound_win(struct inbound_win *b, u8 *count, u64 size, u64 cpu_addr, u64 pci_offset) { @@ -1189,6 +1224,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK); writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1); + if (pcie->cfg->post_setup) { + ret = pcie->cfg->post_setup(pcie); + if (ret < 0) + return ret; + } + return 0; } @@ -1761,6 +1802,7 @@ static const struct pcie_cfg_data bcm2712_cfg = { .soc_base = BCM7712, .perst_set = brcm_pcie_perst_set_7278, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, + .post_setup = brcm_pcie_post_setup_bcm2712, .quirks = CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN, .num_inbound_wins = 10, }; From patchwork Fri Oct 25 12:45:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 13850664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 271D7D0C609 for ; Fri, 25 Oct 2024 13:07:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=cPYiM/+5rf2FfDXB9bFp6VTaU1OVtVUZPNeAcuiYuOQ=; b=Y5HKjDVpmPV5AOhgu2T/NuTC8f g0xHEERO0GU4//o0MozhPN9r04yR2+1m/gpryQCtvtu5Kvb+h2V/UYF0nHYmRSaPVj7rZOfqI1Shl FTFaJi1SDhzm0lP2D8Wg7/MhqXMt+R5DpJu6lHJe4XRQeAXt07DNY87s05Nw46YUbZOX4/6cGzO9f kGtHW79ITH8Ju/1U56XN5m+xVAyqOaYLh6Bcz0Udb75m93AkmRXaR1rXwPn4T9ZTGUhC7pbJzuu7T EGN9YdKkX8nD69lNzmkbRWsnEWcqFfoPHCE2c+ooTWdWUAlcMFysR7GJP0k3kmj/3oNl/oPbsoXO6 ohgaaHfA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t4K24-00000003lJ2-1qMH; Fri, 25 Oct 2024 13:07:12 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t4JhG-00000003hxQ-3x8K; Fri, 25 Oct 2024 12:45:43 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=cPYiM/+5rf2FfDXB9bFp6VTaU1OVtVUZPNeAcuiYuOQ=; b=Ttv+BC4841ekt4+QKLZC+Xepd7 f5oJ/pa8I9uK2dGCAya5dsWZjs1RuNBH7kpgQuncfpiUQul56kZwKY4uCdRJ+adfNnOra6CCbn1yF i/k1XUXNvxkYGXRno2Uaib+MqBUHClNW5DMvMk4VxKNgbwpu/8AU6dFQe6R3bSD+hzyn54m/LTD2y v9g0TMblTnuTByCzKp4H57faZKAAKvvFE9nvbNxJYmvLDbuxxtz+Z0j5iFQBItUoO2zJ2ol7wDlqd GsD5jqirx3FbIs95R+jS2nkJ3TsLxLVXRKq/BmmkwCGTEAjZD4v36sKKFujBMEvvzFY3B2V6hizl1 CgY0c1VA==; Received: from smtp-out2.suse.de ([2a07:de40:b251:101:10:150:64:2]) by desiato.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t4JhD-00000008uQO-3GMc; Fri, 25 Oct 2024 12:45:41 +0000 Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id CA5401FE0E; Fri, 25 Oct 2024 12:45:37 +0000 (UTC) Authentication-Results: smtp-out2.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id B117F136F5; Fri, 25 Oct 2024 12:45:36 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id sJm1KPCSG2fzOAAAD6G6ig (envelope-from ); Fri, 25 Oct 2024 12:45:36 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH v4 09/10] arm64: dts: broadcom: bcm2712: Add PCIe DT nodes Date: Fri, 25 Oct 2024 15:45:14 +0300 Message-ID: <20241025124515.14066-10-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241025124515.14066-1-svarbanov@suse.de> References: <20241025124515.14066-1-svarbanov@suse.de> MIME-Version: 1.0 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[]; TAGGED_RCPT(0.00)[dt]; ASN(0.00)[asn:25478, ipnet:::/0, country:RU] X-Rspamd-Queue-Id: CA5401FE0E X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241025_134540_119070_BE7C87D0 X-CRM114-Status: UNSURE ( 9.24 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add PCIe devicetree nodes, plus needed reset and mip MSI-X controllers. Signed-off-by: Stanimir Varbanov --- v3 -> v4: - Added msi-controller property required by brcm,stb-pcie.yaml schema arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 162 ++++++++++++++++++++++ 1 file changed, 162 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 6e5a984c1d4e..8fcdf27c1221 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -192,6 +192,12 @@ soc: soc@107c000000 { #address-cells = <1>; #size-cells = <1>; + pcie_rescal: reset-controller@119500 { + compatible = "brcm,bcm7216-pcie-sata-rescal"; + reg = <0x00119500 0x10>; + #reset-cells = <0>; + }; + sdio1: mmc@fff000 { compatible = "brcm,bcm2712-sdhci", "brcm,sdhci-brcmstb"; @@ -204,6 +210,12 @@ sdio1: mmc@fff000 { mmc-ddr-3_3v; }; + bcm_reset: reset-controller@1504318 { + compatible = "brcm,brcmstb-reset"; + reg = <0x01504318 0x30>; + #reset-cells = <1>; + }; + system_timer: timer@7c003000 { compatible = "brcm,bcm2835-system-timer"; reg = <0x7c003000 0x1000>; @@ -267,6 +279,156 @@ gicv2: interrupt-controller@7fff9000 { }; }; + axi@1000000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x00 0x00000000 0x10 0x00000000 0x01 0x00000000>, + <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, + <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, + <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; + + dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, + <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, + <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, + <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; + + pcie0: pcie@100000 { + compatible = "brcm,bcm2712-pcie"; + reg = <0x00 0x00100000 0x00 0x9310>; + device_type = "pci"; + linux,pci-domain = <0>; + max-link-speed = <2>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + interrupt-parent = <&gicv2>; + interrupts = , + ; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + resets = <&bcm_reset 42>, <&pcie_rescal>; + reset-names = "bridge", "rescal"; + msi-controller; + msi-parent = <&pcie0>; + + ranges = + /* ~4GB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ + <0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>, + /* 12GB, 64-bit, prefetchable at PCIe 04_0000_0000 */ + <0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>; + + dma-ranges = + /* 64GB, 64-bit, prefetchable at PCIe 10_0000_0000 */ + <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>; + + status = "disabled"; + }; + + pcie1: pcie@110000 { + compatible = "brcm,bcm2712-pcie"; + reg = <0x00 0x00110000 0x00 0x9310>; + device_type = "pci"; + linux,pci-domain = <1>; + max-link-speed = <2>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + interrupt-parent = <&gicv2>; + interrupts = , + ; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + resets = <&bcm_reset 43>, <&pcie_rescal>; + reset-names = "bridge", "rescal"; + msi-controller; + msi-parent = <&mip1>; + + ranges = + /* ~4GB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ + <0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>, + /* 12GB, 64-bit, prefetchable at PCIe 04_0000_0000 */ + <0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>; + + dma-ranges = + /* 64GB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */ + <0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>; + + status = "disabled"; + }; + + pcie2: pcie@120000 { + compatible = "brcm,bcm2712-pcie"; + reg = <0x00 0x00120000 0x00 0x9310>; + device_type = "pci"; + linux,pci-domain = <2>; + max-link-speed = <2>; + bus-range = <0x00 0xff>; + num-lanes = <4>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + interrupt-parent = <&gicv2>; + interrupts = , + ; + interrupt-names = "pcie", "msi"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + resets = <&bcm_reset 44>, <&pcie_rescal>; + reset-names = "bridge", "rescal"; + msi-controller; + msi-parent = <&mip0>; + + ranges = + /* ~4GB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ + <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>, + /* 12GB, 64-bit, prefetchable at PCIe 04_0000_0000 */ + <0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>; + + dma-ranges = + /* 4MB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */ + <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>, + /* 64GB, 64-bit, prefetchable at PCIe 10_0000_0000 */ + <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>; + + status = "disabled"; + }; + + mip0: msi-controller@130000 { + compatible = "brcm,bcm2712-mip"; + reg = <0x00 0x00130000 0x00 0xc0>, + <0xff 0xfffff000 0x00 0x1000>; + msi-controller; + msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>; + brcm,msi-offset = <0>; + }; + + mip1: msi-controller@131000 { + compatible = "brcm,bcm2712-mip"; + reg = <0x00 0x00131000 0x00 0xc0>, + <0xff 0xfffff000 0x00 0x1000>; + msi-controller; + msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>; + brcm,msi-offset = <8>; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = X-Patchwork-Id: 13850663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72627D0C608 for ; Fri, 25 Oct 2024 13:05:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=puxdRXFYuInUQU6g76BScKsZQb6nOGEMLTN1grk7qd8=; b=vmOnKWgpFd3jZ/R2/PpYLkL8v2 LrC8xk3X0TwNSU2qT5gqTiaK1kEC1gIWqE2JcjXl1fkKa5IEuVnlTK57flg9V/hJCIwVgjAKIgx1Y gJfnH4seKg9qTUO0ry33oC4zb+DGEekoZBsOaNN9xS/gnjaWeL6JiuerYUYdcI/lqGc7YXmU6NqTT vM3XzPbU8qMjI7ykSRpXpEGDVLwWUvhrUSxdeWdTp7tGe4LosmVfcwwjpu9G8zmMs0vGLFzB8jGEw BCfaB8EY5WAcwoa2yA37GKDkOREK6X4d6W5tFCobDzgGw6tTxXxeLcpOtxUVkHF1Y8eC+ACi0rsNq F/N/EYEg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t4K0W-00000003l2w-18U2; Fri, 25 Oct 2024 13:05:36 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t4JhG-00000003hxN-2s5P; Fri, 25 Oct 2024 12:45:42 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=puxdRXFYuInUQU6g76BScKsZQb6nOGEMLTN1grk7qd8=; b=VbWMbylvcuqLsBznJOS5rF3JtW 7NoG1+aDg2rZM1N1FYgmfkH7ABofqYYIUi4aaWoQVnLdmJH/QZol0boRIL1TkhdZqVj82RdykiXei zNFkJSVAEsmdJcV9uRY6xc0RczFS7ERnx09OZ3rkqw4REHTyYCdDsYGH7iZLNxNWqD6BNBFnod9g5 UYlOiajBiLCGYyOg5r4QIx1td4OZWv/eGdDgSo53/KazimUvgZhIMwEf7tYLGGxvKQNZE3Np6q2qP 85bF4HM5PTkrgiKiXFxGC0EyvMlss84Lm4G86ZSFyqnSskjOHEgs+uscwo6rJzBsHXh+/ZL9q2h+S JVTEEgug==; Received: from smtp-out2.suse.de ([195.135.223.131]) by desiato.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t4JhD-00000008uQT-3fJp; Fri, 25 Oct 2024 12:45:41 +0000 Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id DB9CE1FE73; Fri, 25 Oct 2024 12:45:38 +0000 (UTC) Authentication-Results: smtp-out2.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id DA837136F5; Fri, 25 Oct 2024 12:45:37 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id oH70MvGSG2fzOAAAD6G6ig (envelope-from ); Fri, 25 Oct 2024 12:45:37 +0000 From: Stanimir Varbanov To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell , Stanimir Varbanov Subject: [PATCH v4 10/10] arm64: dts: broadcom: bcm2712-rpi-5-b: Enable PCIe DT nodes Date: Fri, 25 Oct 2024 15:45:15 +0300 Message-ID: <20241025124515.14066-11-svarbanov@suse.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241025124515.14066-1-svarbanov@suse.de> References: <20241025124515.14066-1-svarbanov@suse.de> MIME-Version: 1.0 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[]; TAGGED_RCPT(0.00)[dt]; ASN(0.00)[asn:25478, ipnet:::/0, country:RU] X-Rspamd-Queue-Id: DB9CE1FE73 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241025_134540_056535_DB90D139 X-CRM114-Status: UNSURE ( 8.70 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable pcie1 and pcie2 DT nodes. Pcie1 is used for the extension connector and pcie2 is used for RP1 south-bridge. Signed-off-by: Stanimir Varbanov --- v3 -> v4: - no changes. arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts index 2bdbb6780242..e970a6013c6f 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -62,3 +62,11 @@ &sdio1 { sd-uhs-ddr50; sd-uhs-sdr104; }; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +};