From patchwork Fri Oct 25 16:02:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13850991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B19D9D1039E for ; Fri, 25 Oct 2024 16:02:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3908B10EB0B; Fri, 25 Oct 2024 16:02:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Anv8yZ/o"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 358FA10EB08 for ; Fri, 25 Oct 2024 16:02:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729872149; x=1761408149; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OvkyWEBcP7FDFcLe6rbtSO07Dpr9muyb4loIDlQCFd0=; b=Anv8yZ/oL1XeoRE19RXFOadRjW8Ijx7MjTUgy56xqgKbVcE8saopjyNi DCjyMgZwHpa44Lz1tpmc1yoONw5gp/n92tBAzp5nZUMKxXgyjGfGJgWbg FfBA8NfJlnnFH0QYIPu8RptCWeKJBvi9r4iyE7H+o8o1ZimLDMluD0krK hCxFzr7G8pi39IucMFNq3YJlZyKy6q0DjvN0Vw1dVq0icG480yc1ZkZRU LiVs7XEKxKzv5kelgKxrThmWFw6QA2xK2w3+ssKFK2INFcym6bNz9Hw2W /cI/AdsF4N/uleZ4KosvnI60aIyguChJEuLVHmHPNcAV0SEvhFkEJJeBX g==; X-CSE-ConnectionGUID: 9rO05AuGRZSJzjZoKW07KQ== X-CSE-MsgGUID: m0lWqDiTTEWjxQU9gW9/CA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="33242378" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="33242378" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:02:29 -0700 X-CSE-ConnectionGUID: DdaCsyFnRjOi/euYR1xEfA== X-CSE-MsgGUID: AHi67aNlSzO4hPFTmKAT4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81783694" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:02:28 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= Subject: [PATCH v5 1/8] drm/i915/dp: Flush modeset commits during connector detection Date: Fri, 25 Oct 2024 19:02:52 +0300 Message-ID: <20241025160259.3088727-2-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241025160259.3088727-1-imre.deak@intel.com> References: <20241025160259.3088727-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Make sure that a DP connector detection doesn't happen in parallel with an ongoing modeset on the connector. The reasons for this are: - Besides reading the capabilities, EDID etc. the detection may change the state of the sink (via the AUX bus), for instance by setting the LTTPR mode or the source OUI (the latter introduced by an upcoming patch). It's better to avoid such changes affecting an onging modeset in any way. - During a modeset's link training any access to DPCD registers, besides the registers used for link training should be avoided, at least in the LTTPR non-transparent and transparent link training modes. Such asynchronous accesses - besides connector detection - can also happen via the AUX device node for instance, for those a parallel modeset will have to be avoided in a similar way to the change in this patch. (A topic for a follow-up change.) - The source OUI written to an eDP sink is valid only while the panel power is enabled. A modeset on eDP will enable/disable the panel power synchronously; this should be prevented in the middle of the connector detection, to ensure a consistent sink state (which depends on the source OUI) for the whole duration of detection. The panel power could still get disabled during detection after an idle period (1 sec), this will be prevented by the next patch. v2: (Ville) - s/wait_for_crtc_hw_done/wait_for_connector_hw_done - Get drm_device using an intel_display instead of drm_i915_private ptr. Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 27 ++++++++++++++++++--- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ 3 files changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7e29619ba0400..d2019c9ef8e91 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5036,6 +5036,21 @@ bool intel_dp_has_connector(struct intel_dp *intel_dp, return false; } +static void wait_for_connector_hw_done(const struct drm_connector_state *conn_state) +{ + struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct intel_display *display = to_intel_display(connector); + + drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex); + + if (!conn_state->commit) + return; + + drm_WARN_ON(display->drm, + !wait_for_completion_timeout(&conn_state->commit->hw_done, + msecs_to_jiffies(5000))); +} + int intel_dp_get_active_pipes(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask) @@ -5072,10 +5087,7 @@ int intel_dp_get_active_pipes(struct intel_dp *intel_dp, if (!crtc_state->hw.active) continue; - if (conn_state->commit) - drm_WARN_ON(&i915->drm, - !wait_for_completion_timeout(&conn_state->commit->hw_done, - msecs_to_jiffies(5000))); + wait_for_connector_hw_done(conn_state); *pipe_mask |= BIT(crtc->pipe); } @@ -5084,6 +5096,11 @@ int intel_dp_get_active_pipes(struct intel_dp *intel_dp, return ret; } +void intel_dp_flush_connector_commits(struct intel_connector *connector) +{ + wait_for_connector_hw_done(connector->base.state); +} + static bool intel_dp_is_connected(struct intel_dp *intel_dp) { struct intel_connector *connector = intel_dp->attached_connector; @@ -5597,6 +5614,8 @@ intel_dp_detect(struct drm_connector *connector, if (!intel_display_driver_check_access(dev_priv)) return connector->status; + intel_dp_flush_connector_commits(intel_connector); + /* Can't disconnect eDP */ if (intel_dp_is_edp(intel_dp)) status = edp_detect(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 60baf4072dc9d..4efb9605a50e0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -54,6 +54,7 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp, int intel_dp_get_active_pipes(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask); +void intel_dp_flush_connector_commits(struct intel_connector *connector); void intel_dp_link_check(struct intel_encoder *encoder); void intel_dp_check_link_state(struct intel_dp *intel_dp); void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 1a2ff3e1cb68f..5bba078c00d89 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1573,6 +1573,8 @@ intel_dp_mst_detect(struct drm_connector *connector, if (!intel_display_driver_check_access(i915)) return connector->status; + intel_dp_flush_connector_commits(intel_connector); + return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr, intel_connector->port); } From patchwork Fri Oct 25 16:02:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13850992 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC455D1039A for ; Fri, 25 Oct 2024 16:02:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C5D0410EB0C; Fri, 25 Oct 2024 16:02:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bhEOLFtH"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D0BE10EB0B for ; Fri, 25 Oct 2024 16:02:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729872150; x=1761408150; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sr6zeKmw5mLWnDSchuFvS12ggnYQ9ZYzpmIewI2+D+U=; b=bhEOLFtHwjVxkA+FxG1CPf2rkYdbR9pn3S9/+mtwy8hSck77pqisirkf zHHmt+korhPjrEaYkL3SGD7M24jL7GYTcExobq2ZR7YOnnPH4g8oZHabB 6m4z5XBaAchah/Rff3uIIqst5lBXKGSDrZsSiZ7NahNWKP+jHd7BQbOdS AwB/fV3ujdIfVO14H7qQYu2OtcJ9Q9PlISwUIPgqYngk6svrdfBpqFMTc k0NH5c/pA3YJZWcjTheIP/C8HQY+XwGmB4MM6llJ7DfeQ4/Y1UeAaJlQv khYNDoyp2BQMwIwJVcfrCOqJbR8fFmQZN/ZcsqBhkCwKk9hZRtWOrfA1x g==; X-CSE-ConnectionGUID: xX9GTOcbS5e6C4WIRPltjw== X-CSE-MsgGUID: R+vUnbR+TCex88eVQIucUQ== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="33242382" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="33242382" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:02:30 -0700 X-CSE-ConnectionGUID: 4FcjeEx7Rpa/Ahi8CdZ5Sg== X-CSE-MsgGUID: YqSna30eQYiVi92aoBSoKg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81783697" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:02:29 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Jani Nikula , =?utf-8?b?VmlsbGUgU3lyasOk?= =?utf-8?b?bMOk?= Subject: [PATCH v5 2/8] drm/i915/dp: Ensure panel power remains enabled during connector detection Date: Fri, 25 Oct 2024 19:02:53 +0300 Message-ID: <20241025160259.3088727-3-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241025160259.3088727-1-imre.deak@intel.com> References: <20241025160259.3088727-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The sink's capabilities, like the DSC caps, depend on the source OUI written to the sink's DPCD registers and so this OUI value should be valid for the whole duration of the detection. An eDP sink will reset this OUI value when the panel power is disabled, so prevent the disabling - happening by default after a 1 sec idle period - for the whole duration of detection. v2: Update the documentation for intel_pps_on(). (Jani) Cc: Jani Nikula Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++++++----- drivers/gpu/drm/i915/display/intel_pps.c | 14 +++++++++++++- drivers/gpu/drm/i915/display/intel_pps.h | 1 + 3 files changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d2019c9ef8e91..69a4e9c86d386 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5616,6 +5616,8 @@ intel_dp_detect(struct drm_connector *connector, intel_dp_flush_connector_commits(intel_connector); + intel_pps_vdd_on(intel_dp); + /* Can't disconnect eDP */ if (intel_dp_is_edp(intel_dp)) status = edp_detect(intel_dp); @@ -5646,12 +5648,15 @@ intel_dp_detect(struct drm_connector *connector, intel_dp_tunnel_disconnect(intel_dp); - goto out; + goto out_unset_edid; } ret = intel_dp_tunnel_detect(intel_dp, ctx); - if (ret == -EDEADLK) - return ret; + if (ret == -EDEADLK) { + status = ret; + + goto out_vdd_off; + } if (ret == 1) intel_connector->base.epoch_counter++; @@ -5679,7 +5684,7 @@ intel_dp_detect(struct drm_connector *connector, * with EDID on it */ status = connector_status_disconnected; - goto out; + goto out_unset_edid; } /* @@ -5708,7 +5713,7 @@ intel_dp_detect(struct drm_connector *connector, intel_dp_check_device_service_irq(intel_dp); -out: +out_unset_edid: if (status != connector_status_connected && !intel_dp->is_mst) intel_dp_unset_edid(intel_dp); @@ -5717,6 +5722,9 @@ intel_dp_detect(struct drm_connector *connector, status, intel_dp->dpcd, intel_dp->downstream_ports); +out_vdd_off: + intel_pps_vdd_off(intel_dp); + return status; } diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index ffeee9daa5689..73a2c9bdd2add 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -801,7 +801,8 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp) } /* - * Must be paired with intel_pps_off(). + * Must be paired with intel_pps_vdd_off() or - to disable + * both VDD and panel power - intel_pps_off(). * Nested calls to these functions are not allowed since * we drop the lock. Caller must use some higher level * locking to prevent nested calls from other threads. @@ -950,6 +951,17 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync) edp_panel_vdd_schedule_off(intel_dp); } +void intel_pps_vdd_off(struct intel_dp *intel_dp) +{ + intel_wakeref_t wakeref; + + if (!intel_dp_is_edp(intel_dp)) + return; + + with_intel_pps_lock(intel_dp, wakeref) + intel_pps_vdd_off_unlocked(intel_dp, false); +} + void intel_pps_on_unlocked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h index bc5046d536264..c83007152f07d 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.h +++ b/drivers/gpu/drm/i915/display/intel_pps.h @@ -34,6 +34,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp); void intel_pps_check_power_unlocked(struct intel_dp *intel_dp); void intel_pps_vdd_on(struct intel_dp *intel_dp); +void intel_pps_vdd_off(struct intel_dp *intel_dp); void intel_pps_on(struct intel_dp *intel_dp); void intel_pps_off(struct intel_dp *intel_dp); void intel_pps_vdd_off_sync(struct intel_dp *intel_dp); From patchwork Fri Oct 25 16:02:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13850998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2FA9D1039E for ; Fri, 25 Oct 2024 16:02:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 488F110EB14; Fri, 25 Oct 2024 16:02:42 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="JyYFTu/a"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id DA3C810EB0D for ; Fri, 25 Oct 2024 16:02:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729872152; x=1761408152; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1YXb+6uJBcYGNh3ZeO/9v4QAUB0mKmX4ATzHaF/O+SI=; b=JyYFTu/aFZOSXotjCCjafPmRG8dnThvm/0aCdxEZop+iZtLym2H+gbk7 ffwgzIC86HXI4tU2VWhzcJqc2Tz32YRxoqDcTS3TKDribPzrdkru6k1dP W+9JlTNgefBgeN+s1874P26OUeGLL1YyUVJr9FmSduVCoGFra3DdxFTyr oDfnnHGUO0m+26+IAw3PPckrOJbmm+1/OmU5TksMlGFI/VAYM1XDzgZFu ahbh0lagFa3NfXDmy8E85k9j6ij9KBeIDt+6KAE1hVxhBfenTh3ZOK7gn xjnwpa7ofZJaIB3VaFYJsdiMvuX8bVz5SYkRshONTwc6ixAlUhiwhZu+I g==; X-CSE-ConnectionGUID: oHSrkg+zRCKQ9h62Ep29mw== X-CSE-MsgGUID: FGofLLBwRSW+JnfQn9X0Og== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="33242386" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="33242386" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:02:31 -0700 X-CSE-ConnectionGUID: 3sKlrTJ5SU6g1XPVsUBb2g== X-CSE-MsgGUID: kvekcTnSTIKGahiGLd7y2w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81783701" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:02:31 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= Subject: [PATCH v5 3/8] drm/i915/dp: Initialize the source OUI write timestamp always Date: Fri, 25 Oct 2024 19:02:54 +0300 Message-ID: <20241025160259.3088727-4-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241025160259.3088727-1-imre.deak@intel.com> References: <20241025160259.3088727-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" If the source OUI DPCD register value matches the expected Intel OUI value, the write timestamp doesn't get updated leaving it at the 0 initial value if the OUI wasn't written before. This can lead to an incorrect wait duration in intel_dp_wait_source_oui(), since jiffies is not inited to 0 in general (on a 32 bit system INITIAL_JIFFIES is set to 5 minutes ahead of wrap-around). Fix this by intializing the write timestamp in the above case as well. Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 69a4e9c86d386..778cc33d3c690 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3415,8 +3415,11 @@ intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful) if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) drm_err(&i915->drm, "Failed to read source OUI\n"); - if (memcmp(oui, buf, sizeof(oui)) == 0) + if (memcmp(oui, buf, sizeof(oui)) == 0) { + /* Assume the OUI was written now. */ + intel_dp->last_oui_write = jiffies; return; + } } if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) From patchwork Fri Oct 25 16:02:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13850994 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F116FD116FB for ; Fri, 25 Oct 2024 16:02:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9043910EB10; Fri, 25 Oct 2024 16:02:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="IzHxaD5T"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1E53210EB0D for ; Fri, 25 Oct 2024 16:02:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729872153; x=1761408153; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dzaZnI2uxq89jxOTaLb+kSjGXSwgAxsyebLW5IMlSo4=; b=IzHxaD5TM4YHcGxu9Ek4wOaGX6dEOxC2iUrGP+CfsbZ35x0GtXmlQJ3Z E1iN990aq7CNiZrZ65agFYDX8AfCI6jC+hNbT6F5VPnM3YUcSmTWnv4kr e0Qv4aYX5DqnluBIMJVCR3nK4DrJaNjAmpG0iQl/idxwi0bZCpeByeixX 40uRyiKlJX2msR/+Sx8T6JIG+hh3yr54WOsVA8fjM2Dp1vuwJC58JYPyR v16iuogf37L63LQeYxv9ncF6fkY9SmzMI+rejdu82Ca1LRBhLVhY972mb G1zStpQXUZ+ZSu19NvUg2BPX8m/Yf+YkwxsIQAjhliCEo0ZXSsfkGZHoN A==; X-CSE-ConnectionGUID: Gfm9MlohRwKFAKiq8vnEbw== X-CSE-MsgGUID: B1paVQ+mTnG/jqKbPumfYA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="33242388" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="33242388" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:02:33 -0700 X-CSE-ConnectionGUID: fDRsfAN3QdC2Lq/Mr+uUWg== X-CSE-MsgGUID: SE3F3tbpSeini7rKUb5JZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81783703" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:02:32 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= Subject: [PATCH v5 4/8] drm/i915/dp: Track source OUI validity explicitly Date: Fri, 25 Oct 2024 19:02:55 +0300 Message-ID: <20241025160259.3088727-5-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241025160259.3088727-1-imre.deak@intel.com> References: <20241025160259.3088727-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" While updating the source OUI on the sink the driver should avoid writing the OUI if it's already up-to-date to prevent the sink from resetting itself in response to the update. On eDP - the only output type where the OUI was updated so far - the driver ensured this by comparing the current source OUI DPCD register values with the expected Intel OUI value, skipping the update in case of a match. On some non-eDP sinks - at least on Synaptics branch devices - this method doesn't work, since the source OUI DPCD registers read back as all 0, even after updating the registers. Handle the above kind of sinks by tracking when the OUI was updated and so should be valid, regardless of what the DPCD registers contain. eDP sinks reset the written source OUI value when the panel power is disabled, invalidate the OUI state accordingly. This is required by a follow-up patch updating the source OUI for non-eDP sink types as well. v2: Fix setting intel_dp::oui_valid=true, if the DPCD register contains already the expected value. Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/g4x_dp.c | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 1 + .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 38 ++++++++++++------- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_pps.c | 6 ++- 6 files changed, 34 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 440fb3002f286..596e926ef0894 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -1251,6 +1251,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder) intel_dp->DP = intel_de_read(display, intel_dp->output_reg); intel_dp->reset_link_params = true; + intel_dp_invalidate_source_oui(intel_dp); if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) vlv_pps_pipe_reset(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ff4c633c85460..c4fa161e118dd 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4392,6 +4392,7 @@ static void intel_ddi_encoder_reset(struct drm_encoder *encoder) struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); intel_dp->reset_link_params = true; + intel_dp_invalidate_source_oui(intel_dp); intel_pps_encoder_reset(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 2bb1fa64da2f1..9b46427806c6d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1765,6 +1765,7 @@ struct intel_dp { /* When we last wrote the OUI for eDP */ unsigned long last_oui_write; + bool oui_valid; bool colorimetry_support; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 778cc33d3c690..ca5912f8057b6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3401,33 +3401,46 @@ void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, } static void -intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful) +intel_dp_init_source_oui(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); u8 oui[] = { 0x00, 0xaa, 0x01 }; u8 buf[3] = {}; + if (!intel_dp_is_edp(intel_dp)) + return; + + if (READ_ONCE(intel_dp->oui_valid)) + return; + + WRITE_ONCE(intel_dp->oui_valid, true); + /* * During driver init, we want to be careful and avoid changing the source OUI if it's * already set to what we want, so as to avoid clearing any state by accident */ - if (careful) { - if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) - drm_err(&i915->drm, "Failed to read source OUI\n"); + if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) + drm_err(&i915->drm, "Failed to read source OUI\n"); - if (memcmp(oui, buf, sizeof(oui)) == 0) { - /* Assume the OUI was written now. */ - intel_dp->last_oui_write = jiffies; - return; - } + if (memcmp(oui, buf, sizeof(oui)) == 0) { + /* Assume the OUI was written now. */ + intel_dp->last_oui_write = jiffies; + return; } - if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) + if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) { drm_err(&i915->drm, "Failed to write source OUI\n"); + WRITE_ONCE(intel_dp->oui_valid, false); + } intel_dp->last_oui_write = jiffies; } +void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp) +{ + WRITE_ONCE(intel_dp->oui_valid, false); +} + void intel_dp_wait_source_oui(struct intel_dp *intel_dp) { struct intel_connector *connector = intel_dp->attached_connector; @@ -3463,8 +3476,7 @@ void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) lspcon_resume(dp_to_dig_port(intel_dp)); /* Write the source OUI as early as possible */ - if (intel_dp_is_edp(intel_dp)) - intel_edp_init_source_oui(intel_dp, false); + intel_dp_init_source_oui(intel_dp); /* * When turning on, we need to retry for 1ms to give the sink @@ -4185,7 +4197,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector * If needed, program our source OUI so we can make various Intel-specific AUX services * available (such as HDR backlight controls) */ - intel_edp_init_source_oui(intel_dp, true); + intel_dp_init_source_oui(intel_dp); return true; } diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 4efb9605a50e0..48f10876be656 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -189,6 +189,7 @@ void intel_dp_check_frl_training(struct intel_dp *intel_dp); void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); +void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp); void intel_dp_wait_source_oui(struct intel_dp *intel_dp); int intel_dp_output_bpp(enum intel_output_format output_format, int bpp); diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 73a2c9bdd2add..017474a2a8574 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -862,8 +862,10 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp) intel_de_read(display, pp_stat_reg), intel_de_read(display, pp_ctrl_reg)); - if ((pp & PANEL_POWER_ON) == 0) + if ((pp & PANEL_POWER_ON) == 0) { intel_dp->pps.panel_power_off_time = ktime_get_boottime(); + intel_dp_invalidate_source_oui(intel_dp); + } intel_display_power_put(dev_priv, intel_aux_power_domain(dig_port), @@ -1075,6 +1077,8 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp) wait_panel_off(intel_dp); intel_dp->pps.panel_power_off_time = ktime_get_boottime(); + intel_dp_invalidate_source_oui(intel_dp); + /* We got a reference when we enabled the VDD. */ intel_display_power_put(dev_priv, intel_aux_power_domain(dig_port), From patchwork Fri Oct 25 16:02:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13850993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E0C9D1039A for ; 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X-CSE-ConnectionGUID: jGglfOnsRcK5QKQwpWcJOQ== X-CSE-MsgGUID: 6XlB79AcRyK79yEY34EggA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="33242391" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="33242391" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:02:34 -0700 X-CSE-ConnectionGUID: J1EiTFGMSxqVkng/7fTnOg== X-CSE-MsgGUID: Tu7WnWmASOWl3K8NC/FCrg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81783704" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:02:33 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= Subject: [PATCH v5 5/8] drm/i915/dp: Reuse intel_dp_detect_dsc_caps() for eDP Date: Fri, 25 Oct 2024 19:02:56 +0300 Message-ID: <20241025160259.3088727-6-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241025160259.3088727-1-imre.deak@intel.com> References: <20241025160259.3088727-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Reuse intel_dp_detect_dsc_caps() which already checks for the source's DSC cap and retrieves the DPCD version from the DPRX caps. Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 38 ++++++++++++------------- 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index ca5912f8057b6..a3bc631d64095 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4014,6 +4014,23 @@ static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector * intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd); } +static void +intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ + if (!HAS_DSC(i915)) + return; + + if (intel_dp_is_edp(intel_dp)) + intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], + connector); + else + intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], + connector); +} + static void intel_edp_mso_mode_fixup(struct intel_connector *connector, struct drm_display_mode *mode) { @@ -4189,9 +4206,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector intel_dp_set_max_sink_lane_count(intel_dp); /* Read the eDP DSC DPCD registers */ - if (HAS_DSC(dev_priv)) - intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], - connector); + intel_dp_detect_dsc_caps(intel_dp, connector); /* * If needed, program our source OUI so we can make various Intel-specific AUX services @@ -5578,23 +5593,6 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) false); } -static void -intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) -{ - struct drm_i915_private *i915 = dp_to_i915(intel_dp); - - /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ - if (!HAS_DSC(i915)) - return; - - if (intel_dp_is_edp(intel_dp)) - intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], - connector); - else - intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], - connector); -} - static void intel_dp_detect_sdp_caps(struct intel_dp *intel_dp) { From patchwork Fri Oct 25 16:02:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13850996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2BEBD1039A for ; Fri, 25 Oct 2024 16:02:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 59A2110EB12; Fri, 25 Oct 2024 16:02:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="elgd0/ri"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8C8E410EB0F for ; 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25 Oct 2024 09:02:35 -0700 X-CSE-ConnectionGUID: UQVrsGAmSnWJOanfgJee/w== X-CSE-MsgGUID: qNzwE5MGR6SKdkN3sdBemg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81783709" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:02:34 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= Subject: [PATCH v5 6/8] drm/i915/dp: Write the source OUI for eDP before detecting sink capabilities Date: Fri, 25 Oct 2024 19:02:57 +0300 Message-ID: <20241025160259.3088727-7-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241025160259.3088727-1-imre.deak@intel.com> References: <20241025160259.3088727-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The eDP sink's capabilities, like DSC, may depend on the source OUI written to the sink, so ensure the OUI is written before reading out the capabilities. Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a3bc631d64095..0d6d7dc1e4ccd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4196,6 +4196,12 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14; } + /* + * If needed, program our source OUI so we can make various Intel-specific AUX services + * available (such as HDR backlight controls) + */ + intel_dp_init_source_oui(intel_dp); + /* * This has to be called after intel_dp->edp_dpcd is filled, PSR checks * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] @@ -4208,12 +4214,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector /* Read the eDP DSC DPCD registers */ intel_dp_detect_dsc_caps(intel_dp, connector); - /* - * If needed, program our source OUI so we can make various Intel-specific AUX services - * available (such as HDR backlight controls) - */ - intel_dp_init_source_oui(intel_dp); - return true; } From patchwork Fri Oct 25 16:02:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13850995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D19CD1039E for ; Fri, 25 Oct 2024 16:02:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1DFED10EB0F; Fri, 25 Oct 2024 16:02:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kWrfF0/K"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id D44CE10EB0F for ; Fri, 25 Oct 2024 16:02:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729872157; x=1761408157; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s16p+2dI/8GqFUNP2AAQlgyOhzZL3LWhLgRSzOTe6sk=; b=kWrfF0/K5Hry4LG04i5TLNrChKow8w0h3zTMzrAXuvGaF3RgULOws6Rr IIhZHbwDuvznrR/lcShsG7nul6yPJ8WRZJgAa0qs+6LEH5Fkpu1roUp+2 Xu2vc+MbPi1RW85Bx944XnUlAH94cIDWjwc3NWaH7GqA8aFBJBAzYNpx8 PIOG6CqxLwVIux8rYGMroWst7A2PEWyFpagEb9gZjieDesa4WHrJtGSu5 uHFPe/sMR1MhBow2UM7zYKy8noeJbmDT69EHiK+L+y+RSHheHlA6nqmrM iZajvj/S4EPz8EvMSsC/uZtaIKOn46LbiIuyBSJV3g/4jKEDYRJVioyu/ g==; X-CSE-ConnectionGUID: /LWEtYWXSC+OnajyV9MDqw== X-CSE-MsgGUID: Fa74AAl/TL+mAd5n+Yq58Q== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="33242404" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="33242404" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:02:36 -0700 X-CSE-ConnectionGUID: Kxk0KjsdQJyZ4yvnknCxqg== X-CSE-MsgGUID: qgAyP/08S1KRVIXlNYOK4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81783713" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:02:36 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= Subject: [PATCH v5 7/8] drm/i915/dp: Write the source OUI during connector detection Date: Fri, 25 Oct 2024 19:02:58 +0300 Message-ID: <20241025160259.3088727-8-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241025160259.3088727-1-imre.deak@intel.com> References: <20241025160259.3088727-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The DP sink's capabilities, like DSC, may depend on the source OUI written to the sink. On eDP this OUI value could have been reset before the detection started if the panel power on it got disabled. Make sure the OUI is re-written at the beginning of detection in this case, before the sink capabilities are read out. Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0d6d7dc1e4ccd..916301aa9f6b6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5664,6 +5664,8 @@ intel_dp_detect(struct drm_connector *connector, goto out_unset_edid; } + intel_dp_init_source_oui(intel_dp); + ret = intel_dp_tunnel_detect(intel_dp, ctx); if (ret == -EDEADLK) { status = ret; From patchwork Fri Oct 25 16:02:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13850997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 239E2D116FB for ; Fri, 25 Oct 2024 16:02:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BE30310EB13; Fri, 25 Oct 2024 16:02:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Zj5SfnFO"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id D911A10EB0F for ; Fri, 25 Oct 2024 16:02:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729872158; x=1761408158; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=+tU+hnS3v0kko76tvaq20/XUEF948WIb28DNlkWqP8E=; b=Zj5SfnFOeLR9HPowk7+EVZfKU737zVX0Q8gEfGBaw7oNdaAnaSsOUxm/ OZX0B/XwAZwlCBCR/2lJS9rPQnEe/rEjva6YoSDDt1bsp4PHbSLcx865u 12ylSxcPQhmot/GTL7eqzcFsn486GXtnDOW3JGFtugXnGG8YM4QiV5W+F g9BqWBzv0wMq+oIkvuZe8Udo8p0+kGAn8lg+ho5RH1OyV9FpBoDy+72Lk 0m9cJrTMDFmQuUM24JJk3uWd66AxzUFn1kw/BRQUe+qb7Xxek6bR1Y/K5 CviTAU72BMvZk2psnaHtOs/FR7V/TZWmmbEeQBhQuKkl79VoKdPBhZtnN g==; X-CSE-ConnectionGUID: CVjX7H3GQ1GtbcbPF8lmtA== X-CSE-MsgGUID: 9i478rdYQbirsuTyK3owCg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="33242406" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="33242406" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:02:37 -0700 X-CSE-ConnectionGUID: mf2xTv80R4qpw8hxgRSFZQ== X-CSE-MsgGUID: 2Nsm95N4RpSv5cNfnPs+7Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,232,1725346800"; d="scan'208";a="81783715" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2024 09:02:37 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v5 8/8] drm/i915/dp: Write the source OUI for non-eDP sinks as well Date: Fri, 25 Oct 2024 19:02:59 +0300 Message-ID: <20241025160259.3088727-9-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241025160259.3088727-1-imre.deak@intel.com> References: <20241025160259.3088727-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" At least the i-tec USB-C Nano 2x Display Docking Station (containing a Synaptics MST branch device) requires the driver to update the source OUI DPCD registers to expose its DSC capability. Accordingly update the OUI for all sink types (besides eDP where this has been done already). v2: Rebased on latest patch version. Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11776 Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 916301aa9f6b6..24daf5f973770 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3407,9 +3407,6 @@ intel_dp_init_source_oui(struct intel_dp *intel_dp) u8 oui[] = { 0x00, 0xaa, 0x01 }; u8 buf[3] = {}; - if (!intel_dp_is_edp(intel_dp)) - return; - if (READ_ONCE(intel_dp->oui_valid)) return; @@ -6133,6 +6130,8 @@ intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) if (long_hpd) { intel_dp->reset_link_params = true; + intel_dp_invalidate_source_oui(intel_dp); + return IRQ_NONE; }