From patchwork Tue Oct 29 19:12:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13855314 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DB94D3A695 for ; Tue, 29 Oct 2024 19:11:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 619A810E6E0; Tue, 29 Oct 2024 19:11:45 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="BJZ+ESB3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 09C4710E6DE for ; Tue, 29 Oct 2024 19:11:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730229105; x=1761765105; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=C1yV3IyV4gicB2UK05+sle9LT8gCt8hTp6kAUxfHIPE=; b=BJZ+ESB3XdVk4JSv/U7bCQZ3RW/BmGHCh0ltBK6lnrkpjPZY2ylEZRz5 8/zzuX/BrP1lE0pbxEvcRzbMQ0RE7+c6iXT9nH4qI71DafyMem/LnCMKR nLExm1MOoFvnNA2I96bH0/h10WV8/d+WuLxdo+dNWVWLUSj4CFjAa2NwL sRmbAXEUGMZyNn/ik6uCz0I5k/vq9uLLCCPChlp36aQsQuIAaKfE1ImW+ hmWRyBBg/YmzBVisTKOxhKXAhJ+k6Ms9AS069qWvPtDfAfQbOsCEMIuvn iC19bPQ329BcfWB8H0RN45vQJPLh7Khc6dm7pjTwUncDScA6eSeQ/qiYr g==; X-CSE-ConnectionGUID: 3y0E5LneQIOkYf3E+1aMgw== X-CSE-MsgGUID: 8/+RTT1KTfikEJSYDCkp6Q== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="29745594" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="29745594" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2024 12:11:44 -0700 X-CSE-ConnectionGUID: UOuX7ofnQLGNeeOQ9wYxCA== X-CSE-MsgGUID: KMyUFKsLSaSuHz9vcAOlfg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="86812700" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2024 12:11:44 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 1/4] drm/i915/ptl/dp_mst: Fix slave transcoder enabling wrt. DDI function Date: Tue, 29 Oct 2024 21:12:12 +0200 Message-ID: <20241029191215.3889861-2-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241029191215.3889861-1-imre.deak@intel.com> References: <20241029191215.3889861-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On PTL during modeset enabling configure the DDI function without enabling it for MST slave transcoders before programming the data and link M/N values. The DDI function gets enabled separately later in the transcoder enabling sequence. This fixes a slave transcoder getting stuck during enabling, leading to page flip timeout errors on the corresponding pipe. The spec requires the same programming step for ADLP+ platforms, that will be addressed separately (on those platforms the above transcoder getting stuck issue was not observed). Bspec: 68849 Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_ddi.h | 2 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ff4c633c85460..6bbfe0762cafa 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -619,7 +619,7 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable * bit. */ -static void +void intel_ddi_config_transcoder_func(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index 6d85422bdefef..1aa2e3a190aee 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -57,6 +57,8 @@ void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, void intel_ddi_init(struct intel_display *display, const struct intel_bios_encoder_data *devdata); bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); +void intel_ddi_config_transcoder_func(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 1a2ff3e1cb68f..7c16406883594 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1224,6 +1224,9 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream) intel_ddi_enable_transcoder_clock(encoder, pipe_config); + if (DISPLAY_VER(dev_priv) >= 30 && !first_mst_stream) + intel_ddi_config_transcoder_func(encoder, pipe_config); + intel_dsc_dp_pps_write(&dig_port->base, pipe_config); intel_ddi_set_dp_msa(pipe_config, conn_state); } From patchwork Tue Oct 29 19:12:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13855315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 825EFD3A694 for ; Tue, 29 Oct 2024 19:11:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1CC4C10E6E1; Tue, 29 Oct 2024 19:11:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bqjlSsbv"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2635E10E6E0 for ; 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29 Oct 2024 12:11:46 -0700 X-CSE-ConnectionGUID: 6QjMGZJ1Tx2ilHTp6QQcKQ== X-CSE-MsgGUID: RSeE77ngRwa27Ky/IfQHOA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="86812713" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2024 12:11:45 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 2/4] drm/i915/dp: Export intel_ddi_config_transcoder_dp2() Date: Tue, 29 Oct 2024 21:12:13 +0200 Message-ID: <20241029191215.3889861-3-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241029191215.3889861-1-imre.deak@intel.com> References: <20241029191215.3889861-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Export intel_ddi_config_transcoder_dp2() taken into use by the MST encoder in the next patch. Move the HAS_DP20() check to the function, so it doesn't need to be checked for each caller. Besides enabling the DP2 configuration also add a way to disable it, required by the MST slave transcoder disabling sequence in the next patch. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 15 +++++++++------ drivers/gpu/drm/i915/display/intel_ddi.h | 3 +++ 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 6bbfe0762cafa..5ff7d23775d82 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -454,15 +454,19 @@ static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) return master_transcoder + 1; } -static void +void intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) + const struct intel_crtc_state *crtc_state, + bool enable) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 val = 0; - if (intel_dp_is_uhbr(crtc_state)) + if (!HAS_DP20(i915)) + return; + + if (enable && intel_dp_is_uhbr(crtc_state)) val = TRANS_DP2_128B132B_CHANNEL_CODING; intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); @@ -2549,7 +2553,7 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, /* * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. */ - intel_ddi_config_transcoder_dp2(encoder, crtc_state); + intel_ddi_config_transcoder_dp2(encoder, crtc_state, true); /* * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST @@ -2686,8 +2690,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, */ intel_ddi_enable_transcoder_clock(encoder, crtc_state); - if (HAS_DP20(dev_priv)) - intel_ddi_config_transcoder_dp2(encoder, crtc_state); + intel_ddi_config_transcoder_dp2(encoder, crtc_state, true); /* * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index 1aa2e3a190aee..bf27b2fbb08e9 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -65,6 +65,9 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state); +void intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + bool enable); void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, bool enabled); From patchwork Tue Oct 29 19:12:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13855316 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7151BD3A692 for ; Tue, 29 Oct 2024 19:11:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1CB4010E6E4; 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X-CSE-ConnectionGUID: gUjXOr7XRcimkvRMggTEsQ== X-CSE-MsgGUID: 7wDHQZX8S3edxdhbjd3QIw== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="29745605" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="29745605" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2024 12:11:47 -0700 X-CSE-ConnectionGUID: +hm5xwwrRQOFtywgDoliFA== X-CSE-MsgGUID: Dv3RaTABT5OtAzunNYvueQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="86812727" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2024 12:11:46 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 3/4] drm/i915/ptl/dp_mst: Align slave transcoder sequences with spec wrt. DP2 config Date: Tue, 29 Oct 2024 21:12:14 +0200 Message-ID: <20241029191215.3889861-4-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241029191215.3889861-1-imre.deak@intel.com> References: <20241029191215.3889861-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On PTL during modeset enabling and disabling enable and disable the DP2 configuration for MST slave transcoders as required by the specification. The spec requires the same programming steps on ADLP+ platforms as well, this will be addressed by the next patch. Bspec: 68849 Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 7c16406883594..b1eee8500a383 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1057,6 +1057,9 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, intel_ddi_disable_transcoder_func(old_crtc_state); + if (DISPLAY_VER(dev_priv) >= 30 && !last_mst_stream) + intel_ddi_config_transcoder_dp2(encoder, old_crtc_state, false); + for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { const struct intel_crtc_state *old_pipe_crtc_state = intel_atomic_get_old_crtc_state(state, pipe_crtc); @@ -1224,8 +1227,10 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream) intel_ddi_enable_transcoder_clock(encoder, pipe_config); - if (DISPLAY_VER(dev_priv) >= 30 && !first_mst_stream) + if (DISPLAY_VER(dev_priv) >= 30 && !first_mst_stream) { + intel_ddi_config_transcoder_dp2(encoder, pipe_config, true); intel_ddi_config_transcoder_func(encoder, pipe_config); + } intel_dsc_dp_pps_write(&dig_port->base, pipe_config); intel_ddi_set_dp_msa(pipe_config, conn_state); From patchwork Tue Oct 29 19:12:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13855317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B986D3A696 for ; Tue, 29 Oct 2024 19:11:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AFFCF10E6E5; Tue, 29 Oct 2024 19:11:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="KkBsrNaB"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6AE5810E6E1 for ; Tue, 29 Oct 2024 19:11:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730229108; x=1761765108; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=yDzZl1JQuspzlRWr2hzYejub4PkNT4THf2BzpvQ3V2I=; b=KkBsrNaBaG4QrRmdhrCT/opb85lZWG7T/OmYZF1zGrfyGhqtSAVyqgtl dB9hADjR0KkyBW9dvrCtaFDu7L02PXaR3qUGP/hcRNAI7X1iD1Du/U6RW VEYl5+Hm8NNATjWaD4X/pgj1dAtUUPVJcdTeBxFfH7OcYXSwtW6zjGxov 8QRZmKn6GT5mY/pKrml6DZzgOb1Q6Hu7N9CT6l8L7w5hSRmrhzjLp2CWM etpTgsQumw8bHWGvXbt6mqWAMfxgHbIkYsYSVSKMp+eYF6TOuTgaW/mbe p4d3S1YtNfi6c+XtKPA4q0ub6FDWHCLPvgAY0AdSynCzQRePuV8KiYjSt g==; X-CSE-ConnectionGUID: kam1FbCxSnSF9EBXekryfQ== X-CSE-MsgGUID: mY5rULjESDSQ3WvgIQdRig== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="29745613" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="29745613" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2024 12:11:48 -0700 X-CSE-ConnectionGUID: CpG1A++ARHKS28Hk7j9JlA== X-CSE-MsgGUID: 9jPw7YVxTiGYbXEqmZJgHw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="86812745" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2024 12:11:47 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH 4/4] drm/i915/adlp+: Align slave transcoder sequences with spec wrt. DDI function/DP2 config Date: Tue, 29 Oct 2024 21:12:15 +0200 Message-ID: <20241029191215.3889861-5-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241029191215.3889861-1-imre.deak@intel.com> References: <20241029191215.3889861-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On ADLP+ during modeset enabling configure the DDI function without enabling it for MST slave transcoders before programming the data and link M/N values. The DDI function gets enabled separately later in the transcoder enabling sequence. Also for these platforms the DP2 configuration needs to be enabled/disabled during enabling/disabling MST slave transcoders. Align the code with the spec wrt. the above DDI function and DP2 configuration programming. Bspec: 55424, 54128, 65448, 68849 Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index b1eee8500a383..089ed457621e7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1057,7 +1057,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, intel_ddi_disable_transcoder_func(old_crtc_state); - if (DISPLAY_VER(dev_priv) >= 30 && !last_mst_stream) + if (DISPLAY_VER(dev_priv) >= 13 && !last_mst_stream) intel_ddi_config_transcoder_dp2(encoder, old_crtc_state, false); for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { @@ -1227,7 +1227,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream) intel_ddi_enable_transcoder_clock(encoder, pipe_config); - if (DISPLAY_VER(dev_priv) >= 30 && !first_mst_stream) { + if (DISPLAY_VER(dev_priv) >= 13 && !first_mst_stream) { intel_ddi_config_transcoder_dp2(encoder, pipe_config, true); intel_ddi_config_transcoder_func(encoder, pipe_config); }