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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.23.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:23:52 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 01/23] ARM: dts: socfpga: fix typo Date: Tue, 29 Oct 2024 20:23:27 +0000 Message-Id: <20241029202349.69442-2-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 A semicolon was fallen off the wall. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 6b6e77596..7113fe5b5 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -169,8 +169,7 @@ main_gpio_db_clk: main_gpio_db_clk@74 { main_sdmmc_clk: main_sdmmc_clk@78 { #clock-cells = <0>; - compatible = "altr,socfpga-a10-perip-clk" -; + compatible = "altr,socfpga-a10-perip-clk"; clocks = <&main_pll>; reg = <0x78>; }; From patchwork Tue Oct 29 20:23:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13855366 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55565207A17; Tue, 29 Oct 2024 20:23:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233439; cv=none; b=fVW7YGH2G6CAUyr+HgeAjGZcK9sFjTJ27RLklU9RxjazmcgCMDp48hrS6RmnSouYq6kh5gRqTn+r//9IyK/sTcAlqfv/BFTNe57GWcMFebjMZ4O32V9A46CuprKn3JwiXNo/Fq70Dvgg9Nr7rbTSKcWWcYMBrL8zQ/cqY2+z07s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233439; c=relaxed/simple; bh=McMTyWzS0Bg4WFWkM4x5Eq6n8AM1vXInQ676orlwBs8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=g3fPMvowlTrbjM+U+N455w1fAI8kK9LDRgt2m3Euw3AXkF6ze9ro2HTB1J5ZlH0PoV6fYLgce4bqN04YMVQRFtZgpGZAib7XyFz5q//Udf6LVRr0xZdYAAzclvhEcjta2qC+JOfDPKvbm/pG2DhywyRM7Cy206qS1Ofm1Uas1g0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=P6cWlj20; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="P6cWlj20" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-37d450de14fso529999f8f.2; Tue, 29 Oct 2024 13:23:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730233436; x=1730838236; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a7BTF2QgV5p9nNttdJyKFEUTkRzHJB1L1AnxAUE0mKw=; b=P6cWlj207WRhWakbZfsj4LyvtYTT4yeMOF2J+ZYMZSCsq3Ff0Lm9zCpwMYUFxZYE7P 0iHbf/l/zu9DjIimuFUZWvipkQIP4mCcZDwHhPxwZkoTbMOKdVj4Gtftoz5t2+PIWMom g6XoEUEemzd6DIl6rXcA3X69MKQeUzX34Pm/YPkOHZxjL5lK2+rcaHp/dMb4gNS2sgNB CgvDo7hEIyvEWxo3LhOsCOf8RYjsH2TJ160kZM1wv08DYoa7VCdu6xkwv5lGrW26tBRe vSKIk4Na16Ul49Png0p7ZXvdvSGr8omkrbzCN3DQ+c9Im1aylUZ3E0OEj+8qDx+wQ481 TF/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730233436; x=1730838236; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a7BTF2QgV5p9nNttdJyKFEUTkRzHJB1L1AnxAUE0mKw=; b=UKmjE6B2y8jWMdtycSPcjGqB2TGaYRseUG22sK0FhUY0FdqGg/Tms5dV/Cxjd/1ZkC gF0Fq1tLRbQgyF9ugD2vLSKUmpaInq/kJ14tKRC6d8ihNMyhlcpiWaePH3kyjzTM9b90 2pEOglbSH9j0lHqFY7G/gphQxdepL9vdhA9zQsUdPFCsjpjJrr7qGIpc45Cgig1/X2cx V70woASzvR+Mcqnau8w8wyvpveQQy7SIwsx5A8nPC7Qcd3FrveL8ucmUJ9lorAQFNIJQ EzZ5hth7jMo5Ww8aC7R+i8tzWEYpmCbrwztsVc3AIC9V/3RK6fYeP2BXmdojGqKgltk0 y5SQ== X-Forwarded-Encrypted: i=1; AJvYcCV5R1E0ef5ydGQ7NvNZXt0JclcEVSNja8tNXSUZqtgderuMPLp1sdsUMzvQmndDhCaf1etvv0lYNd9u+HGo@vger.kernel.org, AJvYcCXIw9rGE7FMDLS+VVanrdacyQRaTYfqFkNli4qCiR6XlKGR5QZFdj4HDUxxn2CcywDtaFx8WPRyOAhy@vger.kernel.org, AJvYcCXJ+LRk9In+EdaVUu+C1RMfdCRlZ3cep1tTKenttX51LjmxF1kgxXy8nonRh4/01Z2YUKGKpfVn@vger.kernel.org X-Gm-Message-State: AOJu0Yz1XbTP1b/DTUAZhhfrhCNYQPnB68iocsaAPGKh4/uQgcU6ZC+6 MK6KViAqPnbe/DWaRsBxIjsNWp8FwhlSc7d2hzwDl73ssldVl3o+ X-Google-Smtp-Source: AGHT+IGD+/RLlUFQ9JfrHmh8ZbfUuGjxW0QoMqGnWizIoxkZXn06IHyKtDzC4H57odNMJ3rODgdWcg== X-Received: by 2002:a05:6000:186b:b0:378:955f:d244 with SMTP id ffacd0b85a97d-380612bdf5dmr4232846f8f.14.1730233435443; Tue, 29 Oct 2024 13:23:55 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.23.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:23:54 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 02/23] ARM: dts: socfpga: align bus name with bindings Date: Tue, 29 Oct 2024 20:23:28 +0000 Message-Id: <20241029202349.69442-3-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Binding expects the bus node name to match bus and not amba. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 2 +- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi index 35be14150..c7ba1e4c7 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -62,7 +62,7 @@ soc { interrupt-parent = <&intc>; ranges; - amba { + bus { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 7113fe5b5..7abb8a0c5 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -54,7 +54,7 @@ soc { interrupt-parent = <&intc>; ranges; - amba { + bus { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From patchwork Tue Oct 29 20:23:29 2024 Content-Type: text/plain; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.23.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:23:56 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 03/23] ARM: dts: socfpga: align dma name with binding Date: Tue, 29 Oct 2024 20:23:29 +0000 Message-Id: <20241029202349.69442-4-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Binding expects the node name to match with dma-controller. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 2 +- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi index c7ba1e4c7..01cc5280f 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -68,7 +68,7 @@ bus { #size-cells = <1>; ranges; - pdma: pdma@ffe01000 { + pdma: dma-controller@ffe01000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xffe01000 0x1000>; interrupts = <0 104 4>, diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 7abb8a0c5..aa0e960a3 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -60,7 +60,7 @@ bus { #size-cells = <1>; ranges; - pdma: pdma@ffda1000 { + pdma: dma-controller@ffda1000 { compatible = "arm,pl330", "arm,primecell"; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.23.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:23:58 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 04/23] ARM: dts: socfpga: align fpga-region name Date: Tue, 29 Oct 2024 20:23:30 +0000 Message-Id: <20241029202349.69442-5-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Binding and setup expects to match fpga-region instead of old naming. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 2 +- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi index 01cc5280f..1562669b3 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -87,7 +87,7 @@ pdma: dma-controller@ffe01000 { }; }; - base_fpga_region { + fpga-region { compatible = "fpga-region"; fpga-mgr = <&fpgamgr0>; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index aa0e960a3..90e4ea61d 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -80,7 +80,7 @@ pdma: dma-controller@ffda1000 { }; }; - base_fpga_region { + fpga-region { #address-cells = <0x1>; #size-cells = <0x1>; From patchwork Tue Oct 29 20:23:31 2024 Content-Type: text/plain; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.23.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:00 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 05/23] ARM: dts: socfpga: add label to clock manager Date: Tue, 29 Oct 2024 20:23:31 +0000 Message-Id: <20241029202349.69442-6-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Devicetree setup expects a clock manager label to be around. In preparation of upcoming changes to allow for compatibility. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 90e4ea61d..7f7ac0dc1 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -88,7 +88,7 @@ fpga-region { fpga-mgr = <&fpga_mgr>; }; - clkmgr@ffd04000 { + clkmgr: clkmgr@ffd04000 { compatible = "altr,clk-mgr"; reg = <0xffd04000 0x1000>; From patchwork Tue Oct 29 20:23:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13855370 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2114D20967F; Tue, 29 Oct 2024 20:24:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233446; cv=none; b=dKUzrmV4QTnNjwEdqRowBBTljiulOkCIX9bti4ehbMn4+Tt5qoNyA/JrOKg7690KeIsmfeDY4Yz5/m5BOs/BHIqoslLx65FqSq3OlHq6/+eZv5Qs1K+X0iHW4s96mWoIcu/8ObMZvclY8WhtlULjFTR3HYqoIsFscZd/OTRDFwE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233446; c=relaxed/simple; bh=OtMc8F1P0PTrSTV9GAwD2G3wO6F1jpiSdyrg5IQ28zs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=avImlMkGqbC14+/IubSWNKJniD3P5RBTQaRsgpr+cPcXca8w3ryiWu8yxzG+RwJxwY6HSKqOXAseoQwAHar0Smmd04UL0BOd2OW1G0arCPeniNSsORYXvnPw0H6c+4w5SKEOxGO3PlV4Z5h5tNQMGqyM1bc74a30XZ1LEDJHcxc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KTm/yf8f; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KTm/yf8f" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-37d4dbb4a89so618747f8f.3; Tue, 29 Oct 2024 13:24:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730233442; x=1730838242; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zykG5xT9htU2beqODKL0ma8uO47wG8f6mRcFvD55rTU=; b=KTm/yf8fEuNcLlRj1twUuWPqJloGq6njXSGx+ZpxbW9mbtcExJvxeZHMlf5+guLb5l 9SddzHVRnj0bfhQZ4D9uJPxCrdasTrgjCJkNCPVFM033K8Ow2ljkYtCXRRQBkhlw2+i7 nCi1d/4J/8bFGjkgXhwhrPEG2wJ9s/3vZI+gr/oxtcf1xGmQp+Etf02UhE6i2ex8Beba 7hY44O4XHaRxOhZml4tOrB8dLTTNrQ6tccB2XGm6of75WwJxmQzUJtX5CVE1rcvDL3LD S2Cbmjqdjt4IeAxcdqJaCj4WrQtm5bdyYJmqyREdUFJ0uF/D2xjldzcWsjLSUnrkVtq+ 0Fzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730233442; x=1730838242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zykG5xT9htU2beqODKL0ma8uO47wG8f6mRcFvD55rTU=; b=Th7eX+qigy7d64VtIdvrL9IBxbfPnzbvN3AY6FtKhrtjTEclbuf0s+NZ/9ZPQRGf4P 2rCFUGbvOHxuSWqo2bTo9q1dp7EHFMyvRtdURgP03dZYsj7rm1PI500x8/7HcTsPC8ct IkhnTWOD9hUzBHLBbeiJztJlaFmDGZhQhht0U4vNmTXdFcvQtARaRpPcyFnLNf09nF0D BCUcF1FG9oU/45jnsYWYFvvRsTyAlDa2cuNihx7HYm1COw0+idhMnTCjNYk+SI8vShLA HNC9JwuVm3F19La0X6qVG2QXLw3uMbrfMh8l1azUqJoMuydP7MweuON6Ss8uC6vlGCex sHkg== X-Forwarded-Encrypted: i=1; AJvYcCU9csY04wpK4PlsKNJtqbWboX0PW83RrAgiD4GCf6lOAj2xrSVU7RzSnmHr3ozDBwKm/AQ/vGzyCR3Nf2F2@vger.kernel.org, AJvYcCV1JpANa9fHweE5CNTxzJTbQQukFhqkilgaJEusX028rWpqHSYuk+O8qv6jlArbA15AOkcIYUCE@vger.kernel.org, AJvYcCWVzCDhZbTWTAXLxk2cXzTowx/PBVZHuXALMYntsbp0qlKffeCi74c0cZO0rYp6sLtdjtIyFvBS3qSR@vger.kernel.org X-Gm-Message-State: AOJu0YzdkEdKULHQiIYmt1XQeA0HQOG4bngS7ClDv2AtJeRofGnpjInc m14hP+iP0el6GctiEiZPt3HvWppkx+RhUHm6d9VTpd34jDxe06i8 X-Google-Smtp-Source: AGHT+IHmAsezJTQ6HDzRiPuCCGE+RMKKJV1S7Rnrkqh2NL2lY4iIeUnDKBM6QOnU1gla9isevRSz4g== X-Received: by 2002:a05:600c:3542:b0:42c:ba6c:d9a7 with SMTP id 5b1f17b1804b1-4319ad08603mr47418785e9.4.1730233442025; Tue, 29 Oct 2024 13:24:02 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:01 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 06/23] ARM: dts: socfpga: add missing cells properties Date: Tue, 29 Oct 2024 20:23:32 +0000 Message-Id: <20241029202349.69442-7-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Binding requires size-cells and address-cells to be around for the SRAM. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 7f7ac0dc1..4b19fad1e 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -684,6 +684,8 @@ nand: nand-controller@ffb90000 { ocram: sram@ffe00000 { compatible = "mmio-sram"; + #address-cells = <1>; + #size-cells = <1>; reg = <0xffe00000 0x40000>; }; From patchwork Tue Oct 29 20:23:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13855371 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC696209F35; Tue, 29 Oct 2024 20:24:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233447; cv=none; b=kH8INhWBdkRQyZWJ3X0O0Gr62zNBClwj7qStyBUhdBfNZWjs5DL9c+m4BsCg9IpwLb/yonAK8jPWiNxoiy6V2kd4Ng2dMw9q4e/ROcZnMWaNwywluJXNNH0IhGhOCI18zJNgRvrqqDGrBNIUbDDakGFtS1tqEGyw1pvKctaw3dU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233447; c=relaxed/simple; bh=1KzJp/fai6aB837Tp2XCYOTjK4FVSS8lCtpXFfw4Wj0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YYZOHOAoeNZhaRWTTfOSKNU4dKRXeqiOwhhVECD++SJVCvGhiqjW92bbq2mX9/yLTeyRDm5ru0RoAMt6S8kRdJAxALV3HWvQTdnhsTajmjM+keC/QV5ukPSI23xpyLQCz5k/1TnlZRGWyLvSdQ4EOjiHQEG1/tTK2U6919XLXNI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Uaa34itJ; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Uaa34itJ" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-37d432f9f5aso549002f8f.3; Tue, 29 Oct 2024 13:24:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730233444; x=1730838244; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=syqLQEEuQIy2cda968KqPmvPAkdMXpl9TyM7P/fgr+8=; b=Uaa34itJ3roPdHxdOvgqwlkZeILUH/XfeRPvKbWIs8Guz65xsP5cZsdgAyLVn7W7Qv eYtXyft4RML2Vwwi/qW9jBTb/o3ModgkIqkOvdrVnlAYhYUmtFRtwQRldYZKm9JGFSaA V1CiRyjre1cmpfoEGoUAsVQjj5l9ciSSenIKsKczMcMdN425PX31AYIfq1uT4rAW7SWX Lc+8kLSUFSnEHIGvi0KE98YjFnb5bqPx+3J1dDfS5cJm67BcH7ix2bQT2MeuBTBU6H1r rZxNRtQqAavNgC8ys5POpXmIHdc9tPn3M1SUoSiLbfj0l5uWVqe4N1v06aSn+HbgMnXm tb7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730233444; x=1730838244; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=syqLQEEuQIy2cda968KqPmvPAkdMXpl9TyM7P/fgr+8=; b=Dx43qhrC3/lb89DMr3pE1VJD61+81uwLkWQg2A/mWB3NhVbvtreUPcQSHn/TAi4cmR X8/0Uy2biWMDAVaMYHNVF6MME5hOBZbQxmaKnC986vxDE+LfqROuJuY19YcIMOxnF0Ua W81XxFIP3PB2qkb+G/hS6yfolwPkgQwCqy/X4FpUyrr8EtYmFEmqoFcBz5C70LT4gfR7 LJjWd+l2HTcceMELvX1JAAF9LdeDTrjB+jshyq8XosNtokPJwcdpGLZ6fnDUWeFvDiPG JUxhYmdkb8zSkvHivrqJQQYwxhw8TiikviZ76sbr1c6YhREWi48H3vrtIYcpwE8TQWJm 1YmQ== X-Forwarded-Encrypted: i=1; AJvYcCUGOeyoNtjMvjUa3jacQHmq2TWfHsrMBKBaFdn9dI24lLIR8re94sAjN157q44bDYz07gmuPD0GD7AG@vger.kernel.org, AJvYcCUaW4lpqufPZiErGbpXtVE+ubJZRi9I0LePK2MZZJG4zMO3cKI5T19GHY9y5ieWm9Rs5yKORKPLHfsv9lOc@vger.kernel.org, AJvYcCX45872ng4qunEg9qN+ThPYf64YaLnvXvN+7bcEBBuhUXR1xtrS2o4HIWX0tETYqeLrg+QoyCEK@vger.kernel.org X-Gm-Message-State: AOJu0Yzrn4MSHOhV+eS+LbZ5T69ztzTz3VYJgHtaAlacYZZfjCe0kgPY 6P3sDuRC3vae8Ej+l4TzNs8VspD8q2vHeBr66zrP1w/IXUy9IrM5 X-Google-Smtp-Source: AGHT+IHGVFfyqJqlmqeKRFFKcmhj1OyaAu/znhSmRzQJTc6ZYgh+32XL3bPFTzuO8uUces3IhKZcmQ== X-Received: by 2002:a05:6000:1446:b0:37d:54d0:1f15 with SMTP id ffacd0b85a97d-38061231c59mr4689734f8f.7.1730233443892; Tue, 29 Oct 2024 13:24:03 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:03 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 07/23] ARM: dts: socfpga: fix missing ranges Date: Tue, 29 Oct 2024 20:23:33 +0000 Message-Id: <20241029202349.69442-8-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add reanges, since by dtschema 'ranges' is a required property here. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 4b19fad1e..65d04339f 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -81,10 +81,10 @@ pdma: dma-controller@ffda1000 { }; fpga-region { + compatible = "fpga-region"; #address-cells = <0x1>; #size-cells = <0x1>; - - compatible = "fpga-region"; + ranges; fpga-mgr = <&fpga_mgr>; }; From patchwork Tue Oct 29 20:23:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13855372 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7E2220A5D7; Tue, 29 Oct 2024 20:24:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233449; cv=none; b=BtgAfK6L6UiYMafjB0dsrsvVZMu7DGdmdhkgixnJ9sTb9aC28o+bR+XRNzPcM8G/25jtKz5Wh23JCujEQFO3mVty1//L0HZnEe1hpgXZJzLkvzV8RGOS6F0WI6VTBmpOT+QDECVBwVXiWknsbRFm+eCsCqV4n5XrhXhfilDAW4g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233449; c=relaxed/simple; bh=y6S/vFniqdK8FnY4Owxt462kYlq+HMo/27OIQpdXFyk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Rb7Fkcwo42ul2DZ2hwzrrcOskePkHFnKtY8pL+PVb2sOQINjhGLY8wGYMyfoEiRxE5LG7+AilEm0eGvtnoHKnCAscZGJOcEtOVg4SJWUym/5gLyi3GIK7GXqyy64wLjj+FVU+I9UnP3cZkIeFWIdEf9Nqh42/gPeQocprG/SVsc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KlhBr3BN; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KlhBr3BN" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-4315b957ae8so6260395e9.1; Tue, 29 Oct 2024 13:24:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730233446; x=1730838246; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QbnDXxocaCyheHFI8hTECOWKPKoXgfCmEGz3dctI1es=; b=KlhBr3BNIIEa6JN7gHPI+luJ08sLt/T0LUeCXefeMqqmCXyEfETDzc1tAZbS265ogL xoLU9eg2U9EZtUOOK607Ce3BjZxyodffAg7/XNJ5tc7H3galxf9sR2XYXM1kJ4dk0yvs wkEbyTcJg2q7pDzHtC5rjCdPj6uh2Nmzidqxp60mziqg9aEHB5Acj1BD0gXKa/bhY+kb Pm/u7dccaZCBipsX6b7HArqbHiKnucRM3K6PgViXk1qJ7/ifvFDBgWGdihLoQ4a/aFyj TaYhQIxkEb3Sf7A+aJyouJsu4+t2WwL1eXlqVr/z8/2gLDu7e8u3M2KeGmUMY2NOPM1Y kcQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730233446; x=1730838246; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QbnDXxocaCyheHFI8hTECOWKPKoXgfCmEGz3dctI1es=; b=UaRNMLV2U1jzFNUkjbFz+EpN6+LL+AKF0wR5nppPFjt8Xxi7pjw2cyuPp/DxZy00Ik li8zvr8LDRUkNvtmrMgfZrQvwp6g/+fIZtsuLWGR+Zat5wznzIewlYa/NFK2SccAQb+o GCdLubnhIRvMI/QY1s17dPh4SMhLgLl5yJtwJeh8nBicNQjzb32eCOUJ1CWF36j40dd4 aorZhv7AP/FAGwXpAI1EsPG8h2mNMQeTYr5LCIypQEPz9Xd+k5OfRQEA9mDKu4M/KQVb dr2FN+0Y7JN55G87KIGHsCUw8eDcaiRoPrR+VHAAVUlpdoeFtu/uLY+HcNDd6sqeJHGd oWOg== X-Forwarded-Encrypted: i=1; AJvYcCUQINACtSZTAzEiTDpsxOqPpVpzqvrLzgqnveBWFufcALxVx69DDj6NvP1wdYvH7vTfmsJPTATw4Lc+SwNa@vger.kernel.org, AJvYcCVlJpjWFJA22Sz+B8pLaQD9lT18ODXo7C/ud755UghM4TxrgMBVj3AfmK+fMJ8d7nkePeHuMBC5zotp@vger.kernel.org, AJvYcCWZ/v2tkjEMklPecmieGtawr8bvqoa3rpnwZ7FlmMxTh9ysP8QDlVt3lgkmDV3NpQvFaN5700RE@vger.kernel.org X-Gm-Message-State: AOJu0YxZm7YxND14OiO1I1GI6Y/x3cZJWvLlsb1XTJxwrXMkJAHK+rtW M/Cgbi/aNK8QfHa+cWs9PiY4kz7Evm4oAgivGJmgjQUWqTtSDDIy X-Google-Smtp-Source: AGHT+IETpjLLRg+7eXu2VyfPEE1vigfdrCP6sTkEwWApr6Df5/fyHL5jVC/64h7dxa0Nz1OLwcuYIA== X-Received: by 2002:a05:600c:511b:b0:431:558c:d9e9 with SMTP id 5b1f17b1804b1-4319ad24126mr50500115e9.5.1730233446109; Tue, 29 Oct 2024 13:24:06 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:05 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 08/23] ARM: dts: socfpga: add clock-frequency property Date: Tue, 29 Oct 2024 20:23:34 +0000 Message-Id: <20241029202349.69442-9-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add 'clock-frequency' is a required property by dtschema. Initialization is open, similar to agilex devices. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 65d04339f..5f4bed187 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -99,21 +99,25 @@ clocks { cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { #clock-cells = <0>; compatible = "fixed-clock"; + clock-frequency = <0>; }; cb_intosc_ls_clk: cb_intosc_ls_clk { #clock-cells = <0>; compatible = "fixed-clock"; + clock-frequency = <0>; }; f2s_free_clk: f2s_free_clk { #clock-cells = <0>; compatible = "fixed-clock"; + clock-frequency = <0>; }; osc1: osc1 { #clock-cells = <0>; compatible = "fixed-clock"; + clock-frequency = <0>; }; main_pll: main_pll@40 { From patchwork Tue Oct 29 20:23:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13855373 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3A2220A5FF; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:07 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 09/23] ARM: dts: socfpga: add ranges property to sram Date: Tue, 29 Oct 2024 20:23:35 +0000 Message-Id: <20241029202349.69442-10-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add 'ranges' to the SRAM node as it is a required property by the dtschema. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 5f4bed187..6a2ecc7ed 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -691,6 +691,7 @@ ocram: sram@ffe00000 { #address-cells = <1>; #size-cells = <1>; reg = <0xffe00000 0x40000>; + ranges; }; eccmgr: eccmgr { From patchwork Tue Oct 29 20:23:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13855374 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3618420ADEA; Tue, 29 Oct 2024 20:24:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233453; cv=none; b=uenXZlmRpEaT78/sRjAVX+UaeTfB3LVE3LZLxnK20MBOJhSdelpx1FfM4uXwfaBT7Yrlv3u1Zq+RnXfMlHG1BxqvYVBPqlZz7ZEfpG3u0QvFEpnBq1slZP+04uvUWPtdhyf5Hf1bAEZO/gvuFFPHnGmg0wgUjH8MfJXLvZXVQ8g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233453; c=relaxed/simple; bh=GRIprTk55YoxyAtAqBSmeVlFwn+FJRp9HdXHznTSR8s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hhH5HUM8Y0EX5Pv+8SYKO3JYfo7CUZ7xE9xnabYV7GRLRqIguw7thDGh9WMPL8z1ObJ0oVTOy+KE30CPOJiq2aR1xDRtNGS3qjowhJSlSQp/j9kctqSB2KULyAGjY5PGT4llbiMD1/Y1ZvvS2QwHnq6CvztaXbVoKeYSdI5mBc0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=b2Qq838J; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="b2Qq838J" Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-37d450de14fso530055f8f.2; Tue, 29 Oct 2024 13:24:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730233449; x=1730838249; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vySvn0PrZ5KmWWRcUjB0f7ffbO3G5ojONpptbAIcwaU=; b=b2Qq838JE0H88FpiqeV3bkkHVchB1tQ+CoprqhVliecg0yqZRnrUr+0OmIrrYU0IMC zWScm1oM0SPgT+MBff0d+9zctiLoEBSCCC73adxqJuss3BLaPRGyx3bVL1p4nsB/7cir 0XlaCPZNRtcwPQcx+uWsNbx5Vvvyx0CJYhlAUrsdWUnrZWO9ZvCczUbCuKaY8EtjMYXs zvmNqCFojRmEXvxnTxUrB3sttoNM/1tGvh6WHOc/FbaGHwpsSkCxxGDJYSYq/bgDEPjp na+8VHi38ddndSbLJ8R3oor6PjfBY+3syrWoed4iyxMLdZDTLQ7ooHcyNd/BBaPd/rQu oSaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730233449; x=1730838249; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vySvn0PrZ5KmWWRcUjB0f7ffbO3G5ojONpptbAIcwaU=; b=cO7+M3uNyLX+Wvf1qwHaSMskcsBSqZxN4vLJSSvMrDzN/fiL0j+2SV9ynqAF+/qkS9 PjrFHTThxyK2jfbngbDBnyM3eV/3bGAk5+zFb+LLJYwxX6SCpRAJ5euMMS8qRjYiBCPQ MFTtm8ftxborzlm8qYbHXRDb4wWf8mmcdVdEQySOthHuxDdAMMNgCVGCUjo6bSM104vO o7/u0s1NyM9WlI8xLcdrSgbAOuXpz7aQG5KbdDkw4/tj9kmxk2T75qXyg1znJUScJLJB 7+hfanI6nDAsxo/5yXxhqPWq37ae1c7QLRM4rxg1Rz1dtq6u0/VAiO5L6286DR5uENZj O7Tw== X-Forwarded-Encrypted: i=1; AJvYcCUGuO+bXduKIKQ/SFEqi9m9gGwfjCkkrF4ylhaQyhTzkce3SkclDQTk6hI8ER32nkRffutefnok@vger.kernel.org, AJvYcCWKrFrlEhWIJ26lMc9CTSdr9dmID5GOhm15Bvr4yIFyyefcxXf7W5Tju/ElWYVKOM9AVDFinOB6dneizK8P@vger.kernel.org, AJvYcCXvlOaUi9T7KwxCL/sDHgV3sINf4vcISv3qfSihqXz9XJDxTkDktcuSxMjsho/fLKi8z7gx8AG2958e@vger.kernel.org X-Gm-Message-State: AOJu0Yzh+rcv8Mzc7/T6QxXU3a0mdpgwIpe/cA1nt0ndyqqqRMob4qDN EaVuuS25xLfMjISsdZy8bdXyNigr34Maw5Ls5xHlS85gxWEMgI4q X-Google-Smtp-Source: AGHT+IFSpTV0Tj7I6mQHfK9STG9/cLahfdy+XF2noCCt0RfKclZZKLKsVyDf7dEs0S7eg2BUhcBLuA== X-Received: by 2002:a05:600c:45cf:b0:42c:aeee:d8ee with SMTP id 5b1f17b1804b1-4319ad4adc4mr46799135e9.8.1730233449432; Tue, 29 Oct 2024 13:24:09 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:09 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 10/23] ARM: dts: socfpga: remove arria10 reset-names Date: Tue, 29 Oct 2024 20:23:36 +0000 Message-Id: <20241029202349.69442-11-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Remove the reset-names since the binding does not mention them, and they seem not to be used in arria10 (similarily to agilex). Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 6a2ecc7ed..005c57843 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -818,7 +818,6 @@ timer0: timer0@ffc02700 { clocks = <&l4_sp_clk>; clock-names = "timer"; resets = <&rst SPTIMER0_RESET>; - reset-names = "timer"; }; timer1: timer1@ffc02800 { @@ -828,7 +827,6 @@ timer1: timer1@ffc02800 { clocks = <&l4_sp_clk>; clock-names = "timer"; resets = <&rst SPTIMER1_RESET>; - reset-names = "timer"; }; timer2: timer2@ffd00000 { @@ -838,7 +836,6 @@ timer2: timer2@ffd00000 { clocks = <&l4_sys_free_clk>; clock-names = "timer"; resets = <&rst L4SYSTIMER0_RESET>; - reset-names = "timer"; }; timer3: timer3@ffd00100 { @@ -848,7 +845,6 @@ timer3: timer3@ffd00100 { clocks = <&l4_sys_free_clk>; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:10 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 11/23] net: stmmac: add support for dwmac 3.72a Date: Tue, 29 Oct 2024 20:23:37 +0000 Message-Id: <20241029202349.69442-12-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org The dwmac 3.72a is an ip version that can be found on Intel/Altera Arria10 SoCs. Going by the hardware features "snps,multicast-filter-bins" and "snps,perfect-filter-entries" shall be supported. Thus add a compatibility flag, and extend coverage of the driver for the 3.72a. Signed-off-by: Lothar Rubusch --- drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c | 1 + drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c index 598eff926..b9218c07e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c @@ -56,6 +56,7 @@ static const struct of_device_id dwmac_generic_match[] = { { .compatible = "snps,dwmac-3.610"}, { .compatible = "snps,dwmac-3.70a"}, { .compatible = "snps,dwmac-3.710"}, + { .compatible = "snps,dwmac-3.72a"}, { .compatible = "snps,dwmac-4.00"}, { .compatible = "snps,dwmac-4.10a"}, { .compatible = "snps,dwmac"}, diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 54797edc9..e7e2d6c20 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -522,6 +522,7 @@ stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac) if (of_device_is_compatible(np, "st,spear600-gmac") || of_device_is_compatible(np, "snps,dwmac-3.50a") || of_device_is_compatible(np, "snps,dwmac-3.70a") || + of_device_is_compatible(np, "snps,dwmac-3.72a") || of_device_is_compatible(np, "snps,dwmac")) { /* Note that the max-frame-size parameter as defined in the * ePAPR v1.1 spec is defined as max-frame-size, it's From patchwork Tue Oct 29 20:23:38 2024 Content-Type: text/plain; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:12 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 12/23] dt-bindings: net: snps,dwmac: add support for Arria10 Date: Tue, 29 Oct 2024 20:23:38 +0000 Message-Id: <20241029202349.69442-13-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org The hard processor system (HPS) on the Intel/Altera Arria10 provides three Ethernet Media Access Controller (EMAC) peripherals. Each EMAC can be used to transmit and receive data at 10/100/1000 Mbps over ethernet connections in compliance with the IEEE 802.3 specification. The EMACs on the Arria10 are instances of the Synopsis DesignWare Universal 10/100/1000 Ethernet MAC, version 3.72a. Support the Synopsis DesignWare version 3.72a, which is used in Intel's Arria10 SoC, since it was missing. Signed-off-by: Lothar Rubusch Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 15073627c..d26bb77eb 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -26,6 +26,7 @@ select: - snps,dwmac-3.610 - snps,dwmac-3.70a - snps,dwmac-3.710 + - snps,dwmac-3.72a - snps,dwmac-4.00 - snps,dwmac-4.10a - snps,dwmac-4.20a @@ -88,6 +89,7 @@ properties: - snps,dwmac-3.610 - snps,dwmac-3.70a - snps,dwmac-3.710 + - snps,dwmac-3.72a - snps,dwmac-4.00 - snps,dwmac-4.10a - snps,dwmac-4.20a From patchwork Tue Oct 29 20:23:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13855377 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3B8720C027; Tue, 29 Oct 2024 20:24:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233458; cv=none; b=i74QBcqmqBmOkT81gw0LYPNa+NioHoVGCJu7oQ2OqI9ilqGBnM9/tXBH2AxP2/Ro1r9D+xAA6uII2CGutComXAlrzeoDPgxT0+W9ZzZD68HVBEo0XuxC0OTV6/8iVzYqSYj17tskLHYpIyASuBVccPfjAMgAt6HSTLEoaPXBanA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233458; c=relaxed/simple; bh=uNUTiA0HvI5A7c5xE1I8y5ErznWdRKyRHGjQDeKPcAA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bfBbmNhGLKFWmd/rAcuXHwuF11knlTq/1qPTh78YVAdwNG6kPeDMbWyhvOJzasm/ona6zvSWa3bQ6JKmOuwZr2mzdlw+XgOCwu94YRCO4BosRvAwMIEfuH2qLznS3oVi7piR5ayA9I5vX3WsIMXKHkK9FzNBhkniuIK+RoIRMXo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NO39j7PB; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NO39j7PB" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-37d4fa7d3baso658447f8f.0; Tue, 29 Oct 2024 13:24:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730233455; x=1730838255; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rx0eMLUEzhYETTDB2Dx4nHIilzNRVf/VQgEFIdoul78=; b=NO39j7PB/Vs+r84wf8v/+SXBuBtfXl315WcBxSbXk7GdJzl+5lZBMOjJFFM/APF+pG VJgv5yYfGYlfEiAnH7ce/KzVAU9VtC/uB+7fIP/Dys8Twz24nCKEO1nZXJpLwsNeFy5d Lly0Hmp+TDN/COWQoVd28M7cr5xB1rNU224yRDDeBTan1/LH8eWttv55ucSGYAefg1na 8F/X2HlEs1VuMuBHpTc8dVN+3PMntDMMXSRzW2qYUOmU6c+muJTpjCvNCp6g5HgcS5RI JVuBYRKIfuNeHWaSKPEuK67VZG0zqZ21dfq6dEc6KCg7eCpQHaYXW6XArLB0KysKI3Si LO6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730233455; x=1730838255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rx0eMLUEzhYETTDB2Dx4nHIilzNRVf/VQgEFIdoul78=; b=Al9gfyEF5J2z2xuAQobFVSmpOKi54uKgIXhJj9CGvqEo/+yVGcGn3Ykir8wxK0a29I 8vo6NACUIaNLOYvTJ3QsTbZgss3q7rOdKuafqJeOqCpCKPxBAqftT8F6FHudsPIO25X8 d5GUMv0fKOcSCz6tyV73duLCVcOwa5gu8DjKFyKAdtL0OPWQrXw97Apo2Lsj+cTKq4OA eJ9xoUzv2qF/F/VCYz2lh5dcqYghWvTLNKWCovwUd3DlwCfL0EXzTrBJtFu4TxNdhUsw s6FRVGDr1viyvA6KwZsBds1Fm7fPrEL+K7UUla5BNff8Ua/5GgWVNk5xm9qVVMoSBASC lmRg== X-Forwarded-Encrypted: i=1; AJvYcCVHnAzXiOtA3tjAvJ/vTGqn0I6rrMKvFiOWmFTAgKF4/GoBnE0Ia+3sme+dCQj4JTr7gdNSIHAx@vger.kernel.org, AJvYcCVt+yG801PDHtWnIJCHk8zy+Vjf+0sHkbhAmA1xeB5MGZGYMglI/ieP6ChUMOHl0e5g0aJ4h4tOm0cjOnQS@vger.kernel.org, AJvYcCWbpWBMhJHN0aTG+hqKTugvLNWetyYE4+a+ZIttBsy82euuj2dGBL8zdspLhFZA2+AwI46inff6AFND@vger.kernel.org X-Gm-Message-State: AOJu0YxopKp5g//bApXJl2/f46V5WXnGFFXxptFgfYFghDpiDT2tSIEO /65ypG+E9CWydSuHfdpve7Wx2jVSso4EhprzPvi9MIQETc57/Rko X-Google-Smtp-Source: AGHT+IEnuFjr/Zc4f6jXZAW8xbcExw/fgwTtYOC4EmQWOqcT/pxDPVKNa5Oe0HscWQqMZwS60H9tkw== X-Received: by 2002:a5d:47c2:0:b0:374:ca43:ac00 with SMTP id ffacd0b85a97d-38061126ae4mr3904749f8f.4.1730233454663; Tue, 29 Oct 2024 13:24:14 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:14 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 13/23] ARM: dts: socfpga: add Enclustra boot-mode dtsi Date: Tue, 29 Oct 2024 20:23:39 +0000 Message-Id: <20241029202349.69442-14-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add generic boot-mode support to Enclustra Arria10 and Cyclone5 boards. Some Enclustra carrier boards need hardware adjustments specific to the selected boot-mode. Enclustra's Arria10 SoMs allow for booting from different media. By muxing certain IO pins, the media can be selected. This muxing can be done by gpios at runtime e.g. when flashing QSPI from off the bootloader. But also to have statically certain boot media available, certain adjustments to the DT are needed: - SD: QSPI must be disabled - eMMC: QSPI must be disabled, bus width can be doubled to 8 byte - QSPI: any mmc is disabled, QSPI then defaults to be enabled The boot media must be accessible to the bootloader, e.g. to load a bitstream file, but also to the system to mount the rootfs and to use the specific performance. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga_enclustra_mercury_bootmode_emmc.dtsi | 12 ++++++++++++ .../socfpga_enclustra_mercury_bootmode_qspi.dtsi | 8 ++++++++ .../socfpga_enclustra_mercury_bootmode_sdmmc.dtsi | 8 ++++++++ 3 files changed, 28 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi new file mode 100644 index 000000000..d79cb64da --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&qspi { + status = "disabled"; +}; + +&mmc { + bus-width = <8>; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi new file mode 100644 index 000000000..5ba21dd8f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&mmc { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi new file mode 100644 index 000000000..2b102e0b6 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&qspi { + status = "disabled"; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:15 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 14/23] ARM: dts: socfpga: add Enclustra base-board dtsi Date: Tue, 29 Oct 2024 20:23:40 +0000 Message-Id: <20241029202349.69442-15-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add generic Enclustra base-board support for the Mercury+ PE1, the Mercury+ PE3 and the Mercury+ ST1 board. The carrier boards can be freely combined with the SoMs Mercury+ AA1, Mercury SA1 and Mercury+ SA2. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga_enclustra_mercury_pe1.dtsi | 33 +++++++++++ .../socfpga_enclustra_mercury_pe3.dtsi | 55 +++++++++++++++++++ .../socfpga_enclustra_mercury_st1.dtsi | 15 +++++ 3 files changed, 103 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi new file mode 100644 index 000000000..abc4bfb7f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + status = "okay"; + + eeprom@57 { + status = "okay"; + compatible = "microchip,24c128"; + reg = <0x57>; + pagesize = <64>; + label = "user eeprom"; + address-width = <16>; + }; + + lm96080: temperature-sensor@2f { + status = "okay"; + compatible = "national,lm80"; + reg = <0x2f>; + }; + + si5338: clock-controller@70 { + compatible = "silabs,si5338"; + reg = <0x70>; + }; + +}; + +&i2c_encl_fpga { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi new file mode 100644 index 000000000..bc57b0680 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + i2c-mux@74 { + status = "okay"; + compatible = "nxp,pca9547"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@56 { + status = "okay"; + compatible = "microchip,24c128"; + reg = <0x56>; + pagesize = <64>; + label = "user eeprom"; + address-width = <16>; + }; + + lm96080: temperature-sensor@2f { + status = "okay"; + compatible = "national,lm80"; + reg = <0x2f>; + }; + + pcal6416: gpio@20 { + status = "okay"; + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; + +&i2c_encl_fpga { + status = "okay"; + + i2c-mux@75 { + status = "okay"; + compatible = "nxp,pca9547"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + }; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi new file mode 100644 index 000000000..4c00475f4 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + si5338: clock-controller@70 { + compatible = "silabs,si5338"; + reg = <0x70>; + }; +}; + +&i2c_encl_fpga { + status = "okay"; +}; From patchwork Tue Oct 29 20:23:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13855379 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21E9F20C47F; Tue, 29 Oct 2024 20:24:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233462; cv=none; b=PgXg8Hu2X3OTcuJAvavi5XVhxGKgG4QUpKjli7yEV7K8eax7sXBlr6/Rz6CAhJrt8e0+VpRkTr/9UuJP8/dm7HqDtVdjTfZK/z6WGqTL6+SzEdllkyN0NcBqMol6IryZnT6L8stUt5rDFMR26iXoTRQ+h4/RuphVHQPnvTOqsPI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233462; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:17 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 15/23] ARM: dts: socfpga: add Enclustra Mercury SA1 Date: Tue, 29 Oct 2024 20:23:41 +0000 Message-Id: <20241029202349.69442-16-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce support for Enclustra's Mercury SA1 SoM based on Intel Cyclone5 technology as a .dtsi file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga/socfpga_cyclone5_mercury_sa1.dtsi | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi new file mode 100644 index 000000000..2041088b7 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Enclustra Mercury SA1"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &gmac1; + }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc04000 { + }; + i2c_encl_fpga: i2c@ffc05000 { + }; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; +}; + +&osc1 { + clock-frequency = <50000000>; +}; + +&i2c_encl { + i2c-sda-hold-time-ns = <300>; + clock-frequency = <100000>; + status = "okay"; + + isl12020: rtc@6f { + compatible = "isil,isl12022"; + reg = <0x6f>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns = <300>; + status = "disabled"; +}; + +&uart0 { + clock-frequency = <100000000>; +}; + +&mmc0 { + status = "okay"; + /delete-property/ cap-mmc-highspeed; + /delete-property/ cap-sd-highspeed; +}; + +&qspi { + status = "okay"; + + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <10000000>; + + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@raw { + label = "Flash Raw"; + reg = <0x0 0x4000000>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + /delete-property/ mac-address; + phy-mode = "rgmii"; + phy-handle = <&phy3>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg = <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps = <1680>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + rxdv-skew-ps = <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps = <1860>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; + }; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; From patchwork Tue Oct 29 20:23:42 2024 Content-Type: text/plain; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:19 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v4 16/23] dt-bindings: altera: add Enclustra Mercury SA1 Date: Tue, 29 Oct 2024 20:23:42 +0000 Message-Id: <20241029202349.69442-17-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Update the DT binding for the Enclustra Mercury+ SA1 SoM Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 8c7575455..87a22d2a4 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -51,6 +51,16 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga + - description: Mercury SA1 boards + items: + - enum: + - enclustra,mercury-sa1-pe1 + - enclustra,mercury-sa1-pe3 + - enclustra,mercury-sa1-st1 + - const: enclustra,mercury-sa1 + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + - description: Stratix 10 boards items: - enum: From patchwork Tue Oct 29 20:23:43 2024 Content-Type: text/plain; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:21 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 17/23] ARM: dts: socfpga: add Enclustra Mercury+ SA2 Date: Tue, 29 Oct 2024 20:23:43 +0000 Message-Id: <20241029202349.69442-18-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce Enclustra's Mercury+ SA2 SoM based on Intel Cyclone5 technology as a .dtsi file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga/socfpga_cyclone5_mercury_sa2.dtsi | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi new file mode 100644 index 000000000..f46f1410f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Enclustra Mercury+ SA2"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &gmac1; + }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc04000 { + }; + i2c_encl_fpga: i2c@ffc05000 { + }; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x80000000>; /* 2GB */ + }; +}; + +&osc1 { + clock-frequency = <50000000>; +}; + +&i2c_encl { + i2c-sda-hold-time-ns = <300>; + clock-frequency = <100000>; + status = "okay"; + + isl12020: rtc@6f { + compatible = "isil,isl12022"; + reg = <0x6f>; + }; + + atsha204a: crypto@64 { + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns = <300>; + status = "disabled"; +}; + +&uart0 { + clock-frequency = <100000000>; +}; + +&mmc0 { + status = "okay"; +}; + +&qspi { + status = "okay"; + + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <10000000>; + + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@raw { + label = "Flash Raw"; + reg = <0x0 0x4000000>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + /delete-property/ mac-address; + phy-mode = "rgmii"; + phy-handle = <&phy3>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg = <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps = <1680>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + rxdv-skew-ps = <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps = <1860>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; + }; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; From patchwork Tue Oct 29 20:23:44 2024 Content-Type: text/plain; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:23 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v4 18/23] dt-bindings: altera: add binding for Mercury+ SA2 Date: Tue, 29 Oct 2024 20:23:44 +0000 Message-Id: <20241029202349.69442-19-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Update the device-tree binding for the Enclustra Mercury+ SA2 SoM. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 87a22d2a4..31af6859d 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -61,6 +61,16 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga + - description: Mercury+ SA2 boards + items: + - enum: + - enclustra,mercury-sa2-pe1 + - enclustra,mercury-sa2-pe3 + - enclustra,mercury-sa2-st1 + - const: enclustra,mercury-sa2 + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + - description: Stratix 10 boards items: - enum: From patchwork Tue Oct 29 20:23:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13855383 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CBA120E02F; Tue, 29 Oct 2024 20:24:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233469; cv=none; b=NekP8WnVE2PE/Lsi9FlJdXWSOLCVsTvhxxMMV5nakuLIqaIucOLxZbUBB0Gr9JNKgdsVpUWB381Ya461rCg/KE23tE+Fyj8wFBU+PFPpGmoXYEzpxU0nOUc/64DI6vlSRmUgIwuQyzr9DMCz3rHW71WmpQp5TqPMUNQChUt+VNI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233469; c=relaxed/simple; bh=GxNYh9AtD0jg7shj8J50zLay/5TG8a1ZXUimig9pYiY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZqQkCNug4wwVVrDxMqXwhpUFRoKemY+8Bo9I34tZIScgeAXRpKpKc0dIDHdQ8Pp/6YVft66DnIvOZLQgBTwwLO3UUrADcHFQXtcLJP6QnuWfPhenrTUVp8wC0o9XaAohXCGu1Ii3gzCw51QLUfgAjdHiK88wFAnmOPdKtSvNLOw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=YD7dZWmj; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YD7dZWmj" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-43158124a54so7106215e9.3; Tue, 29 Oct 2024 13:24:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730233465; x=1730838265; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qJYzgv7BpNS3X0anslX6neWR7MP+bzIdFazI1EGhk+Y=; b=YD7dZWmjpsMZQycqCj4Ax72ZUpU5Y+UT1XfAlyPCeTgWklFtqCBdFYlh6wHJuAy7gk 7UnN3z18jELoZ9EAU1hCu0jMpIRE40pVbY0QKEm+enRimLmxNWjtjdO7oANFLB1TwFKI C6XdIRGLTXWP5KrX3E8LqdhIQW2rJEgd0F+UgJe30N3ZRX9xqhpmbuHRms8O4z+PZ3T6 GdOlEqVRpwtxdbBurEbRBimaJ8Ioa8AFx6zTw2wYJM96zt7eBWbQBvLfDOQM+8HRb7bn g7J/IdTGoXRhYvO53ugLZaMNS1L4G7RlM8ZqgE7kHekR0G+9P7W+ITwSw6vJ/XcHgQ9c jK5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730233465; x=1730838265; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qJYzgv7BpNS3X0anslX6neWR7MP+bzIdFazI1EGhk+Y=; b=UVuyy4sSRAnuYh6lRMuuZ58t6jwhwkB/7+2YQiTR/zT44HzjrNwJ8PrRrx9VOPTan2 Eq27kJo01GlAqBxsUHGIJ7cTRV0bQtTBPHWESRvFziILc7oIMo+OOMBa1XQUrNnQgFTJ w/nWcaT3G5oyPAxEWY4KJy+Qit8pXBi6QvgWGKvti8OyE7I6Fvfq5jKba/Hp/YkKRkNI IXahYkprTXgQPYJMikbwkL/TZe6/h5XRgxrwnPUfVbsCqvM4i4JD1D9bGY4gfXkmkg7u z+o9x9ZI+tsofmOFwIJkxK/7kSQTTbOFqduOxmI25BkWszHznHu8HT2c0xC7R7rutNVn pq4g== X-Forwarded-Encrypted: i=1; AJvYcCUcjMR25Kdx5bwQJPVRxAiQAVga7kT5oQqK/rLq4oRhg7RnZfbPNHdt1o+dpvbGQfKHjAGNexdzJ9J8aPuC@vger.kernel.org, AJvYcCWA4v89TiuYiToPDUTIFS/PlUuNpsihAElbQnitMdcyia3ClGOFgdIOaXawDMfqm6U4YUeRpcAd@vger.kernel.org, AJvYcCWwnfyeBlnOin73If+VlfW0xDLpkAuW0IdXnn+ovA2OiSuHGLKjLoq3AzoqG99MP8qfubXtgW381tb9@vger.kernel.org X-Gm-Message-State: AOJu0YyFhrdpQRhiRYcyy4VJaAwJYxdZYJPQcBhpZ+DMufor8VIkrM1x P8ut/8Jz8FAbahlbKOLcwdzQiW0AXoLbk9punn0RRy8gdd1SX5lY X-Google-Smtp-Source: AGHT+IGRmWtXkT5jAPAXRCxV+0flfcZw0XykWsjSo1z4+Tq4K4M0238SRmf//mWNOkIOSWwEX17Vsg== X-Received: by 2002:a05:600c:190a:b0:431:4e73:a515 with SMTP id 5b1f17b1804b1-4319ac9ad38mr47697085e9.3.1730233465129; Tue, 29 Oct 2024 13:24:25 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:24 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 19/23] ARM: dts: socfpga: add Mercury AA1 combinations Date: Tue, 29 Oct 2024 20:23:45 +0000 Message-Id: <20241029202349.69442-20-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce support for Enclustra's Mercury+ AA1 SoM, based on Intel Arria10. This is a flexible approach to allow for combining SoM with carrier board .dtsi and boot-mode .dtsi in a device-tree file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga/socfpga_arria10_mercury_aa1.dtsi | 141 +++++++++++++++--- 1 file changed, 120 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi index 41f865c8c..41351d58f 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi @@ -7,12 +7,14 @@ / { - model = "Enclustra Mercury AA1"; - compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga"; + model = "Enclustra Mercury+ AA1"; + compatible = "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; aliases { ethernet0 = &gmac0; serial1 = &uart1; + spi0 = &qspi; }; memory@0 { @@ -24,52 +26,102 @@ memory@0 { chosen { stdout-path = "serial1:115200n8"; }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc02300 { + }; + i2c_encl_fpga: i2c@ffc02200 { + }; + }; +}; + +&i2c_encl { + status = "okay"; + i2c-sda-hold-time-ns = <300>; + clock-frequency = <100000>; + + atsha204a: crypto@64 { + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; + + isl12022: rtc@6f { + compatible = "isil,isl12022"; + reg = <0x6f>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns = <300>; + status = "disabled"; }; &gmac0 { + status = "okay"; phy-mode = "rgmii"; phy-addr = <0xffffffff>; /* probe for phy addr */ - max-frame-size = <3800>; - phy-handle = <&phy3>; + /delete-property/ mac-address; + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; phy3: ethernet-phy@3 { - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ + reg = <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps = <1680>; /* 780ps */ rxd0-skew-ps = <420>; /* 0ps */ rxd1-skew-ps = <420>; /* 0ps */ rxd2-skew-ps = <420>; /* 0ps */ rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <1860>; /* 960ps */ rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - reg = <3>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps = <1860>; /* 960ps */ + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + txen-skew-ps = <0>; /* -420ps */ }; }; }; -&i2c1 { - atsha204a: crypto@64 { - compatible = "atmel,atsha204a"; - reg = <0x64>; - }; +&gpio0 { + status = "okay"; +}; - isl12022: isl12022@6f { - compatible = "isil,isl12022"; - reg = <0x6f>; - }; +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&uart0 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; }; /* Following mappings are taken from arria10 socdk dts */ &mmc { + status = "okay"; cap-sd-highspeed; broken-cd; bus-width = <4>; @@ -79,3 +131,50 @@ &mmc { &osc1 { clock-frequency = <33330000>; }; + +&eccmgr { + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&qspi { + status = "okay"; + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <10000000>; + + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@raw { + label = "Flash Raw"; + reg = <0x0 0x4000000>; + }; + }; +}; + +&watchdog1 { + status = "disabled"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; From patchwork Tue Oct 29 20:23:46 2024 Content-Type: text/plain; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:27 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v4 20/23] dt-bindings: altera: add Mercury AA1 combinations Date: Tue, 29 Oct 2024 20:23:46 +0000 Message-Id: <20241029202349.69442-21-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Update binding with combined .dts for the Mercury+ PE1, PE3 and ST1 carrier boards with the Mercury+ AA1 SoM. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 31af6859d..51f10ff8e 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -32,6 +32,9 @@ properties: items: - enum: - enclustra,mercury-pe1 + - enclustra,mercury-aa1-pe1 + - enclustra,mercury-aa1-pe3 + - enclustra,mercury-aa1-st1 - google,chameleon-v3 - const: enclustra,mercury-aa1 - const: altr,socfpga-arria10 From patchwork Tue Oct 29 20:23:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13855385 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 867A520EA4F; Tue, 29 Oct 2024 20:24:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233472; cv=none; b=STdZKg87Ifjover9nf6aurfTAtFV1tpWeZMNmyEoO1SNHOiY+SS7H6Yi2vw5UygNFZNbEGL4809c7HUn9lYTIdIrzSpR64mFFkqYvf/DiMp9Dsw6k9NXebZU7xmZHlRkpvx49bQpXOgnSIHKeTQ8Z4qMXjXu02wHGx2B+4heDU0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233472; c=relaxed/simple; bh=yqFBZ5HwYNdpyrFZYRbb5VqKZv0W3oDP/XE4ZOzqORs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ik3/e8uZzjcLQ3xCnARciJWKp6OX+q2lEyIMK1trdjHAePe0jgtzO2Onkad6MsaR79hMmgyPmvrslQo3hpyrIuW+PavRR8bN+piPBbw8WXDSkdvOJskAcQxZwxpJKM/7Nx4NXWn109eSSr4ClXPp6X5eTFYRhmVgZEAf95ndhBo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KffcFfKy; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KffcFfKy" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-431506d4f3bso6272435e9.0; Tue, 29 Oct 2024 13:24:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730233469; x=1730838269; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y0rrp5xrTxl0hGh1RK0+7VZvEHCMBhzUuqSkpHc7vyU=; b=KffcFfKySkXxEP+7DJ+is8atSJgtRRsoDmKssFSFebAc5Pc0pya78EDpTVKl/ONGfh mY1p6UdHX7rIZCz3Gb19PIImD0bKRhS2Kz9vzHubeLjhCVCoSjCBZWc4QGJlqQQUqhPd TvbmTzcpBdtWk239CiKhxMSk25iTGjbWnW6T4AgpnyTz3S/D8/1ujIoP+Y1SUjV5OcUu wpcrtV56E3QfugevlK/4By32LJxpkZmTBde4rZ4o0GmpeEGE/MemiHuhS1igySmM0VjH J+5jwh+gR1h/NMoIb0zF7vtMbMCVV14whe/j0Nmdjs7VSydCrodndb55M+hqLwsOT2oV Dz8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730233469; x=1730838269; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y0rrp5xrTxl0hGh1RK0+7VZvEHCMBhzUuqSkpHc7vyU=; b=UykMUkPBsV3DSf9wzNrfvFCAqFEpbyvU9+IMvT13RzoHIqa+aDJy4HpvDrK75IaXMT RpZ7KXjDJkVSlg4ThLATKJp8wXWIXI4Kl/KM/YJsoiarjwUq+m/oQhD89WJbi2jipQIJ Hg2ZktwrTEzQydZikTU4IeOUCY8SKBBvOP6CMJFKc+Ov2xctJ5jz6bllUOc3oxRKdIDQ YTMmdrCpqQt058sE0vFsw7wvQ2MZhygscydFLpk3Bli7r6lcm+PqlJ5aIx1doKeV9fmF 49HKx1XWOYRBpavT7b99dBc673ukqaZ6bUy+n1JJkDWLTyFUffYrHhGPatS3n3H9AClp XGuQ== X-Forwarded-Encrypted: i=1; AJvYcCV10KDc1lQS78RrvbgknvGOWR5Hio8rMrxMldCA6IbgIJQPDZXphMKSkNKtQy87AJGNPQfjAy3i7amDOo7d@vger.kernel.org, AJvYcCWGMa24QYvcQIDU7SYmP/M0G7hHzIZc9praIf2aULismzLPhawhbGrt+EOyIDtF5BamxT1/Gn2y@vger.kernel.org, AJvYcCXgb/U/+qcmv869s1Y4ACemvRrT+omqWQ9c/gUXl54U/BF/KviRcqtW7kWoPO2wJ10TyIeCCrtUJU65@vger.kernel.org X-Gm-Message-State: AOJu0YxLiVstc3cScu1z2P4/iCDGWaQaKEuP8F7GzXMvJT8vWPP5eUif piWTL/Ap6Kx3HwXfnW7cYijv7dTZrQlMAKcrm/QBYdLsDE3vNptH X-Google-Smtp-Source: AGHT+IEhYwBOUVTvTj3Hj0ZMICPfIHBCtNgFSxbtpX78XFkcd9rCEeOvpqOMJ3bxsigpakj/rBHQPA== X-Received: by 2002:a05:600c:3b13:b0:431:55f3:d34b with SMTP id 5b1f17b1804b1-4319aca248dmr50351615e9.3.1730233468766; Tue, 29 Oct 2024 13:24:28 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:28 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 21/23] ARM: dts: socfpga: removal of generic PE1 dts Date: Tue, 29 Oct 2024 20:23:47 +0000 Message-Id: <20241029202349.69442-22-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Remove the older socfpga_arria10_mercury_pe1.dts, since it is duplicate, the hardware is covered by the combination of Enclustra's .dtsi files. The older .dts was limited to only the case of having an Enclustra Mercury+ AA1 on a Mercury+ PE1 base board, booting from sdmmc. This functionality is provided also by the generic Enclustra dtsi and dts files, in particular socfpga_arria10_mercury_aa1_pe1_sdmmc.dts. Since both .dts files cover the same, the older one is to e replaced in favor of the more modularized approach. Signed-off-by: Lothar Rubusch Acked-by: Steffen Trumtrar --- arch/arm/boot/dts/intel/socfpga/Makefile | 1 - .../socfpga/socfpga_arria10_mercury_pe1.dts | 55 ------------------- 2 files changed, 56 deletions(-) delete mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile index c467828ae..d95862e34 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -2,7 +2,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3.dtb \ - socfpga_arria10_mercury_pe1.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts deleted file mode 100644 index cf533f76a..000000000 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2023 Steffen Trumtrar - */ -/dts-v1/; -#include "socfpga_arria10_mercury_aa1.dtsi" - -/ { - model = "Enclustra Mercury+ PE1"; - compatible = "enclustra,mercury-pe1", "enclustra,mercury-aa1", - "altr,socfpga-arria10", "altr,socfpga"; - - aliases { - ethernet0 = &gmac0; - serial0 = &uart0; - serial1 = &uart1; - }; -}; - -&gmac0 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&mmc { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; From patchwork Tue Oct 29 20:23:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13855386 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1358020F5A3; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:29 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v4 22/23] dt-bindings: altera: removal of generic PE1 dts Date: Tue, 29 Oct 2024 20:23:48 +0000 Message-Id: <20241029202349.69442-23-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Remove the binding for the generic Mercury+ AA1 on PE1 carrier board. The removed Mercury+ AA1 on PE1 carrier board is just a particular setup case, which is actually replaced by the set of generic Mercury+ AA1 combinations patch. In other words a combination of a Mercury+ AA1 on a PE1 base board, with boot mode SD card is already covered by the generic AA1 combinations. There is no further reason to keep this particular case now in a redundantly. Thus the redundant DT setup is removed. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 51f10ff8e..1561f0164 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -31,7 +31,6 @@ properties: - description: Mercury+ AA1 boards items: - enum: - - enclustra,mercury-pe1 - enclustra,mercury-aa1-pe1 - enclustra,mercury-aa1-pe3 - enclustra,mercury-aa1-st1 From patchwork Tue Oct 29 20:23:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13855387 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4C4420F5D4; Tue, 29 Oct 2024 20:24:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233477; cv=none; b=oedckLabZk8Xfy/xvVz2HD7QtPKmGYVzkOgNrzwAJ/aWP8Y0gWSxvGAaDN+fXgOvvma7WInbZgvDDTrG2WI+RZ7oeJwXJvKCr2f3l5UE2oIFXku2oILQIuGl3xT8YPg6G33tLkbme5sat5NMkyQRf9eRoCUlCjU83D73Cz47iJM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730233477; c=relaxed/simple; bh=BKcROuWUYTw9JhFiD7stJcvz4b+0cKybV+ykIP65zt4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=F0YCBSS2FV0xR85w4nTL2pGH7Fhp5Klp9bD6l3xFoXSXXNqiniYjDeWop4q28c+bacmEFe8Ohk7N+LyRCiIybo86erft1hMncPokbGvgEOxU+dxxNtm0RrYzjEQvTOxXXFfju5wLt+pqWp3NghIVtPTbk8TTpIGtB6k61zInHeQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=GQnDnDGQ; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GQnDnDGQ" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-37d58a51fa5so503546f8f.1; Tue, 29 Oct 2024 13:24:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730233472; x=1730838272; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=58/Yp9z5BeuiNsOYUdEfHyKptWKflHI/Ww9dE/OYykM=; b=GQnDnDGQ2HK5FZ77PvVQLp96FKDs5vYzg/0VroyLVtlHW/C4LxXdkbOKMUnGLD9EyH GggZ3wuJwf5gYa+Emhxl93kY/uTonniNlm0SwQdrM8NM6PswVyWrSSC1XFaIyTSqJq5H V+VE/4e1SqYUuTy481eLFyAIXdoCTEOG9YYNQugCbDARjIMpgBSUPzByTB9g5UgDDDfm XKQkJltxcSrixdobZs/utPy22m3TfLNOSRocZRxP9EzPTFhkYWTS/RctBGgd50MJA1O+ 5SZGEPcncDpUraTtrLMAK6TVCtW/RfBbxe7v+HYSdrIogAbJrRPTi2KWshU7xBwfbC0v vYWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730233472; x=1730838272; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=58/Yp9z5BeuiNsOYUdEfHyKptWKflHI/Ww9dE/OYykM=; b=sVAvuEgiH4MHPAnMeHzrOA9NRp5JjXnw+s1U3/nfDoUB3e/TYSAYgJOWgewuHtk9Go Y5zQHuMX/NDgxnW6vMIIZt7/HVfr38lwgeVjPxThOEwaWTVb2K46eZufpPSA4rP7hq8L yUXWCc68+SJkmejy7dKUpLk20b1JBNxb3lhyWpK6+n2vN/mhb3Em0uTofyqTtIErWNyj JAVyY4uJdV/SoynfHPv8TIKmRpbML6pJsry6xw4NEXKIMnaa65iUVbTyho6hkm0V+SK7 KyRqEPiZNeYSICouJAIE902SRlJ38FQQE4QyuqW8JLDN84pWNr78yshlN4KH+lIgItjI 3uHg== X-Forwarded-Encrypted: i=1; AJvYcCWyC6tUEciBu2fBS4r1TS5BuqqbCZj+ROO4zT5nhCqGoNkdLcDNGwf68EKvwNEcoJ94/LLHMOxJ78xvYFsW@vger.kernel.org, AJvYcCXAEaa2rjJyF/JK87KkQf/k3uQndH1V4NwkrFCb/tRgeG5D5p3/lk+7/28YSLkIdv1GrDRfxUCzYSNs@vger.kernel.org, AJvYcCXaw1gIrV4C9b6oBDA2tptAdDXVsCs14ibZ+kMM5sRZ3raqMTJqLMk8+PUwCcIG2YnA1qrVD7KK@vger.kernel.org X-Gm-Message-State: AOJu0YwMtm8PB+xUZKasiJcm7GNIT0KWLCmF9Xq0RtNklTqnHEY62Os0 hizizuxNZi1WLoXsNrDL3xJ7/dAtKbR5PXO+Vysvh25syiXF0rHN X-Google-Smtp-Source: AGHT+IHUTIPntp80wlmsDSZsxnN4LdgLxCxHE5azOHJ+sZci6nyjaVWgArufst7Usgp1AAGI9yIUwA== X-Received: by 2002:a05:6000:186b:b0:378:955f:d244 with SMTP id ffacd0b85a97d-380612bdf5dmr4233334f8f.14.1730233471868; Tue, 29 Oct 2024 13:24:31 -0700 (PDT) Received: from 6c1d2e1f4cf4.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38058b3bf85sm13619976f8f.42.2024.10.29.13.24.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2024 13:24:31 -0700 (PDT) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 23/23] ARM: dts: socfpga: add Enclustra SoM dts files Date: Tue, 29 Oct 2024 20:23:49 +0000 Message-Id: <20241029202349.69442-24-l.rubusch@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com> References: <20241029202349.69442-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the approach to set up a combination of Enclustra's SoM on a carrier board and corresponding boot-mode as single device-tree target. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/Makefile | 24 +++++++++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe1_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe3_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe3_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_st1_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_st1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_pe1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_pe3_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_st1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts | 16 +++++++++++++ 25 files changed, 408 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile index d95862e34..861880560 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -2,6 +2,30 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3.dtb \ + socfpga_arria10_mercury_aa1_pe1_emmc.dtb \ + socfpga_arria10_mercury_aa1_pe1_qspi.dtb \ + socfpga_arria10_mercury_aa1_pe1_sdmmc.dtb \ + socfpga_arria10_mercury_aa1_pe3_emmc.dtb \ + socfpga_arria10_mercury_aa1_pe3_qspi.dtb \ + socfpga_arria10_mercury_aa1_pe3_sdmmc.dtb \ + socfpga_arria10_mercury_aa1_st1_emmc.dtb \ + socfpga_arria10_mercury_aa1_st1_qspi.dtb \ + socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_st1_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_st1_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_st1_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts new file mode 100644 index 000000000..b6cca0b5f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts new file mode 100644 index 000000000..6ad023477 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts new file mode 100644 index 000000000..653c9a865 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts new file mode 100644 index 000000000..ae9c7c6a2 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts new file mode 100644 index 000000000..c3a0c30a0 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts new file mode 100644 index 000000000..dc1e1ad20 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts new file mode 100644 index 000000000..61d5e4c85 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts new file mode 100644 index 000000000..a3b99c9b1 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts new file mode 100644 index 000000000..5deb289e2 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts new file mode 100644 index 000000000..85d6146da --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts new file mode 100644 index 000000000..770ab680a --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts new file mode 100644 index 000000000..990ca0fec --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts new file mode 100644 index 000000000..6c8fd5b0d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts new file mode 100644 index 000000000..329242607 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts new file mode 100644 index 000000000..1eb10b524 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts new file mode 100644 index 000000000..8c97b5b3a --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts new file mode 100644 index 000000000..e6d14b22e --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts new file mode 100644 index 000000000..beaeca94d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts new file mode 100644 index 000000000..6f79d9ed1 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts new file mode 100644 index 000000000..b94bd8baf --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible = "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts new file mode 100644 index 000000000..51fc4a229 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts new file mode 100644 index 000000000..e4209209f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible = "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts new file mode 100644 index 000000000..ab4549a0d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts new file mode 100644 index 000000000..ebe62879c --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model = "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible = "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +};