From patchwork Wed Oct 30 19:23:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13857107 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F433D6B6C4 for ; Wed, 30 Oct 2024 19:23:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3541010E7F4; Wed, 30 Oct 2024 19:23:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FY0LcecG"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0B00B10E0CA for ; Wed, 30 Oct 2024 19:22:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730316172; x=1761852172; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=feZrERrK12YXAKoW1Ul05/EjOHowxM+1fsbaeVQTZOE=; b=FY0LcecGLMlg/glM9xsMnpnGWVzcfs918fj/m54kc6U3eqjvG2pA43cg FXisJ2xOuMTnS6b2ao6wNSOn64o+a9QrZVomaJ0J0helRKcHqKZ+7PEwf utUKH/tfje+alp83zrOOh2UW3sgbhnQ0Jfq425UzcVsF1gdPWiu4dTmMZ D6Tc9+XtAoG0wpIYFnr9v44rbnPKSZTI2aAqJxsR12bHU26uC8DOB46KG 3lj3yMvU1ChpBw2Nxg7HmXC3xhd1jgnTXYPoKQKsFwsIpWXeIE8ObJkpS NuENz5YUjTEy4KKwZS7YFI5RBnF5V4+4O49AJJ6CdNiE3KhyCygw8x4lw Q==; X-CSE-ConnectionGUID: GqfmpXvqQ427Y9qYjY2vWg== X-CSE-MsgGUID: Um4Pip7xRJuIIusSUyTjmw== X-IronPort-AV: E=McAfee;i="6700,10204,11241"; a="41435007" X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="41435007" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 12:22:42 -0700 X-CSE-ConnectionGUID: KH21p8LiRkSFq8n5kwyDvA== X-CSE-MsgGUID: XjMu2veZSDG4/f1YwviMGA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="82521942" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 12:22:41 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 1/5] drm/i915/ptl/dp_mst: Fix slave transcoder enabling wrt. DDI function Date: Wed, 30 Oct 2024 21:23:09 +0200 Message-ID: <20241030192313.4030617-2-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241030192313.4030617-1-imre.deak@intel.com> References: <20241030192313.4030617-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On PTL during modeset enabling configure the DDI function without enabling it for MST slave transcoders before programming the data and link M/N values. The DDI function gets enabled separately later in the transcoder enabling sequence. This fixes a slave transcoder getting stuck during enabling, leading to page flip timeout errors on the corresponding pipe. The spec requires the same programming step for ADLP+ platforms, that will be addressed separately (on those platforms the above transcoder getting stuck issue was not observed). Bspec: 68849 Signed-off-by: Imre Deak Reviewed-by: Luca Coelho --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_ddi.h | 2 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 2bd14e2134be9..069cca4b38b2e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -619,7 +619,7 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable * bit. */ -static void +void intel_ddi_config_transcoder_func(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index 6d85422bdefef..1aa2e3a190aee 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -57,6 +57,8 @@ void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, void intel_ddi_init(struct intel_display *display, const struct intel_bios_encoder_data *devdata); bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); +void intel_ddi_config_transcoder_func(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 1a2ff3e1cb68f..7c16406883594 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1224,6 +1224,9 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream) intel_ddi_enable_transcoder_clock(encoder, pipe_config); + if (DISPLAY_VER(dev_priv) >= 30 && !first_mst_stream) + intel_ddi_config_transcoder_func(encoder, pipe_config); + intel_dsc_dp_pps_write(&dig_port->base, pipe_config); intel_ddi_set_dp_msa(pipe_config, conn_state); } From patchwork Wed Oct 30 19:23:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13857102 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37337D6B6CC for ; Wed, 30 Oct 2024 19:22:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9EBE810E0CA; Wed, 30 Oct 2024 19:22:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="V41oPWjb"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2E33210E7EA for ; Wed, 30 Oct 2024 19:22:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730316172; x=1761852172; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=Lu4itYljrS3wlgYES/q6L0fS4p3bpUXoqzKJY7+k0kw=; b=V41oPWjbrxJr5MPPlAXlqxHL1f5zDaO42ZUsqbdz4VZnrM/e+iVt/Bx9 5cdq6FXYuOcE22b3f02PSXlVHQDfAPNyyqWQVUgfIfthJL4PqRBG1cfcr DBkAzsPg/GVUI2PQ10Zi03nsYV/kOauIN3MR1KEVM6X4mPOlnFsqRKGfg au3ipF1T1LJ6rYUYwrva9wxxBOPpPtCJYE0va6l9QhxUESM0jLoDj9nxo gsLkmVUvrrG/VDcCyABMecrqQ3lWQU0N7YpB1yTN1p/qoR2hAqnx9vFx5 AVCvoXVBAG3oY2ajdHkp5wjO2P42xGPVw01bxlIVZXalNXbREmmTcDitQ A==; X-CSE-ConnectionGUID: 7JwWWQsERC26gP0oZqcErQ== X-CSE-MsgGUID: sfTmmltnR1aFI2t+esOxTQ== X-IronPort-AV: E=McAfee;i="6700,10204,11241"; a="41435008" X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="41435008" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 12:22:43 -0700 X-CSE-ConnectionGUID: GlqcJ4/FRHqLTQOZZ501Kg== X-CSE-MsgGUID: azr4c8B9TRSZQ36h2aaA7A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="82521949" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 12:22:42 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 2/5] drm/i915/adlp+/dp_mst: Align slave transcoder enabling with spec wrt. DDI function Date: Wed, 30 Oct 2024 21:23:10 +0200 Message-ID: <20241030192313.4030617-3-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241030192313.4030617-1-imre.deak@intel.com> References: <20241030192313.4030617-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On ADLP+ during modeset enabling configure the DDI function without enabling it for MST slave transcoders before programming the data and link M/N values. The DDI function gets enabled separately later in the transcoder enabling sequence. Align the code with the spec based on the above. v2: Move this patch earlier in the series, addressing the DP2 config fixes for all ADLP+ platforms later. Bspec: 55424, 54128, 65448, 68849 Signed-off-by: Imre Deak Reviewed-by: Luca Coelho --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 7c16406883594..bf264bd1881b5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1224,7 +1224,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream) intel_ddi_enable_transcoder_clock(encoder, pipe_config); - if (DISPLAY_VER(dev_priv) >= 30 && !first_mst_stream) + if (DISPLAY_VER(dev_priv) >= 13 && !first_mst_stream) intel_ddi_config_transcoder_func(encoder, pipe_config); intel_dsc_dp_pps_write(&dig_port->base, pipe_config); From patchwork Wed Oct 30 19:23:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13857103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8692DD6B6C4 for ; Wed, 30 Oct 2024 19:22:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0DB3E10E7E8; Wed, 30 Oct 2024 19:22:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="LsptX0Rf"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id BAB6710E0CA for ; Wed, 30 Oct 2024 19:22:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730316172; x=1761852172; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Jejkoxck4xjSqARiiqXdaZqSa6nRul3iKsIkGmVlCQQ=; b=LsptX0RfZH78CHtgC2BBc6z/Fq3bPNAh+ZjSR35LpJWxm0M1CMVKa2r7 1dwlbBs2UP15LsCrk81Ew7qEt/47m3cc3d7OptBdVOLrv8CcmN56LH4Hv FMsTqFiLKFfjsNQC4HTPNkYx9dq5GfIO0q3iA1+WfP1wfxz5VKZZ4zrFu L4mUHsKt0guU+ebzFCiGME1fMa+2h9mtCT0wHHeQLlSZVDDOySBo1uFh1 1cjqMHJefyjlXc/mOsN2+HT7JpuUm9cp5kutPt7hNiLwLX+9B5VVY59Sr WKu47yM1GBnSv5fMthh6Ge0o3BDskRKobPSiDRr6ov6GeyryYFzEGYDVR g==; X-CSE-ConnectionGUID: lQL6q1dYTjKLf+cPN5j3dQ== X-CSE-MsgGUID: nUNfyY8WSvyXb3ph6v9k/Q== X-IronPort-AV: E=McAfee;i="6700,10204,11241"; a="41435010" X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="41435010" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 12:22:44 -0700 X-CSE-ConnectionGUID: hLKSlOc2SDClimzfakqy8w== X-CSE-MsgGUID: tS2MH927Rp6uIPYKe1WqXg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="82521966" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 12:22:43 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH v2 3/5] drm/i915/dp_mst: Add a way to disable the DP2 config Date: Wed, 30 Oct 2024 21:23:11 +0200 Message-ID: <20241030192313.4030617-4-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241030192313.4030617-1-imre.deak@intel.com> References: <20241030192313.4030617-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a way to disable the DP2 configuration, required by the next patch during transcoder disabling. While at it drop the redundant encoder parameter. v2: - Keep intel_ddi_config_transcoder_dp2() static. (Jani) - Remove the encoder parameter. Cc: Jani Nikula Signed-off-by: Imre Deak Reviewed-by: Luca Coelho --- drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 069cca4b38b2e..dcd43087fa7ed 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -455,14 +455,18 @@ static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) } static void -intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, + bool enable) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(crtc_state); + struct drm_i915_private *i915 = to_i915(display->drm); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 val = 0; - if (intel_dp_is_uhbr(crtc_state)) + if (!HAS_DP20(i915)) + return; + + if (enable && intel_dp_is_uhbr(crtc_state)) val = TRANS_DP2_128B132B_CHANNEL_CODING; intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); @@ -2549,7 +2553,7 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, /* * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. */ - intel_ddi_config_transcoder_dp2(encoder, crtc_state); + intel_ddi_config_transcoder_dp2(crtc_state, true); /* * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST @@ -2686,8 +2690,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, */ intel_ddi_enable_transcoder_clock(encoder, crtc_state); - if (HAS_DP20(dev_priv)) - intel_ddi_config_transcoder_dp2(encoder, crtc_state); + intel_ddi_config_transcoder_dp2(crtc_state, true); /* * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST From patchwork Wed Oct 30 19:23:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13857105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B52BD6B6CC for ; Wed, 30 Oct 2024 19:23:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ADE8110E7ED; Wed, 30 Oct 2024 19:22:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="jQ+9RZ5t"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 19E7F10E7E8 for ; Wed, 30 Oct 2024 19:22:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730316172; x=1761852172; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=whKvvPrCY/6BHR1yNJyNq0UqmTfs3QlGKKVQsQPy2B8=; b=jQ+9RZ5tDaaa0zpVAsfcBdr/VTsip6zyO+GT4S2CqOHjOuCsT5f8lLvC rYTY+y0ePCETNKgFENR02y44drGc9dyWFzGU8Ws9wQTw2Or4yZHKu9ohl Ozz/Ny1P//nSxOUbR8CH6I6WnUqYWqAMC+9BlLi5lDkVFIJUNWhrFWis0 At4p6ojLSbFy8VK6j5AYDovpg4V3rhsCL5R/mqFxSE6zpNqeB/5N039KX vZmsGVy8NjKYZLXtvh7lcAXKDHw8ZkOQFR37hcVP61+0Y89UgjVYTfnkk lN42CcxEbBSRcSLkVmsEfBiEh2qrdyf0/ZcXa2GNAjyNo91wzVK4dUd3d g==; X-CSE-ConnectionGUID: UeSJTGmsRZKbKuZSzPwSDw== X-CSE-MsgGUID: ARUKKrihRgaRrmCetKcfXg== X-IronPort-AV: E=McAfee;i="6700,10204,11241"; a="41435013" X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="41435013" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 12:22:45 -0700 X-CSE-ConnectionGUID: 8VXBGl3jTTiCCJo0WvKbCw== X-CSE-MsgGUID: eNumDkY7TLas7PXfEqJaAg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="82521973" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 12:22:44 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH v2 4/5] drm/i915/adlp+/dp_mst: Align slave transcoder sequences with spec wrt. DP2 config Date: Wed, 30 Oct 2024 21:23:12 +0200 Message-ID: <20241030192313.4030617-5-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241030192313.4030617-1-imre.deak@intel.com> References: <20241030192313.4030617-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On ADLP+ during modeset enabling and disabling, enable and disable the DP2 configuration for MST slave transcoders as required by the specification. Update the documentation of intel_ddi_config_transcoder_func() / intel_ddi_disable_transcoder_func() based on the above. While at it also clarify the programming steps of these functions specific to transcoder types. v2: - Enable/disable the DP2 config from intel_ddi_config_transcoder_func()/intel_ddi_disable_transcoder_func(). (Jani) - Handle all ADLP+ platforms in one patch, instead of doing that separately wrt. PTL. Bspec: 55424, 54128, 65448, 68849 Cc: Jani Nikula Signed-off-by: Imre Deak Reviewed-by: Luca Coelho --- drivers/gpu/drm/i915/display/intel_ddi.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index dcd43087fa7ed..d82bc1bf8b68f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -621,7 +621,8 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, /* * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable - * bit. + * bit for the DDI function and enables the DP2 configuration. Called for all + * transcoder types. */ void intel_ddi_config_transcoder_func(struct intel_encoder *encoder, @@ -632,12 +633,20 @@ intel_ddi_config_transcoder_func(struct intel_encoder *encoder, enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 ctl; + intel_ddi_config_transcoder_dp2(crtc_state, true); + ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); ctl &= ~TRANS_DDI_FUNC_ENABLE; intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), ctl); } +/* + * Disable the DDI function and port syncing. + * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, + * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master + * transcoders these are done later in intel_ddi_post_disable_dp(). + */ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -674,6 +683,9 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), ctl); + if (intel_dp_mst_is_slave_trans(crtc_state)) + intel_ddi_config_transcoder_dp2(crtc_state, false); + if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); @@ -2552,10 +2564,6 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, /* * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. - */ - intel_ddi_config_transcoder_dp2(crtc_state, true); - - /* * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST * Transport Select */ @@ -2690,8 +2698,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, */ intel_ddi_enable_transcoder_clock(encoder, crtc_state); - intel_ddi_config_transcoder_dp2(crtc_state, true); - /* * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST * Transport Select From patchwork Wed Oct 30 19:23:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13857106 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9755D6B6C4 for ; Wed, 30 Oct 2024 19:23:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 169A210E7EF; Wed, 30 Oct 2024 19:23:00 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="W92Oq3Wd"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 42CA010E0CA for ; Wed, 30 Oct 2024 19:22:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730316172; x=1761852172; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=FNlTS61oeuP+rVgSex5iU7wcpaICs5crDDvfQ8lNTpE=; b=W92Oq3Wdwi//Y3VaY0vYwbS7YJXHfbGBhccutCm/9HJsTS1PS8Ka+oSz v7BIORxDLLisJXyEyXKgL+J0WUBM354e+3aMH0pK7nf0iCtKNB4PQfyiQ qZfD4OVD33nQJD3gDxhtTJfKKPhaU95KC0SeBt04vEB9IHEhswp4Csuaw s5BqXiU2fIhYS+GF5utktEspH6q/dKLxKQ1qlOsTlvUjo3EIxfez0LlG1 0XVBazeg4aTVT/gDMc3gMBoO8NRm2Xr/hSWimhzp/SJWWEbrBivrpqAXQ 56VBY386K44rkd/JAmJGyPkbgXjpwULVBk0ii28iLeIHF1NZSWiPsT7qe Q==; X-CSE-ConnectionGUID: uwmmVxgwT1mBTB7iAIYKKA== X-CSE-MsgGUID: 2AzG8GdSTXaFiUO1rQmokg== X-IronPort-AV: E=McAfee;i="6700,10204,11241"; a="41435015" X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="41435015" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 12:22:46 -0700 X-CSE-ConnectionGUID: A88vYYHLTB27lf499YM7Cw== X-CSE-MsgGUID: mwfY++7mS5KjkqTLDd1kFg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="82521976" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 12:22:45 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 5/5] drm/i915/adlp+/dp_mst: Align master transcoder disabling with spec wrt. DP2 config Date: Wed, 30 Oct 2024 21:23:13 +0200 Message-ID: <20241030192313.4030617-6-imre.deak@intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20241030192313.4030617-1-imre.deak@intel.com> References: <20241030192313.4030617-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On ADLP+ during modeset disabling, disable the DP2 configuration for MST master transcoders as required by the specification. Bspec: 55424, 54128, 65448, 68849 Signed-off-by: Imre Deak Reviewed-by: Luca Coelho --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index d82bc1bf8b68f..6adbc7d0b90d9 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3062,6 +3062,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); + intel_ddi_config_transcoder_dp2(old_crtc_state, false); + /* * From TGL spec: "If single stream or multi-stream master transcoder: * Configure Transcoder Clock select to direct no clock to the