From patchwork Tue Mar 12 09:05:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 10848791 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9798C1850 for ; Tue, 12 Mar 2019 09:04:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 84D5929416 for ; Tue, 12 Mar 2019 09:04:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 791912948E; Tue, 12 Mar 2019 09:04:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1F1D429416 for ; Tue, 12 Mar 2019 09:04:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727546AbfCLJEn (ORCPT ); Tue, 12 Mar 2019 05:04:43 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:52068 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727639AbfCLJEm (ORCPT ); Tue, 12 Mar 2019 05:04:42 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2C94TUG082137; Tue, 12 Mar 2019 04:04:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1552381470; bh=bsWvIBnAG9ndj75Mz58Sr12fO0SUQ8YBixeuLbEaHCg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dTHFmOa4MYNX7HOZu5qGF6r2GnLrWcvLB5eWN0DGnxcMySqr10jJ9Ae3OOd4PJFsy 7zlG8+QiUkQ/Uaoj+7pBRi/HIE+HToyqsVTB7ULmOayHY2N1jaZFkem8UEKDcWLi9Y dj5pD+w65Sa3MOUzawgwVSbZGyNU+/3jA9rqRV+0= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2C94Tlj004583 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Mar 2019 04:04:29 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Tue, 12 Mar 2019 04:04:29 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Tue, 12 Mar 2019 04:04:29 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2C94Lfr016945; Tue, 12 Mar 2019 04:04:26 -0500 From: Vignesh Raghavendra To: Michael Turquette , Stephen Boyd , Rob Herring , Santosh Shilimkar CC: , , , , Nishanth Menon , Tero Kristo , Linux ARM Mailing List Subject: [PATCH 1/2] dt-bindings: clock: Add binding documentation for TI syscon gate clock Date: Tue, 12 Mar 2019 14:35:17 +0530 Message-ID: <20190312090518.28666-2-vigneshr@ti.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190312090518.28666-1-vigneshr@ti.com> References: <20190312090518.28666-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add dt bindings for TI syscon gate clock. Signed-off-by: Vignesh Raghavendra --- .../bindings/clock/ti,syscon-gate-clock.txt | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti,syscon-gate-clock.txt diff --git a/Documentation/devicetree/bindings/clock/ti,syscon-gate-clock.txt b/Documentation/devicetree/bindings/clock/ti,syscon-gate-clock.txt new file mode 100644 index 000000000000..f2bc4281ddba --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,syscon-gate-clock.txt @@ -0,0 +1,35 @@ +TI syscon gate clock + +The gate clock node must be provided inside a system controller node. + +Required: +- comaptible: Must be "ti,syscon-gate-clock" +- reg: Offset of register that controls the clock within syscon regmap +- ti,clock-bit-idx: bit index that control gate/ungating of clock +- clocks: phandle to the clock parent +- #clock-cells: must be <0> + +Example: + ctrlmmr_epwm_ctrl: syscon@104140{ + compatible = "syscon", "simple-bus"; + reg = <0x0 0x104140 0x0 0x18>; + ranges = <0x0 0x0 0x104140>; + #address-cells = <1>; + #size-cells = <0>; + + ehrpwm0_tbclk: clk@0 { + compatible = "ti,syscon-gate-clock"; + reg = <0x0>; + #clock-cells = <0>; + clocks = <&k3_clks 40 0>; + ti,clock-bit-idx = <0>; + }; + + ehrpwm1_tbclk: clk@4 { + compatible = "ti,syscon-gate-clock"; + reg = <0x4>; + #clock-cells = <0>; + clocks = <&k3_clks 41 0>; + ti,clock-bit-idx = <0>; + }; + }; From patchwork Tue Mar 12 09:05:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 10848787 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B978C1850 for ; Tue, 12 Mar 2019 09:04:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A4E6429416 for ; Tue, 12 Mar 2019 09:04:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 98B722941D; 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Tue, 12 Mar 2019 04:04:29 -0500 From: Vignesh Raghavendra To: Michael Turquette , Stephen Boyd , Rob Herring , Santosh Shilimkar CC: , , , , Nishanth Menon , Tero Kristo , Linux ARM Mailing List Subject: [PATCH 2/2] clk: keystone: Add new driver to handle syscon based clock Date: Tue, 12 Mar 2019 14:35:18 +0530 Message-ID: <20190312090518.28666-3-vigneshr@ti.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190312090518.28666-1-vigneshr@ti.com> References: <20190312090518.28666-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On TI's K2 and K3 SoCs, certain clocks can be gated/ungated by setting a single bit in SoC's System Control Module registers. Sometime more than one clock control can be in the same register. Add driver to support such clocks. Registers that control clocks will be grouped into a syscon regmap. Each clock node will be child of the syscon node. Signed-off-by: Vignesh Raghavendra --- drivers/clk/keystone/Kconfig | 8 ++ drivers/clk/keystone/Makefile | 1 + drivers/clk/keystone/syscon-clk.c | 143 ++++++++++++++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 drivers/clk/keystone/syscon-clk.c diff --git a/drivers/clk/keystone/Kconfig b/drivers/clk/keystone/Kconfig index b04927d06cd1..6a7b80ee62c9 100644 --- a/drivers/clk/keystone/Kconfig +++ b/drivers/clk/keystone/Kconfig @@ -14,3 +14,11 @@ config TI_SCI_CLK This adds the clock driver support over TI System Control Interface. If you wish to use clock resources from the PMMC firmware, say Y. Otherwise, say N. + +config TI_SYSCON_CLK + tristate "Syscon based clock driver for K2/K3 SoCs" + depends on (ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST) && OF + default (ARCH_KEYSTONE || ARCH_K3) + help + This adds clock driver support for syscon based gate + clocks on TI's K2 and K3 SoCs. diff --git a/drivers/clk/keystone/Makefile b/drivers/clk/keystone/Makefile index c12593966f9b..30e481386316 100644 --- a/drivers/clk/keystone/Makefile +++ b/drivers/clk/keystone/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_COMMON_CLK_KEYSTONE) += pll.o gate.o obj-$(CONFIG_TI_SCI_CLK) += sci-clk.o +obj-$(CONFIG_TI_SYSCON_CLK) += syscon-clk.o diff --git a/drivers/clk/keystone/syscon-clk.c b/drivers/clk/keystone/syscon-clk.c new file mode 100644 index 000000000000..063a8e5df324 --- /dev/null +++ b/drivers/clk/keystone/syscon-clk.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ +// + +#include +#include +#include +#include +#include +#include +#include + +struct ti_syscon_gate_clk_priv { + struct clk_hw hw; + struct regmap *regmap; + u32 reg; + u32 idx; +}; + +static struct +ti_syscon_gate_clk_priv *to_ti_syscon_gate_clk_priv(struct clk_hw *hw) +{ + return container_of(hw, struct ti_syscon_gate_clk_priv, hw); +} + +static int ti_syscon_gate_clk_enable(struct clk_hw *hw) +{ + struct ti_syscon_gate_clk_priv *priv = to_ti_syscon_gate_clk_priv(hw); + + return regmap_write_bits(priv->regmap, priv->reg, priv->idx, + priv->idx); +} + +static void ti_syscon_gate_clk_disable(struct clk_hw *hw) +{ + struct ti_syscon_gate_clk_priv *priv = to_ti_syscon_gate_clk_priv(hw); + + regmap_write_bits(priv->regmap, priv->reg, priv->idx, 0); +} + +static int ti_syscon_gate_clk_is_enabled(struct clk_hw *hw) +{ + unsigned int val; + struct ti_syscon_gate_clk_priv *priv = to_ti_syscon_gate_clk_priv(hw); + + regmap_read(priv->regmap, priv->reg, &val); + + return !!(val & priv->idx); +} + +static const struct clk_ops ti_syscon_gate_clk_ops = { + .enable = ti_syscon_gate_clk_enable, + .disable = ti_syscon_gate_clk_disable, + .is_enabled = ti_syscon_gate_clk_is_enabled, +}; + +static int ti_syscon_gate_clk_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct ti_syscon_gate_clk_priv *priv; + struct device *dev = &pdev->dev; + struct clk_init_data init; + unsigned long flags = 0; + const char *parent_name; + struct clk *parent; + u32 idx; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regmap = syscon_node_to_regmap(of_get_parent(node)); + if (IS_ERR(priv->regmap)) { + if (PTR_ERR(priv->regmap) == -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_err(dev, "failed to find parent regmap\n"); + return PTR_ERR(priv->regmap); + } + + if (of_property_read_u32(node, "reg", &priv->reg)) { + dev_err(dev, "missing reg property\n"); + return -EINVAL; + } + + if (of_property_read_u32(node, "ti,clock-bit-idx", &idx)) { + dev_err(dev, "missing ti,bit-shift property\n"); + return -EINVAL; + } + priv->idx = BIT(idx); + + if (of_clk_get_parent_count(node) != 1) { + dev_err(dev, "must have clk parent\n"); + return -EINVAL; + } + + parent = devm_clk_get(dev, NULL); + if (IS_ERR(parent)) { + if (PTR_ERR(priv->regmap) == -EPROBE_DEFER) + return -EPROBE_DEFER; + return PTR_ERR(parent); + } + + parent_name = __clk_get_name(parent); + + init.name = devm_kasprintf(dev, GFP_KERNEL, "%pOFn:%04x:%d", + node, priv->reg, idx); + init.ops = &ti_syscon_gate_clk_ops; + init.flags = flags; + init.parent_names = &parent_name; + init.num_parents = 1; + + priv->hw.init = &init; + ret = devm_clk_hw_register(&pdev->dev, &priv->hw); + if (ret < 0) { + dev_err(dev, "failed to register clk err: %d\n", ret); + return ret; + } + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, priv); +} + +static const struct of_device_id ti_syscon_gate_clk_ids[] = { + { .compatible = "ti,syscon-gate-clock" }, + { } +}; +MODULE_DEVICE_TABLE(of, ti_syscon_gate_clk_ids); + +static struct platform_driver ti_syscon_gate_clk_driver = { + .probe = ti_syscon_gate_clk_probe, + .driver = { + .name = "ti-syscon-gate-clk", + .of_match_table = ti_syscon_gate_clk_ids, + }, +}; + +module_platform_driver(ti_syscon_gate_clk_driver); + +MODULE_ALIAS("platform:ti-syscon-gate-clk"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Syscon backed gate-clock driver"); +MODULE_AUTHOR("Vignesh Raghavendra ");