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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org RTC fields are located in bits [1:0]. Correct the _MASK and _SHIFT macros to use the appropriate mask and shift. Signed-off-by: Ley Foon Tan --- drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h index 28fff6cab812..dd21dcfbbab3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -394,8 +394,8 @@ static inline u32 mtl_chanx_base_addr(const struct dwmac4_addrs *addrs, #define MTL_OP_MODE_EHFC BIT(7) -#define MTL_OP_MODE_RTC_MASK 0x18 -#define MTL_OP_MODE_RTC_SHIFT 3 +#define MTL_OP_MODE_RTC_MASK GENMASK(1, 0) +#define MTL_OP_MODE_RTC_SHIFT 0 #define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT) #define MTL_OP_MODE_RTC_64 0 From patchwork Fri Nov 1 08:23:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 13858944 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8598E674BA for ; Fri, 1 Nov 2024 08:32:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:MIME-Version:Content-Type: Content-Transfer-Encoding:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3ocbx1Hu/tUzczwxjE82MMfg7v5PsTGIm9P4YuZg1qY=; b=Zz1APvfK0NJPduIO/yEC1Art1O ffjp8W8iSbqJpNqDBoVeYz1xBuRunk2RhhdOIboyRNyNafb8UPK4Xlft2Ce4dDtWDFTdDVZW9m74R UKmIQMAISXrkrGBj+Q/7SEC5nlFWsIaVR97plbAhS3iL9IE8cqO9Gw5Ep7CoyL1lP5zti8Okr5R8L Of8fHxFpDj9nwKQu7TZxlcI5GU5R5GPRsLNCRYgBU+Rrtc9TxvKT9IZwtJ7js8Y0LYvstI6h+IKKi 3Rj96aja7kUjgD0kc3xn5TtRZZxAw8KpCoapXjWysQnzw7HaYXq+D8k9NoOJZ0JjyhbdwdgAjmdml xFeM4uZg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t6n52-00000006HgW-0Rx8; Fri, 01 Nov 2024 08:32:28 +0000 Received: from mail-sh0chn02on20722.outbound.protection.partner.outlook.cn ([2406:e500:4420:2::722] helo=CHN02-SH0-obe.outbound.protection.partner.outlook.cn) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t6mx6-00000006G0Y-2xS5 for linux-arm-kernel@lists.infradead.org; Fri, 01 Nov 2024 08:24:17 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=PbY5wj1vyVuePk0j6K1AedbuRIybdzOvvgjgl8bKRLBcnu9DsW3VpPLDiuyHgpmRtD2r601DNqHupCMAV6UbjOWVt+iqj9ZolhKFMx8cP7pymPy5c9YMEIHlJU9l+Bn19GZlIyHnO8RbFXVQc0gkC2ccMGkvUx8yScIKOlxz05X0uKEf9iCx3dX3vV6UNhXP1YbwFS4fg1XCnT96DSXJ1Wg1G91GMahwaesountcb78ofyoQlEzqMiUbGsatVKVUTy6U5VrivJx9tqFGRW3ML+JU5PrSYyKdDXfDhTyS7nzvPuO3iq7y7qBcwhj4Psl6cCtTuKRVgaQ++52xtHZ7hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3ocbx1Hu/tUzczwxjE82MMfg7v5PsTGIm9P4YuZg1qY=; b=KWW6KqeYdS6WqO6j6RsN5ucBoyhVu7W0TlxZU6ehen8sDH7YoQ35C0xOXUtLU1ZwGAVtXkBvgs4chywsykdRG3/wki/WcgABOAzqRGu3xf8Y/Wt76mWwecZiqaSyWClJ1thc69DMf0WPiKStI9s9eXfY1D2vxvn/bmzXBtHWknSWxFkCIzfvk7dBN1CKGFfgbsRZA/mwX4VcetRRa84OidPMdC5BqDx/+SB9Rr4Wek+DNVwRaJKk0hvlTMsNVoXQNqJktvszbqACmB6cRXE/WtgVEoB1/OmrhcdbafTunQKrvSABRxRVnID5BAc86mYn4G8AQMKBcQG2Oy5GSQHTdA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:f::12) by ZQZPR01MB1107.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:f::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8069.27; Fri, 1 Nov 2024 08:24:06 +0000 Received: from ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn ([fe80::617c:34a2:c5bf:8095]) by ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn ([fe80::617c:34a2:c5bf:8095%4]) with mapi id 15.20.8069.016; Fri, 1 Nov 2024 08:24:06 +0000 From: Ley Foon Tan To: Alexandre Torgue , Jose Abreu , Andrew Lunn Cc: "David S . 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Signed-off-by: Ley Foon Tan --- drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c index 7c895e0ae71f..1be77d189ccb 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -266,7 +266,7 @@ static void dwmac4_dma_rx_chan_op_mode(struct stmmac_priv *priv, } else { pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode); mtl_rx_op &= ~MTL_OP_MODE_RSF; - mtl_rx_op &= MTL_OP_MODE_RTC_MASK; + mtl_rx_op &= ~MTL_OP_MODE_RTC_MASK; if (mode <= 32) mtl_rx_op |= MTL_OP_MODE_RTC_32; else if (mode <= 64) @@ -335,7 +335,7 @@ static void dwmac4_dma_tx_chan_op_mode(struct stmmac_priv *priv, } else { pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode); mtl_tx_op &= ~MTL_OP_MODE_TSF; - mtl_tx_op &= MTL_OP_MODE_TTC_MASK; + mtl_tx_op &= ~MTL_OP_MODE_TTC_MASK; /* Set the transmit threshold */ if (mode <= 32) mtl_tx_op |= MTL_OP_MODE_TTC_32; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, lftan.linux@gmail.com, leyfoon.tan@starfivetech.com Subject: [net-next v2 3/3] net: stmmac: dwmac4: Receive Watchdog Timeout is not in abnormal interrupt summary Date: Fri, 1 Nov 2024 16:23:36 +0800 Message-ID: <20241101082336.1552084-4-leyfoon.tan@starfivetech.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241101082336.1552084-1-leyfoon.tan@starfivetech.com> References: <20241101082336.1552084-1-leyfoon.tan@starfivetech.com> X-ClientProxiedBy: ZQ0PR01CA0015.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:5::9) To ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:f::12) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQZPR01MB0979:EE_|ZQZPR01MB1107:EE_ X-MS-Office365-Filtering-Correlation-Id: 4e61733a-76a1-4322-75b4-08dcfa4e8e5d X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|52116014|7416014|41320700013|38350700014; X-Microsoft-Antispam-Message-Info: /Xh5VepZfBhi5lvrZ2i7QqXO9Gap7MtUfsl/jCoeT4xTp3RizaIJL5bln56zMBOGqppx/UEOufi3YuRXpixON9VvpjQEc00dpNCTfi8Qsxupd/7iTr+mFC+4ZXXV/RVG81gIIBzzeM+oubgzvNC1Fy8AQkxvMujQubFlTj0Z0EvBNHp4j9U4NqrMjHfz3gI2PIXaEGCO9SUpXLFMDJD1iuZhRgugr51k+PVJW4PVRuRyibPSsIqEvQ+JZfExqryYUUbOGojLj6QzZL74vgIATT78i0KPCFPWKXilfSPuAF7aeGbWveFmywbVsQ3DZePBAFjPJtVKZZtopdJXge7bpfAo5BqDuPAsV2Iaux7QBfoSh08J5F5kewH3Jfb9BsFa6OU8MqjN7uIksbbQhx4AIPN0YpS4qCJtziIsFWHq0S29Ha9qgkGk/tRDxLx4m6lZV04wKouj7sqJI371HGEmNPsd9hNjUEkFdG4U58lTYc+D6PXZk88svJK78dvD1TM9XY29aswyICpYpVHro08qpQjM9go1c099MLTRr6HhR9bPjGBBOJMrEkAhssy9nURJ/3FuI4Kz7owlZC+v2Ep7fSXnfg0u8s3Hr1OjlPkGFeWkLHST1pmED0jVNoZZcn+Q X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(52116014)(7416014)(41320700013)(38350700014);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0lCT+H1hiyi50kWSAKXprcwYaU4Lnn79wnWppv8XURY4pA2rOsyacLrqEfu3Jr02tkk9Zc3XgFK0ORpuAXkDiYu6DTeZeHocDvzMupsnkJyoR1yY2A68708i6OJqXbOLb+hWWFi6FOs1jhh+z7Vgeiwr7tcvUBCx+u/CSe5kK5tIRFv8zypmJ/kuj7E1lAoWwfBhlFLn65iKU0Bmcgo5gr61BofRRmrUlO7p4ICPU6fyluVWo0M98UmaO7IsNZg5WgG5wnfT1OQ6P7IvxlbbQrfqun1LsA6tY1owKiBZrd55gcUXx0u0vHTRgUVmAct0II9o4P5HxmV0sbpKyj6NfWpmd0JxSqO/G8dF/BznJStNCkF9EYorRhtFrC20e41H4TaxgT4H6tEmXHOJkQGesY9BcwzB0UCh/UcsOKI6fR1XtADkkxbXLGJZ3NMJMGy8LZuSVZEZFBBPNM50B7oGvqgqAyzI1FuY9fjCvdGJqEA94JSEtEMvBHC0CkH9QRyqI4ddkpnKKYDs1PXe39ZRypccBc+ECv0sfeYbCToLQYKPHozF4t/kD2nHBWA0lBJ1Gb6b5wrOJQvJET29SIM5vd+WB1gb4w4MKe7as/4yGDMz0Qni1lfXR2owGYVdlr9TVVxuBTqsoMoE674DJWfVMi/X7LHB1N8UcmMfIj98HS0u1glLLiqNVB6M7gDq4QH0poRbJSB1Ifu5UoclWrjg5JWTd8LYVhCsF9B7/6QLlticJJjxnnf2c1pQoFjcRX1Z+yhWjfvRadRMWg/qVGKMuhabsxgavqk99TULtUBtRHSQUmoVfrehEXfonfHlHzZiV/OEtmorWSW6re0VUWNw/2XgIQF4QuM1Kuu9vNHvBKkaDA+w+J26+1Lbi736QWTSksP2fE26HxpKmPZb6YbEJtjrYUjDp6bqKo5ISdCFnqLsxWT/L8P9VLyAG8wfJC5amUvLM9ItKR1xEGX9e7nWk6fPZzsjO7R/Z7oo2QijhQXwUIpqPMGQ+MfrCyyGOKxG2dBb3i0G9yLRRdOFmlKq1DGy4OptLGPAvKB7sFpTDHDTbX1poxKF+R6974jlolcMTfdv8LExCRGGTdir+xuqIShKNddpA+FSco4PU25YYQlB+VulcO5d8xvBtZjcS4DzFo77+kfKePTs6BSxy/J5tmnY9wXUN5tXIkY6cwkRVvCs4C7GHxAX7XvE6IKMxF3IsNsoJm/FTxGTUhhvoYNdowjz9+jCruvQhFpBy7K4q57Wgylgr2Rkvo9leXuFh8uX9Efjh3zp9Wdd/1+VbkjhpwOlhKq937aCQPE2ddc+qQvISQBwPgeznto09ymeCV2JTaEQSX8EJvaMVuAkVJm90CwBlBs5eykBUkFqV6UU4zSyCDPJfmqdfECtELgASlJcw9ZEGRvhhUM78GPrV6N0QwdvuSIhCN6Pm43fDee/llwjzpvD9d0ODEAq7CUavq5VMZueGxuXiDOSXSey5q7S9PpSqVJ5A9tb6uMI5Ja3v1IzAKm2/+Afr0u60nLfYQ/I7CF15WXM3xK92Ev666HRztzXDcEFGiSy+rk3nxgJ2kiP7uiB4dzC9V4z8QqEDxHnKthNMNXLAdUw2E7+axLzP4J0Ueo8eqxsjt5vaq33Z+k= X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4e61733a-76a1-4322-75b4-08dcfa4e8e5d X-MS-Exchange-CrossTenant-AuthSource: ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Nov 2024 08:24:08.4598 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: fmjVpnnHtNK709rRLo/FCYxvzproSsPXhoTBCeCYSyuCeuGOq4ZhriJJ1eCnltShdMw/Mjl9iR78ZX6I2owZpVBvQYzL7R5xc77l0EVFSp4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQZPR01MB1107 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241101_012418_349920_6B2D55D0 X-CRM114-Status: UNSURE ( 8.57 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Receive Watchdog Timeout (RWT, bit[9]) is not part of Abnormal Interrupt Summary (AIS). Move the RWT handling out of the AIS condition statement. From databook, the AIS is the logical OR of the following interrupt bits: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context Descriptor Error Signed-off-by: Ley Foon Tan --- drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c index 0d185e54eb7e..57c03d491774 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c @@ -185,8 +185,6 @@ int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, x->rx_buf_unav_irq++; if (unlikely(intr_status & DMA_CHAN_STATUS_RPS)) x->rx_process_stopped_irq++; - if (unlikely(intr_status & DMA_CHAN_STATUS_RWT)) - x->rx_watchdog_irq++; if (unlikely(intr_status & DMA_CHAN_STATUS_ETI)) x->tx_early_irq++; if (unlikely(intr_status & DMA_CHAN_STATUS_TPS)) { @@ -198,6 +196,10 @@ int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, ret = tx_hard_error; } } + + if (unlikely(intr_status & DMA_CHAN_STATUS_RWT)) + x->rx_watchdog_irq++; + /* TX/RX NORMAL interrupts */ if (likely(intr_status & DMA_CHAN_STATUS_RI)) { u64_stats_update_begin(&stats->syncp);