From patchwork Tue Nov 5 07:15:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13862577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72683D1CA3A for ; Tue, 5 Nov 2024 07:16:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1A6C310E528; Tue, 5 Nov 2024 07:16:22 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ZGyTdz6j"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id C5D7910E528; Tue, 5 Nov 2024 07:16:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730790980; x=1762326980; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PJF8es8eRCBF+iotQytzntNbm7TyWQeMAoZ8oCX2PXo=; b=ZGyTdz6jVTIe0Evt2zIcyQUJDKyhSJMUbEWtuIsf9jrHZpmcFYj275ZW pA9e6DZdSVT8EGa0/f2GjHBG/Gh711NziAkZTHMHm8OatGMvoSgmu38mL NLP2aic7+Up7rZUTk0fOrVADLWBhk8wM192sEIwccfUDpBImNniIPJL6W u667oJqLhnC1kOltLZk0ouKU9JE0BDp2b3pPmDJfRR1FcK0FM6WvT/kWS nrJvzZdk+V9tDBz9gpfRq6aYUgdDYl7uWzPKgdTd9ZBE8ywVUVvPNBJAl gSDi+y0msvPfG0qbAK/H+Fy3ijI7h0mlNV7L/ytbQoLh7hjymH/D1H+Am Q==; X-CSE-ConnectionGUID: yDn9SXwUQM+4OPL/yyw6Qw== X-CSE-MsgGUID: s4pnISbtS5eFxVhiCrZqLQ== X-IronPort-AV: E=McAfee;i="6700,10204,11246"; a="34449542" X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="34449542" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 23:16:20 -0800 X-CSE-ConnectionGUID: WQ3jwFxiS9yk1GvTu+56Rg== X-CSE-MsgGUID: YG1dtlP5TeaGEN5a0FN7pg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="87835544" Received: from apaszkie-mobl2.apaszkie-mobl2 (HELO vgovind2-mobl3..) ([10.245.245.146]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 23:16:18 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, jani.nikula@intel.com, ville.syrjala@intel.com, jani.saarinen@intel.com Subject: [PATCH 1/8] drm/i915/display: update intel_enabled_dbuf_slices_mask to use intel_display Date: Tue, 5 Nov 2024 09:15:53 +0200 Message-Id: <20241105071600.235338-2-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105071600.235338-1-vinod.govindapillai@intel.com> References: <20241105071600.235338-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Update intel_enabled_dbuf_slices_mask to use intel_display instead of drm_i915_private object. This is a prepratory patch for the next patch in the series, where all intel_de_read calls in skl_watermarks.c are updated to use intel_display instead of drm_i915_private. Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +- drivers/gpu/drm/i915/display/skl_watermark.c | 9 +++++---- drivers/gpu/drm/i915/display/skl_watermark.h | 3 ++- 4 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 2766fd9208b0..62e0faffca40 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1090,7 +1090,7 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) u8 slices_mask; dev_priv->display.dbuf.enabled_slices = - intel_enabled_dbuf_slices_mask(dev_priv); + intel_enabled_dbuf_slices_mask(&dev_priv->display); slices_mask = BIT(DBUF_S1) | dev_priv->display.dbuf.enabled_slices; diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index f0131dd853de..f792db191fcf 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -973,7 +973,7 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) { - u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv); + u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(&dev_priv->display); u8 enabled_dbuf_slices = dev_priv->display.dbuf.enabled_slices; drm_WARN(&dev_priv->drm, diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 3b0e87edbacf..d9d7238f0fb4 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -52,13 +52,13 @@ struct skl_wm_params { u32 dbuf_block_size; }; -u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915) +u8 intel_enabled_dbuf_slices_mask(struct intel_display *display) { u8 enabled_slices = 0; enum dbuf_slice slice; - for_each_dbuf_slice(i915, slice) { - if (intel_de_read(i915, DBUF_CTL_S(slice)) & DBUF_POWER_STATE) + for_each_dbuf_slice(display, slice) { + if (intel_de_read(display, DBUF_CTL_S(slice)) & DBUF_POWER_STATE) enabled_slices |= BIT(slice); } @@ -3126,6 +3126,7 @@ void intel_wm_state_verify(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct skl_hw_state { @@ -3149,7 +3150,7 @@ void intel_wm_state_verify(struct intel_atomic_state *state, skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y); - hw_enabled_slices = intel_enabled_dbuf_slices_mask(i915); + hw_enabled_slices = intel_enabled_dbuf_slices_mask(display); if (DISPLAY_VER(i915) >= 11 && hw_enabled_slices != i915->display.dbuf.enabled_slices) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h index e73baec94873..990793e36272 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.h +++ b/drivers/gpu/drm/i915/display/skl_watermark.h @@ -17,11 +17,12 @@ struct intel_atomic_state; struct intel_bw_state; struct intel_crtc; struct intel_crtc_state; +struct intel_display; struct intel_plane; struct skl_pipe_wm; struct skl_wm_level; -u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915); +u8 intel_enabled_dbuf_slices_mask(struct intel_display *display); void intel_sagv_pre_plane_update(struct intel_atomic_state *state); void intel_sagv_post_plane_update(struct intel_atomic_state *state); From patchwork Tue Nov 5 07:15:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13862578 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BB66D1CA3A for ; Tue, 5 Nov 2024 07:16:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BAED610E52B; Tue, 5 Nov 2024 07:16:26 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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([10.245.245.146]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 23:16:21 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, jani.nikula@intel.com, ville.syrjala@intel.com, jani.saarinen@intel.com Subject: [PATCH 2/8] drm/i9i5/display: use intel_display in intel_de_read calls of skl_watermark.c Date: Tue, 5 Nov 2024 09:15:54 +0200 Message-Id: <20241105071600.235338-3-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105071600.235338-1-vinod.govindapillai@intel.com> References: <20241105071600.235338-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Convert all intel_de_read() to use intel_display instead of struct drm_i915_private object. This is in preparation for the rest of the patches in this series where hw support for the minimum and interim ddb allocations for async flip is added. Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/skl_watermark.c | 48 +++++++++++--------- 1 file changed, 26 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index d9d7238f0fb4..2afc95e7533c 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -82,12 +82,14 @@ intel_has_sagv(struct drm_i915_private *i915) } static u32 -intel_sagv_block_time(struct drm_i915_private *i915) +intel_sagv_block_time(struct intel_display *display) { + struct drm_i915_private *i915 = to_i915(display->drm); + if (DISPLAY_VER(i915) >= 14) { u32 val; - val = intel_de_read(i915, MTL_LATENCY_SAGV); + val = intel_de_read(display, MTL_LATENCY_SAGV); return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val); } else if (DISPLAY_VER(i915) >= 12) { @@ -126,7 +128,7 @@ static void intel_sagv_init(struct drm_i915_private *i915) drm_WARN_ON(&i915->drm, i915->display.sagv.status == I915_SAGV_UNKNOWN); - i915->display.sagv.block_time_us = intel_sagv_block_time(i915); + i915->display.sagv.block_time_us = intel_sagv_block_time(&i915->display); drm_dbg_kms(&i915->drm, "SAGV supported: %s, original SAGV block time: %u us\n", str_yes_no(intel_has_sagv(i915)), i915->display.sagv.block_time_us); @@ -791,7 +793,7 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) } static void -skl_ddb_get_hw_plane_state(struct drm_i915_private *i915, +skl_ddb_get_hw_plane_state(struct intel_display *display, const enum pipe pipe, const enum plane_id plane_id, struct skl_ddb_entry *ddb, @@ -801,18 +803,18 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *i915, /* Cursor doesn't support NV12/planar, so no extra calculation needed */ if (plane_id == PLANE_CURSOR) { - val = intel_de_read(i915, CUR_BUF_CFG(pipe)); + val = intel_de_read(display, CUR_BUF_CFG(pipe)); skl_ddb_entry_init_from_hw(ddb, val); return; } - val = intel_de_read(i915, PLANE_BUF_CFG(pipe, plane_id)); + val = intel_de_read(display, PLANE_BUF_CFG(pipe, plane_id)); skl_ddb_entry_init_from_hw(ddb, val); - if (DISPLAY_VER(i915) >= 11) + if (DISPLAY_VER(display) >= 11) return; - val = intel_de_read(i915, PLANE_NV12_BUF_CFG(pipe, plane_id)); + val = intel_de_read(display, PLANE_NV12_BUF_CFG(pipe, plane_id)); skl_ddb_entry_init_from_hw(ddb_y, val); } @@ -832,7 +834,7 @@ static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, return; for_each_plane_id_on_crtc(crtc, plane_id) - skl_ddb_get_hw_plane_state(i915, pipe, + skl_ddb_get_hw_plane_state(&i915->display, pipe, plane_id, &ddb[plane_id], &ddb_y[plane_id]); @@ -2932,6 +2934,7 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, struct skl_pipe_wm *out) { struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = &i915->display; enum pipe pipe = crtc->pipe; enum plane_id plane_id; int level; @@ -2942,32 +2945,32 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, for (level = 0; level < i915->display.wm.num_levels; level++) { if (plane_id != PLANE_CURSOR) - val = intel_de_read(i915, PLANE_WM(pipe, plane_id, level)); + val = intel_de_read(display, PLANE_WM(pipe, plane_id, level)); else - val = intel_de_read(i915, CUR_WM(pipe, level)); + val = intel_de_read(display, CUR_WM(pipe, level)); skl_wm_level_from_reg_val(val, &wm->wm[level]); } if (plane_id != PLANE_CURSOR) - val = intel_de_read(i915, PLANE_WM_TRANS(pipe, plane_id)); + val = intel_de_read(display, PLANE_WM_TRANS(pipe, plane_id)); else - val = intel_de_read(i915, CUR_WM_TRANS(pipe)); + val = intel_de_read(display, CUR_WM_TRANS(pipe)); skl_wm_level_from_reg_val(val, &wm->trans_wm); if (HAS_HW_SAGV_WM(i915)) { if (plane_id != PLANE_CURSOR) - val = intel_de_read(i915, PLANE_WM_SAGV(pipe, plane_id)); + val = intel_de_read(display, PLANE_WM_SAGV(pipe, plane_id)); else - val = intel_de_read(i915, CUR_WM_SAGV(pipe)); + val = intel_de_read(display, CUR_WM_SAGV(pipe)); skl_wm_level_from_reg_val(val, &wm->sagv.wm0); if (plane_id != PLANE_CURSOR) - val = intel_de_read(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id)); + val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id)); else - val = intel_de_read(i915, CUR_WM_SAGV_TRANS(pipe)); + val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe)); skl_wm_level_from_reg_val(val, &wm->sagv.trans_wm); } else if (DISPLAY_VER(i915) >= 12) { @@ -2985,7 +2988,7 @@ static void skl_wm_get_hw_state(struct drm_i915_private *i915) struct intel_crtc *crtc; if (HAS_MBUS_JOINING(i915)) - dbuf_state->joined_mbus = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN; + dbuf_state->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw); @@ -3014,7 +3017,7 @@ static void skl_wm_get_hw_state(struct drm_i915_private *i915) if (!crtc_state->hw.active) continue; - skl_ddb_get_hw_plane_state(i915, crtc->pipe, + skl_ddb_get_hw_plane_state(display, crtc->pipe, plane_id, ddb, ddb_y); skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb); @@ -3330,18 +3333,19 @@ adjust_wm_latency(struct drm_i915_private *i915, static void mtl_read_wm_latency(struct drm_i915_private *i915, u16 wm[]) { + struct intel_display *display = &i915->display; int num_levels = i915->display.wm.num_levels; u32 val; - val = intel_de_read(i915, MTL_LATENCY_LP0_LP1); + val = intel_de_read(display, MTL_LATENCY_LP0_LP1); wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); - val = intel_de_read(i915, MTL_LATENCY_LP2_LP3); + val = intel_de_read(display, MTL_LATENCY_LP2_LP3); wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); - val = intel_de_read(i915, MTL_LATENCY_LP4_LP5); + val = intel_de_read(display, MTL_LATENCY_LP4_LP5); wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val); wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val); From patchwork Tue Nov 5 07:15:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13862579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 501CDD1CA3E for ; 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([10.245.245.146]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 23:16:25 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, jani.nikula@intel.com, ville.syrjala@intel.com, jani.saarinen@intel.com Subject: [PATCH 3/8] drm/i915/display: update use_minimal_wm0_only to use intel_display Date: Tue, 5 Nov 2024 09:15:55 +0200 Message-Id: <20241105071600.235338-4-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105071600.235338-1-vinod.govindapillai@intel.com> References: <20241105071600.235338-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid using struct drm_i915_private reference and use intel_display instead. This is in preparation for the rest of the patches in this series where hw support for the minimum and interim ddb allocations for async flip is added Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/skl_watermark.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 2afc95e7533c..2018abc35c8a 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -1372,9 +1372,9 @@ static bool use_minimal_wm0_only(const struct intel_crtc_state *crtc_state, struct intel_plane *plane) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); - return DISPLAY_VER(i915) >= 13 && + return DISPLAY_VER(display) >= 13 && crtc_state->uapi.async_flip && plane->async_flip; } From patchwork Tue Nov 5 07:15:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13862580 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33070D1CA3B for ; Tue, 5 Nov 2024 07:16:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CF14E10E530; Tue, 5 Nov 2024 07:16:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="e7UwLA04"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8FC2A10E530; Tue, 5 Nov 2024 07:16:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730790990; x=1762326990; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dfkoONrr2H9jCulSk4ZZ/Xme5pFeIDhodImx+XI1Iio=; b=e7UwLA04N3rlP+Sm8u+DlDpPwxGEd0nldMhAJgjCV/IhiiLxQ+a3aZfg pMvfewRU4KcVGNdOBKPRS9opmYCV4qW4sAHUXX00CWL/leQiwOJqorHYm xkiCGQ5BTnL8D7ECFMuFVYOKnKOrj/4ZK57x7hsu9n97bU0ydm1vqCAVZ vYkyfYwjnPALRKSnvHLL/Wrt8i6s6C4KLupyghpdx05OamnSXAs2Ztu70 iG45/vnqAWuieR3dtoq52L25wYFK7yRnfDUPWNJLBWd6A6jDpIhiecyZ2 aPLeMHCbgdLNig8wcdmn0gcG6p6fmsbhWMSZ4cdvHwlkwiqYAjL9TIOen g==; X-CSE-ConnectionGUID: v84KsADtQzCte27vX/FqEg== X-CSE-MsgGUID: l/EWhDe2TqW9d11RzFp2AQ== X-IronPort-AV: E=McAfee;i="6700,10204,11246"; a="34449548" X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="34449548" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 23:16:30 -0800 X-CSE-ConnectionGUID: D0F3fz6nR9GYd5NkEMiBIA== X-CSE-MsgGUID: mZsRQK4/ROyjwhSMotRnAw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="87835589" Received: from apaszkie-mobl2.apaszkie-mobl2 (HELO vgovind2-mobl3..) ([10.245.245.146]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 23:16:28 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, jani.nikula@intel.com, ville.syrjala@intel.com, jani.saarinen@intel.com Subject: [PATCH 4/8] drm/i915/display: update use_min_ddb to use intel_display Date: Tue, 5 Nov 2024 09:15:56 +0200 Message-Id: <20241105071600.235338-5-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105071600.235338-1-vinod.govindapillai@intel.com> References: <20241105071600.235338-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid using struct drm_i915_private reference and use intel_display instead. This is in preparation for the rest of the patches in this series where hw support for the minimum and interim ddb allocations for async flip is added Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index d89630b2d5c1..2c8fae8de4da 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -211,9 +211,9 @@ static bool use_min_ddb(const struct intel_crtc_state *crtc_state, struct intel_plane *plane) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); - return DISPLAY_VER(i915) >= 13 && + return DISPLAY_VER(display) >= 13 && crtc_state->uapi.async_flip && plane->async_flip; } From patchwork Tue Nov 5 07:15:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13862581 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E63ED1CA3D for ; Tue, 5 Nov 2024 07:16:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BA39410E529; Tue, 5 Nov 2024 07:16:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ZJGhqsYz"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8253410E532; Tue, 5 Nov 2024 07:16:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730790993; x=1762326993; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UqlibNz23g7BS4mu9C6rKdPAQYIVrOXLWkKxbOP7G/w=; b=ZJGhqsYzbwsKlYJE4xRuvtAF0r9VszZoTi02yRuQkH1apgl37lyGKTZi FAg7j5ORj8CAQaFRvFrYbv3hmnhOr/BDwfyV9DwhQcWItyE7oa8YDyJSs qhXsZwsVrdrKWYgYGJCPfGTfKQEg6GVROkiqlPEys0616GqTBlLg6fmtw hRMfXl9Rq3cF9lYP6kbpWAJo8iZyCgHYsEzZa9Z5b4b8TrHDlZ+Y5ykgC mTCgcv4VKF5J7bCpTJ4VXxTemtCihSep21dbKlEN/o+zO4UOZz/JyotMW Yi4+xv7chHBP5/Lo+g/ZmQdpC4wRRlZ2hXGFBZ0fxJNpd5sGIv1c93Y5K w==; X-CSE-ConnectionGUID: 9wYTRg5/RP+jOxL8rJhpFQ== X-CSE-MsgGUID: 3uVyC6iKRKSQi5dGnM6ZjQ== X-IronPort-AV: E=McAfee;i="6700,10204,11246"; a="34449549" X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="34449549" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 23:16:33 -0800 X-CSE-ConnectionGUID: A6HWCoOKQGmUZPqoDVhdxQ== X-CSE-MsgGUID: i89OSmTxQku8oNzztynQsQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="87835612" Received: from apaszkie-mobl2.apaszkie-mobl2 (HELO vgovind2-mobl3..) ([10.245.245.146]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 23:16:31 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, jani.nikula@intel.com, ville.syrjala@intel.com, jani.saarinen@intel.com Subject: [PATCH 5/8] drm/i915/display: update skl_plane_wm_equals to use intel_display Date: Tue, 5 Nov 2024 09:15:57 +0200 Message-Id: <20241105071600.235338-6-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105071600.235338-1-vinod.govindapillai@intel.com> References: <20241105071600.235338-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Use intel_display object instead of struct drm_i915_private in skl_plane_wm_equals(). This is in preparation for the rest of the patches in this series where hw support for the minimum and interim ddb allocations for async flip is added Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/skl_watermark.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 2018abc35c8a..a01b1dc01348 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2384,13 +2384,13 @@ static bool skl_wm_level_equals(const struct skl_wm_level *l1, l1->blocks == l2->blocks; } -static bool skl_plane_wm_equals(struct drm_i915_private *i915, +static bool skl_plane_wm_equals(struct intel_display *display, const struct skl_plane_wm *wm1, const struct skl_plane_wm *wm2) { int level; - for (level = 0; level < i915->display.wm.num_levels; level++) { + for (level = 0; level < display->wm.num_levels; level++) { /* * We don't check uv_wm as the hardware doesn't actually * use it. It only gets used for calculating the required @@ -2650,7 +2650,7 @@ skl_print_wm_changes(struct intel_atomic_state *state) old_wm = &old_pipe_wm->planes[plane_id]; new_wm = &new_pipe_wm->planes[plane_id]; - if (skl_plane_wm_equals(i915, old_wm, new_wm)) + if (skl_plane_wm_equals(&i915->display, old_wm, new_wm)) continue; drm_dbg_kms(&i915->drm, From patchwork Tue Nov 5 07:15:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13862582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DA59D1CA3D for ; Tue, 5 Nov 2024 07:16:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D910E10E52A; Tue, 5 Nov 2024 07:16:37 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Gpkb6Igv"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id CBD9B10E534; Tue, 5 Nov 2024 07:16:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730790996; x=1762326996; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zVFLpyChl9zzEpMr2wcRGvX7C1usw2di5CzjwFJ4AHY=; b=Gpkb6IgveCC7KmFV1B3CMREw49L606pJSrfy+1fcRBK1zsvyMknajVlu 6d5Vy/P4fahTnETnSNvKKgUtjendJ4N9IRGccJuwCOrzQWiv/SnQtJ2zI JyYw1Vkeq7oHX/vKnWPS49kU2XueZigdnFKtlamHIUglYko7dQho50aou j14heJJqwiwMDssZ9tDwIU6HTuYI7tQQ+ZyWkXtsOQsOzY7qLcy8uIYxD qud+ahEukp62QN6/Ic7JgVYPD91k/gT0FYJvn0gxp+EhBa9fJZVxbf7Kf Vts9yIauzoRZ942OSqIvdK+fkRnbbZOAUix4Y+vJ8S94rxZgL3OHTWfB+ g==; X-CSE-ConnectionGUID: YhMS6BQ2Tn+nsa5cj6QR9w== X-CSE-MsgGUID: sBtNiCQqTjq6XFUmwNktuw== X-IronPort-AV: E=McAfee;i="6700,10204,11246"; a="34449550" X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="34449550" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 23:16:36 -0800 X-CSE-ConnectionGUID: fMcq9GI0Tj2h/g/spKyhvg== X-CSE-MsgGUID: p5ziocTHSYG/FA9tcmpfyQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="87835625" Received: from apaszkie-mobl2.apaszkie-mobl2 (HELO vgovind2-mobl3..) ([10.245.245.146]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 23:16:34 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, jani.nikula@intel.com, ville.syrjala@intel.com, jani.saarinen@intel.com Subject: [PATCH 6/8] drm/i915/display: update to plane_wm register access function Date: Tue, 5 Nov 2024 09:15:58 +0200 Message-Id: <20241105071600.235338-7-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105071600.235338-1-vinod.govindapillai@intel.com> References: <20241105071600.235338-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Future platforms can have new additions in the plane_wm registers. So update skl_wm_level_from_reg_val() to have possiblity for such platform differentiations. This is in preparation for the rest of the patches in this series where hw support for the minimum and interim ddb allocations for async flip is added Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/skl_watermark.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index a01b1dc01348..d961d01343b3 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2922,7 +2922,8 @@ skl_compute_wm(struct intel_atomic_state *state) return 0; } -static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level) +static void skl_wm_level_from_reg_val(struct intel_display *display, + u32 val, struct skl_wm_level *level) { level->enable = val & PLANE_WM_EN; level->ignore_lines = val & PLANE_WM_IGNORE_LINES; @@ -2949,7 +2950,7 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, else val = intel_de_read(display, CUR_WM(pipe, level)); - skl_wm_level_from_reg_val(val, &wm->wm[level]); + skl_wm_level_from_reg_val(display, val, &wm->wm[level]); } if (plane_id != PLANE_CURSOR) @@ -2957,7 +2958,7 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, else val = intel_de_read(display, CUR_WM_TRANS(pipe)); - skl_wm_level_from_reg_val(val, &wm->trans_wm); + skl_wm_level_from_reg_val(display, val, &wm->trans_wm); if (HAS_HW_SAGV_WM(i915)) { if (plane_id != PLANE_CURSOR) @@ -2965,14 +2966,14 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, else val = intel_de_read(display, CUR_WM_SAGV(pipe)); - skl_wm_level_from_reg_val(val, &wm->sagv.wm0); + skl_wm_level_from_reg_val(display, val, &wm->sagv.wm0); if (plane_id != PLANE_CURSOR) val = intel_de_read(display, PLANE_WM_SAGV_TRANS(pipe, plane_id)); else val = intel_de_read(display, CUR_WM_SAGV_TRANS(pipe)); - skl_wm_level_from_reg_val(val, &wm->sagv.trans_wm); + skl_wm_level_from_reg_val(display, val, &wm->sagv.trans_wm); } else if (DISPLAY_VER(i915) >= 12) { wm->sagv.wm0 = wm->wm[0]; wm->sagv.trans_wm = wm->trans_wm; From patchwork Tue Nov 5 07:15:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13862583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86F5DD1CA3A for ; Tue, 5 Nov 2024 07:16:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 26E0910E537; Tue, 5 Nov 2024 07:16:44 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OG16+G+C"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8BCB710E536; Tue, 5 Nov 2024 07:16:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730791002; x=1762327002; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E4Il8PauRGpJIoCoz6LCKq6Aq4nHCinOkeXdHKLZtWA=; b=OG16+G+C2W14pM26oRl2N8CiWXcS7LoHokKwOmVcQDQcCIotENnsz+dA 6XLQswI0nJEMQjEW8x95Jq5pRYA6PNFIMAx4bGeqb1iGOjMl6QOsOdjo6 +xbV8U0bCNGq2i+Ip9fC+yUnsWhv1Hh1sujmd6ApGZDBpl8QwXZlXzuzU 5TVSElxPUp2/F0gNj/Ch8PQRF++Nl8NlrQapPPrqZ9lZ0qUJgH/B1qK2v elvPGP1Y5rLWdKigUjLwCeVLWSoQE03b2ypu5R6DX0koNByi7o/jN1+x8 EQRfkrQnJybxt/01eP1NRzhyl31a3oAs9Pq16d418L+/a0FCPyBNaA0RD w==; X-CSE-ConnectionGUID: RHg1JPAfQv+7lGk2qm5VWw== X-CSE-MsgGUID: HYEfaEF6RRibEbbP3remQw== X-IronPort-AV: E=McAfee;i="6700,10204,11246"; a="34449553" X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="34449553" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 23:16:42 -0800 X-CSE-ConnectionGUID: vT9MoLc/T6C/yjkPeZQ1gQ== X-CSE-MsgGUID: xLh5fJrLRxG89MabvANfHw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="87835648" Received: from apaszkie-mobl2.apaszkie-mobl2 (HELO vgovind2-mobl3..) ([10.245.245.146]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 23:16:38 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, jani.nikula@intel.com, ville.syrjala@intel.com, jani.saarinen@intel.com Subject: [PATCH 7/8] drm/i915/xe3: Use hw support for min/interim ddb allocations for async flip Date: Tue, 5 Nov 2024 09:15:59 +0200 Message-Id: <20241105071600.235338-8-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105071600.235338-1-vinod.govindapillai@intel.com> References: <20241105071600.235338-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Stanislav Lisovskiy Starting from xe3, hw now is capable of switching automatically to min ddb allocation(not using any extra blocks) or interim SAGV-adjusted allocation in case if async flip is used. For that purpose there is now additional register, where correspodent values have to be programmed. Bspec: 69880, 72053 Signed-off-by: Stanislav Lisovskiy Signed-off-by: Vinod Govindapillai --- .../gpu/drm/i915/display/intel_atomic_plane.c | 9 ++ .../drm/i915/display/intel_display_types.h | 8 ++ .../drm/i915/display/skl_universal_plane.c | 31 +++++++ .../i915/display/skl_universal_plane_regs.h | 13 +++ drivers/gpu/drm/i915/display/skl_watermark.c | 85 +++++++++++++++++-- 5 files changed, 140 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 2c8fae8de4da..7940cb911889 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -213,6 +213,15 @@ use_min_ddb(const struct intel_crtc_state *crtc_state, { struct intel_display *display = to_intel_display(plane); + /* + * For xe3 onwards this feature is implemented in + * hardware, so no need to force relative data rate to 0, + * we will update a specific register with min_ddb without + * extra blocks. + */ + if (DISPLAY_VER(display) >= 30) + return false; + return DISPLAY_VER(display) >= 13 && crtc_state->uapi.async_flip && plane->async_flip; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index d2b68505f088..c0548db0061c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -770,6 +770,7 @@ struct skl_wm_level { bool enable; bool ignore_lines; bool can_sagv; + bool auto_min_ddb_allowed; }; struct skl_plane_wm { @@ -863,6 +864,13 @@ struct intel_crtc_wm_state { struct skl_ddb_entry plane_ddb[I915_MAX_PLANES]; /* pre-icl: for planar Y */ struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES]; + + /* + * xe3: Minimum amount of display blocks and minimum + * sagv allocation required for async flip + */ + struct skl_ddb_entry plane_min_ddb[I915_MAX_PLANES]; + struct skl_ddb_entry plane_interim_ddb[I915_MAX_PLANES]; } skl; struct { diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 038ca2ec5d7a..69d5ca74c594 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -715,6 +715,26 @@ static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry) PLANE_BUF_START(entry->start); } +static u32 ptl_plane_min_ddb_reg_val(const struct skl_ddb_entry *min_ddb_entry, + const struct skl_ddb_entry *interim_ddb_entry) +{ + u32 val = 0; + + if (min_ddb_entry->end) { + val |= PLANE_AUTO_MIN_DBUF_EN; + val |= REG_FIELD_PREP(PLANE_MIN_DDB_BLOCKS_MASK, + min_ddb_entry->end - min_ddb_entry->start); + } + + if (interim_ddb_entry->end) { + val |= PLANE_AUTO_MIN_DBUF_EN; + val |= REG_FIELD_PREP(PLANE_INTERIM_DDB_BLOCKS_MASK, + interim_ddb_entry->end - interim_ddb_entry->start); + } + + return val; +} + static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level) { u32 val = 0; @@ -723,6 +743,9 @@ static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level) val |= PLANE_WM_EN; if (level->ignore_lines) val |= PLANE_WM_IGNORE_LINES; + if (level->auto_min_ddb_allowed) + val |= PLANE_WM_AUTO_MIN_ALLOC_EN; + val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks); val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines); @@ -742,6 +765,10 @@ static void skl_write_plane_wm(struct intel_dsb *dsb, &crtc_state->wm.skl.plane_ddb[plane_id]; const struct skl_ddb_entry *ddb_y = &crtc_state->wm.skl.plane_ddb_y[plane_id]; + const struct skl_ddb_entry *min_ddb = + &crtc_state->wm.skl.plane_min_ddb[plane_id]; + const struct skl_ddb_entry *interim_ddb = + &crtc_state->wm.skl.plane_interim_ddb[plane_id]; int level; for (level = 0; level < i915->display.wm.num_levels; level++) @@ -766,6 +793,10 @@ static void skl_write_plane_wm(struct intel_dsb *dsb, if (DISPLAY_VER(i915) < 11) intel_de_write_dsb(display, dsb, PLANE_NV12_BUF_CFG(pipe, plane_id), skl_plane_ddb_reg_val(ddb_y)); + + if (DISPLAY_VER(display) >= 30) + intel_de_write_dsb(display, dsb, PLANE_MIN_BUF_CFG(pipe, plane_id), + ptl_plane_min_ddb_reg_val(min_ddb, interim_ddb)); } static void diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index ff31a00d511e..65a5482fae60 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -322,6 +322,7 @@ _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) #define PLANE_WM_EN REG_BIT(31) #define PLANE_WM_IGNORE_LINES REG_BIT(30) +#define PLANE_WM_AUTO_MIN_ALLOC_EN REG_BIT(29) #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) @@ -373,12 +374,24 @@ #define PLANE_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B, \ _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) +#define _PLANE_MIN_BUF_CFG_1_A 0x70274 +#define _PLANE_MIN_BUF_CFG_2_A 0x70374 +#define _PLANE_MIN_BUF_CFG_1_B 0x71274 +#define _PLANE_MIN_BUF_CFG_2_B 0x71374 +#define PLANE_MIN_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_MIN_BUF_CFG_1_A, _PLANE_MIN_BUF_CFG_1_B, \ + _PLANE_MIN_BUF_CFG_2_A, _PLANE_MIN_BUF_CFG_2_B) + /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ #define PLANE_BUF_END_MASK REG_GENMASK(27, 16) #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) #define PLANE_BUF_START_MASK REG_GENMASK(11, 0) #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) +#define PLANE_AUTO_MIN_DBUF_EN REG_BIT(31) +#define PLANE_MIN_DDB_BLOCKS_MASK REG_GENMASK(27, 16) +#define PLANE_INTERIM_DDB_BLOCKS_MASK REG_GENMASK(11, 0) + /* tgl+ */ #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 #define _SEL_FETCH_PLANE_CTL_2_A 0x708b0 diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index d961d01343b3..4e6433374e0d 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -797,7 +797,9 @@ skl_ddb_get_hw_plane_state(struct intel_display *display, const enum pipe pipe, const enum plane_id plane_id, struct skl_ddb_entry *ddb, - struct skl_ddb_entry *ddb_y) + struct skl_ddb_entry *ddb_y, + struct skl_ddb_entry *min_ddb, + struct skl_ddb_entry *interim_ddb) { u32 val; @@ -811,6 +813,17 @@ skl_ddb_get_hw_plane_state(struct intel_display *display, val = intel_de_read(display, PLANE_BUF_CFG(pipe, plane_id)); skl_ddb_entry_init_from_hw(ddb, val); + if (DISPLAY_VER(display) >= 30) { + val = intel_de_read(display, PLANE_MIN_BUF_CFG(pipe, plane_id)); + + skl_ddb_entry_init(min_ddb, 0, + REG_FIELD_GET(PLANE_MIN_DDB_BLOCKS_MASK, + val)); + skl_ddb_entry_init(interim_ddb, 0, + REG_FIELD_GET(PLANE_INTERIM_DDB_BLOCKS_MASK, + val)); + } + if (DISPLAY_VER(display) >= 11) return; @@ -820,7 +833,9 @@ skl_ddb_get_hw_plane_state(struct intel_display *display, static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, struct skl_ddb_entry *ddb, - struct skl_ddb_entry *ddb_y) + struct skl_ddb_entry *ddb_y, + struct skl_ddb_entry *min_ddb, + struct skl_ddb_entry *interim_ddb) { struct drm_i915_private *i915 = to_i915(crtc->base.dev); enum intel_display_power_domain power_domain; @@ -837,7 +852,9 @@ static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, skl_ddb_get_hw_plane_state(&i915->display, pipe, plane_id, &ddb[plane_id], - &ddb_y[plane_id]); + &ddb_y[plane_id], + &min_ddb[plane_id], + &interim_ddb[plane_id]); intel_display_power_put(i915, power_domain, wakeref); } @@ -1374,7 +1391,9 @@ use_minimal_wm0_only(const struct intel_crtc_state *crtc_state, { struct intel_display *display = to_intel_display(plane); + /* Xe3 (ver >= 30) has auto minimum DDB enabled */ return DISPLAY_VER(display) >= 13 && + DISPLAY_VER(display) < 30 && crtc_state->uapi.async_flip && plane->async_flip; } @@ -1515,6 +1534,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state, const struct intel_dbuf_state *dbuf_state = intel_atomic_get_new_dbuf_state(state); const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe]; + struct intel_display *display = to_intel_display(state); int num_active = hweight8(dbuf_state->active_pipes); struct skl_plane_ddb_iter iter; enum plane_id plane_id; @@ -1525,6 +1545,8 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state, /* Clear the partitioning for disabled planes. */ memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb)); memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); + memset(crtc_state->wm.skl.plane_min_ddb, 0, sizeof(crtc_state->wm.skl.plane_min_ddb)); + memset(crtc_state->wm.skl.plane_interim_ddb, 0, sizeof(crtc_state->wm.skl.plane_interim_ddb)); if (!crtc_state->hw.active) return 0; @@ -1597,6 +1619,10 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state, &crtc_state->wm.skl.plane_ddb[plane_id]; struct skl_ddb_entry *ddb_y = &crtc_state->wm.skl.plane_ddb_y[plane_id]; + struct skl_ddb_entry *min_ddb = + &crtc_state->wm.skl.plane_min_ddb[plane_id]; + struct skl_ddb_entry *interim_ddb = + &crtc_state->wm.skl.plane_interim_ddb[plane_id]; const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; @@ -1612,6 +1638,20 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state, } else { skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level], crtc_state->rel_data_rate[plane_id]); + + /* + * xe3: Handle min_ddb and interim_ddb. Unlike the + * normal ddb allocation, min_ddb and interim_ddb config + * expects only the number of blocks from 0. The buffer + * start is found in PLANE_BUF_CFG + * Bspec: 72053 + */ + if (DISPLAY_VER(display) >= 30) { + skl_ddb_entry_init(min_ddb, 0, + wm->wm[0].min_ddb_alloc); + skl_ddb_entry_init(interim_ddb, 0, + wm->sagv.wm0.min_ddb_alloc); + } } } drm_WARN_ON(&i915->drm, iter.size != 0 || iter.data_rate != 0); @@ -1656,6 +1696,8 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state, &crtc_state->wm.skl.plane_ddb[plane_id]; const struct skl_ddb_entry *ddb_y = &crtc_state->wm.skl.plane_ddb_y[plane_id]; + struct skl_ddb_entry *interim_ddb = + &crtc_state->wm.skl.plane_interim_ddb[plane_id]; struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; @@ -1669,6 +1711,11 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state, } skl_check_wm_level(&wm->sagv.wm0, ddb); + /* update the interim ddb, in case if it is changed */ + if (DISPLAY_VER(display) >= 30) + skl_ddb_entry_init(interim_ddb, 0, + wm->sagv.wm0.min_ddb_alloc); + skl_check_wm_level(&wm->sagv.trans_wm, ddb); } @@ -1747,6 +1794,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state, int color_plane, unsigned int pan_x) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_display *display = to_intel_display(crtc_state); struct drm_i915_private *i915 = to_i915(crtc->base.dev); u32 interm_pbpl; @@ -1805,7 +1853,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state, wp->y_min_scanlines, wp->dbuf_block_size); - if (DISPLAY_VER(i915) >= 30) + if (DISPLAY_VER(display) >= 30) interm_pbpl += (pan_x != 0); else if (DISPLAY_VER(i915) >= 10) interm_pbpl++; @@ -1870,6 +1918,11 @@ static int skl_wm_max_lines(struct drm_i915_private *i915) return 31; } +static bool can_use_min_ddb(struct intel_display *display, int level) +{ + return DISPLAY_VER(display) >= 30 && level == 0; +} + static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, struct intel_plane *plane, int level, @@ -1879,6 +1932,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, struct skl_wm_level *result /* out */) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); uint_fixed_16_16_t method1, method2; uint_fixed_16_16_t selected_result; u32 blocks, lines, min_ddb_alloc = 0; @@ -2002,6 +2056,11 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */ result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1; result->enable = true; + /* + * For Xe3, when auto min DDB is enabled, it automatically switches to + * the wm level where this auto min ddb is enabled + */ + result->auto_min_ddb_allowed = can_use_min_ddb(display, level); if (DISPLAY_VER(i915) < 12 && i915->display.sagv.block_time_us) result->can_sagv = latency >= i915->display.sagv.block_time_us; @@ -2398,6 +2457,10 @@ static bool skl_plane_wm_equals(struct intel_display *display, */ if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level])) return false; + + if (DISPLAY_VER(display) >= 30 && + wm1->wm[level].auto_min_ddb_allowed != wm2->wm[level].auto_min_ddb_allowed) + return false; } return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm) && @@ -2929,6 +2992,8 @@ static void skl_wm_level_from_reg_val(struct intel_display *display, level->ignore_lines = val & PLANE_WM_IGNORE_LINES; level->blocks = REG_FIELD_GET(PLANE_WM_BLOCKS_MASK, val); level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val); + level->auto_min_ddb_allowed = DISPLAY_VER(display) >= 30 && + val & PLANE_WM_AUTO_MIN_ALLOC_EN; } static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, @@ -3014,12 +3079,17 @@ static void skl_wm_get_hw_state(struct drm_i915_private *i915) &crtc_state->wm.skl.plane_ddb[plane_id]; struct skl_ddb_entry *ddb_y = &crtc_state->wm.skl.plane_ddb_y[plane_id]; + struct skl_ddb_entry *min_ddb = + &crtc_state->wm.skl.plane_min_ddb[plane_id]; + struct skl_ddb_entry *interim_ddb = + &crtc_state->wm.skl.plane_interim_ddb[plane_id]; if (!crtc_state->hw.active) continue; skl_ddb_get_hw_plane_state(display, crtc->pipe, - plane_id, ddb, ddb_y); + plane_id, ddb, ddb_y, + min_ddb, interim_ddb); skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb); skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y); @@ -3136,6 +3206,8 @@ void intel_wm_state_verify(struct intel_atomic_state *state, struct skl_hw_state { struct skl_ddb_entry ddb[I915_MAX_PLANES]; struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; + struct skl_ddb_entry min_ddb[I915_MAX_PLANES]; + struct skl_ddb_entry interim_ddb[I915_MAX_PLANES]; struct skl_pipe_wm wm; } *hw; const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; @@ -3152,7 +3224,8 @@ void intel_wm_state_verify(struct intel_atomic_state *state, skl_pipe_wm_get_hw_state(crtc, &hw->wm); - skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y); + skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y, hw->min_ddb, + hw->interim_ddb); hw_enabled_slices = intel_enabled_dbuf_slices_mask(display); From patchwork Tue Nov 5 07:16:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Govindapillai X-Patchwork-Id: 13862584 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 909FCD1CA3E for ; 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([10.245.245.146]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 23:16:42 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: vinod.govindapillai@intel.com, jani.nikula@intel.com, ville.syrjala@intel.com, jani.saarinen@intel.com Subject: [PATCH 8/8] drm/i915/debugfs: add dbuf alloc status as part of i915_ddb_info Date: Tue, 5 Nov 2024 09:16:00 +0200 Message-Id: <20241105071600.235338-9-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105071600.235338-1-vinod.govindapillai@intel.com> References: <20241105071600.235338-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From xe3 onwards, there is a provision to define and use min ddb and interim ddb allocations for async flip use case. Add the dbuf allocation status as part of i915_ddb_info as well to show if min or interim ddb is being used. Bspec: 72053 Signed-off-by: Vinod Govindapillai --- .../drm/i915/display/intel_display_debugfs.c | 23 ++++++++++++++++--- .../i915/display/skl_universal_plane_regs.h | 1 + 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 11aff485d8fa..bce4a1ab05c0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -39,6 +39,7 @@ #include "intel_pps.h" #include "intel_psr.h" #include "intel_psr_regs.h" +#include "skl_universal_plane_regs.h" #include "intel_vdsc.h" #include "intel_wm.h" @@ -688,9 +689,24 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) return 0; } +static u32 dbuf_alloc_status(struct intel_display *display, + enum pipe pipe, enum plane_id plane_id) +{ + u32 val = 0; + + if (DISPLAY_VER(display) >= 30) { + u32 reg = intel_de_read(display, + PLANE_MIN_BUF_CFG(pipe, plane_id)); + val = REG_FIELD_GET(PLANE_DBUF_ALLOC_STATUS_MASK, reg); + } + + return val; +} + static int i915_ddb_info(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_display *display = &dev_priv->display; struct skl_ddb_entry *entry; struct intel_crtc *crtc; @@ -699,7 +715,7 @@ static int i915_ddb_info(struct seq_file *m, void *unused) drm_modeset_lock_all(&dev_priv->drm); - seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); + seq_printf(m, "%-15s%8s%8s%8s%16s\n", "", "Start", "End", "Size", "Alloc Status"); for_each_intel_crtc(&dev_priv->drm, crtc) { struct intel_crtc_state *crtc_state = @@ -711,9 +727,10 @@ static int i915_ddb_info(struct seq_file *m, void *unused) for_each_plane_id_on_crtc(crtc, plane_id) { entry = &crtc_state->wm.skl.plane_ddb[plane_id]; - seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1, + seq_printf(m, " Plane%-8d%8u%8u%8u%8u\n", plane_id + 1, entry->start, entry->end, - skl_ddb_entry_size(entry)); + skl_ddb_entry_size(entry), + dbuf_alloc_status(display, pipe, plane_id)); } entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 65a5482fae60..53550356430d 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -390,6 +390,7 @@ #define PLANE_AUTO_MIN_DBUF_EN REG_BIT(31) #define PLANE_MIN_DDB_BLOCKS_MASK REG_GENMASK(27, 16) +#define PLANE_DBUF_ALLOC_STATUS_MASK REG_GENMASK(15, 14) #define PLANE_INTERIM_DDB_BLOCKS_MASK REG_GENMASK(11, 0) /* tgl+ */