From patchwork Tue Nov 5 10:26:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13862778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8DC2D12678 for ; Tue, 5 Nov 2024 10:35:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1566A10E560; Tue, 5 Nov 2024 10:35:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="KfGs9dFh"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 62A0910E557; Tue, 5 Nov 2024 10:35:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730802951; x=1762338951; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pyOQ/mxEZT4HahP/Y4QV6pHhaaMe/ceMczmkNYYTyL0=; b=KfGs9dFhakAHQ+hAkIQgrlEkEcYaa+74UvySjj0rKjXLYruG6iY8+t4W 1yMNj1ztUKqA7wPZNHcPHvhkP1OkTH24bdPertUSQZF4Qtz9AKYrSbiIe ZXtw8bO0wzIZqQohX9sJWuMiW29zJ3mSFB1/fuLVj9g3fR8qVuBwjceR4 tVcZb6OtZ6LzZ0e/0LnEd0rs6LrDFqR2MY7MxbFioeqOLZWnpVcuE9Foc K8gNmmr3imTo5A8k8v5gl8gOKQt8++/6yaxeW7lHk35qa6AQO2cBQ2stN hdhmCPvpU0T/Fhs1g2iteP6NmVF8LPVXnGUpqpVWB+oe+pLeE/CTooodd w==; X-CSE-ConnectionGUID: u/lB8vphRkKZUNrD2YUQfg== X-CSE-MsgGUID: lkM7z/v6SMq7wnqcNrYaIg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="34230832" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="34230832" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Nov 2024 02:35:50 -0800 X-CSE-ConnectionGUID: uIYCvY1oQ9+qi5Ys6raJhQ== X-CSE-MsgGUID: kfFqa+3qSu+zms62KKdYbQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="83485545" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa006.fm.intel.com with ESMTP; 05 Nov 2024 02:35:49 -0800 From: Arun R Murthy To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Arun R Murthy Subject: [PATCH 1/4] drm/plane: Add new plane property IN_FORMATS_ASYNC Date: Tue, 5 Nov 2024 15:56:05 +0530 Message-Id: <20241105102608.3912133-2-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241105102608.3912133-1-arun.r.murthy@intel.com> References: <20241105102608.3912133-1-arun.r.murthy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" There exists a property IN_FORMATS which exposes the plane supported modifiers/formats to the user. In some platforms when asynchronous flips are used all of modifiers/formats mentioned in IN_FORMATS are not supported. This patch adds a new plane property IN_FORMATS_ASYNC to expose the async flips supported modifiers/formats so that user can use this information ahead and done flips with unsupported formats/modifiers. This will save flips failures. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/drm_mode_config.c | 7 +++ drivers/gpu/drm/drm_plane.c | 73 +++++++++++++++++++++++++++++++ include/drm/drm_mode_config.h | 6 +++ include/drm/drm_plane.h | 10 +++++ 4 files changed, 96 insertions(+) diff --git a/drivers/gpu/drm/drm_mode_config.c b/drivers/gpu/drm/drm_mode_config.c index 37d2e0a4ef4b..cff189a2e751 100644 --- a/drivers/gpu/drm/drm_mode_config.c +++ b/drivers/gpu/drm/drm_mode_config.c @@ -379,6 +379,13 @@ static int drm_mode_create_standard_properties(struct drm_device *dev) return -ENOMEM; dev->mode_config.size_hints_property = prop; + prop = drm_property_create(dev, + DRM_MODE_PROP_IMMUTABLE | DRM_MODE_PROP_BLOB, + "IN_FORMATS_ASYNC", 0); + if (!prop) + return -ENOMEM; + dev->mode_config.async_modifiers_property = prop; + return 0; } diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index a28b22fdd7a4..01b8e6932fda 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -141,6 +141,12 @@ * various bugs in this area with inconsistencies between the capability * flag and per-plane properties. * + * IN_FORMATS_ASYNC: + * Blob property which contains the set of buffer format and modifier + * pairs supported by this plane for asynchronous flips. The blob is a struct + * drm_format_modifier_blob. Without this property the plane doesn't + * support buffers with modifiers. Userspace cannot change this property. + * * SIZE_HINTS: * Blob property which contains the set of recommended plane size * which can used for simple "cursor like" use cases (eg. no scaling). @@ -249,6 +255,70 @@ static int create_in_format_blob(struct drm_device *dev, struct drm_plane *plane return 0; } +static int create_in_format_async_blob(struct drm_device *dev, struct drm_plane *plane) +{ + const struct drm_mode_config *config = &dev->mode_config; + struct drm_property_blob *blob; + struct drm_format_modifier *async_mod; + size_t blob_size, async_formats_size, async_modifiers_size; + struct drm_format_modifier_blob *blob_data; + unsigned int i, j; + + async_formats_size = sizeof(__u32) * plane->async_format_count; + if (WARN_ON(!async_formats_size)) { + /* 0 formats are never expected */ + return 0; + } + + async_modifiers_size = + sizeof(struct drm_format_modifier) * plane->async_modifier_count; + + blob_size = sizeof(struct drm_format_modifier_blob); + /* Modifiers offset is a pointer to a struct with a 64 bit field so it + * should be naturally aligned to 8B. + */ + BUILD_BUG_ON(sizeof(struct drm_format_modifier_blob) % 8); + blob_size += ALIGN(async_formats_size, 8); + blob_size += async_modifiers_size; + + blob = drm_property_create_blob(dev, blob_size, NULL); + if (IS_ERR(blob)) + return -1; + + blob_data = blob->data; + blob_data->version = FORMAT_BLOB_CURRENT; + blob_data->count_formats = plane->async_format_count; + blob_data->formats_offset = sizeof(struct drm_format_modifier_blob); + blob_data->count_modifiers = plane->async_modifier_count; + + blob_data->modifiers_offset = + ALIGN(blob_data->formats_offset + async_formats_size, 8); + + memcpy(formats_ptr(blob_data), plane->async_format_types, async_formats_size); + + async_mod = modifiers_ptr(blob_data); + for (i = 0; i < plane->async_modifier_count; i++) { + for (j = 0; j < plane->async_format_count; j++) { + if (!plane->funcs->format_mod_supported || + plane->funcs->format_mod_supported(plane, + plane->async_format_types[j], + plane->async_modifiers[i])) { + async_mod->formats |= 1ULL << j; + } + } + + async_mod->modifier = plane->async_modifiers[i]; + async_mod->offset = 0; + async_mod->pad = 0; + async_mod++; + } + + drm_object_attach_property(&plane->base, config->async_modifiers_property, + blob->base.id); + + return 0; +} + /** * DOC: hotspot properties * @@ -472,6 +542,9 @@ static int __drm_universal_plane_init(struct drm_device *dev, if (format_modifier_count) create_in_format_blob(dev, plane); + if (plane->async_modifier_count) + create_in_format_async_blob(dev, plane); + return 0; } diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index 271765e2e9f2..0c116d6dfd27 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -936,6 +936,12 @@ struct drm_mode_config { */ struct drm_property *modifiers_property; + /** + * @async_modifiers_property: Plane property to list support modifier/format + * combination for asynchronous flips. + */ + struct drm_property *async_modifiers_property; + /** * @size_hints_property: Plane SIZE_HINTS property. */ diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index dd718c62ac31..d9571265251a 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -658,11 +658,21 @@ struct drm_plane { */ bool format_default; + /** @format_types: array of formats supported by this plane */ + uint32_t *async_format_types; + /** @format_count: Size of the array pointed at by @format_types. */ + unsigned int async_format_count; + /** @modifiers: array of modifiers supported by this plane */ uint64_t *modifiers; /** @modifier_count: Size of the array pointed at by @modifier_count. */ unsigned int modifier_count; + /** @modifiers: array of modifiers supported by this plane */ + uint64_t *async_modifiers; + /** @modifier_count: Size of the array pointed at by @modifier_count. */ + unsigned int async_modifier_count; + /** * @crtc: * From patchwork Tue Nov 5 10:26:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13862777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ABEF7D1267D for ; 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X-CSE-ConnectionGUID: 0/lwCgfKRDSdQntskhI7cg== X-CSE-MsgGUID: vYACH5N0RyOC5LSQ6c+rBA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="34230843" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="34230843" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Nov 2024 02:35:52 -0800 X-CSE-ConnectionGUID: jwK4J2SNReqs1bukIZN8BA== X-CSE-MsgGUID: n/g9Km0CTUq8ixVAaNdvuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="83485556" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa006.fm.intel.com with ESMTP; 05 Nov 2024 02:35:50 -0800 From: Arun R Murthy To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Arun R Murthy Subject: [PATCH 2/4] drm/i915/fb: Add async field to the modifiers description Date: Tue, 5 Nov 2024 15:56:06 +0530 Message-Id: <20241105102608.3912133-3-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241105102608.3912133-1-arun.r.murthy@intel.com> References: <20241105102608.3912133-1-arun.r.murthy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Few of the modifiers are not supported with async flip. Add an element async_flip to say if the modifier supports asynchronous flips. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_fb.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 6a7060889f40..f05e0c444618 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -231,6 +231,7 @@ struct intel_modifier_desc { u8 packed_aux_planes:4; u8 planar_aux_planes:4; } ccs; + bool async_flip; }; #define INTEL_PLANE_CAP_CCS_MASK (INTEL_PLANE_CAP_CCS_RC | \ @@ -247,10 +248,12 @@ static const struct intel_modifier_desc intel_modifiers[] = { .modifier = I915_FORMAT_MOD_4_TILED_LNL_CCS, .display_ver = { 20, -1 }, .plane_caps = INTEL_PLANE_CAP_TILING_4, + .async_flip = true, }, { .modifier = I915_FORMAT_MOD_4_TILED_BMG_CCS, .display_ver = { 14, -1 }, .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_NEED64K_PHYS, + .async_flip = true, }, { .modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS, .display_ver = { 14, 14 }, @@ -268,6 +271,7 @@ static const struct intel_modifier_desc intel_modifiers[] = { .ccs.packed_aux_planes = BIT(1), FORMAT_OVERRIDE(gen12_ccs_formats), + .async_flip = true, }, { .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC, .display_ver = { 14, 14 }, @@ -293,10 +297,12 @@ static const struct intel_modifier_desc intel_modifiers[] = { .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS, .display_ver = { 13, 13 }, .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC, + .async_flip = true, }, { .modifier = I915_FORMAT_MOD_4_TILED, .display_ver = { 13, -1 }, .plane_caps = INTEL_PLANE_CAP_TILING_4, + .async_flip = true, }, { .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, .display_ver = { 12, 13 }, @@ -314,6 +320,7 @@ static const struct intel_modifier_desc intel_modifiers[] = { .ccs.packed_aux_planes = BIT(1), FORMAT_OVERRIDE(gen12_ccs_formats), + .async_flip = true, }, { .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, .display_ver = { 12, 13 }, @@ -331,6 +338,7 @@ static const struct intel_modifier_desc intel_modifiers[] = { .ccs.packed_aux_planes = BIT(1), FORMAT_OVERRIDE(skl_ccs_formats), + .async_flip = true, }, { .modifier = I915_FORMAT_MOD_Y_TILED_CCS, .display_ver = { 9, 11 }, @@ -339,21 +347,26 @@ static const struct intel_modifier_desc intel_modifiers[] = { .ccs.packed_aux_planes = BIT(1), FORMAT_OVERRIDE(skl_ccs_formats), + .async_flip = true, }, { .modifier = I915_FORMAT_MOD_Yf_TILED, .display_ver = { 9, 11 }, .plane_caps = INTEL_PLANE_CAP_TILING_Yf, + .async_flip = true, }, { .modifier = I915_FORMAT_MOD_Y_TILED, .display_ver = { 9, 13 }, .plane_caps = INTEL_PLANE_CAP_TILING_Y, + .async_flip = true, }, { .modifier = I915_FORMAT_MOD_X_TILED, .display_ver = { 0, 29 }, .plane_caps = INTEL_PLANE_CAP_TILING_X, + .async_flip = true, }, { .modifier = DRM_FORMAT_MOD_LINEAR, .display_ver = DISPLAY_VER_ALL, + .async_flip = true, }, }; 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05 Nov 2024 02:35:54 -0800 X-CSE-ConnectionGUID: CP1RPsdXQyW9BJixwGSw+A== X-CSE-MsgGUID: FSf/r3PWRlGDnsl5jEme0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="83485571" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa006.fm.intel.com with ESMTP; 05 Nov 2024 02:35:52 -0800 From: Arun R Murthy To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Arun R Murthy Subject: [PATCH 3/4] drm/i915/display: Add async_flip flag in get_modifiers Date: Tue, 5 Nov 2024 15:56:07 +0530 Message-Id: <20241105102608.3912133-4-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241105102608.3912133-1-arun.r.murthy@intel.com> References: <20241105102608.3912133-1-arun.r.murthy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" get_modifiers will get the list of modifiers supported by the plane. Add a flag async_flip to fetch only the async_flip supported modifiers. Also expose function to get the number of modifiers supported by the platform. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/intel_cursor.c | 2 +- drivers/gpu/drm/i915/display/intel_fb.c | 40 +++++++++++++++---- drivers/gpu/drm/i915/display/intel_fb.h | 4 +- drivers/gpu/drm/i915/display/intel_sprite.c | 2 +- .../drm/i915/display/skl_universal_plane.c | 3 +- 6 files changed, 41 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 17a1e3801a85..08d8bb6c770e 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -973,7 +973,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) plane->disable_flip_done = ilk_primary_disable_flip_done; } - modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X); + modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X, false); if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 9ba77970dab7..a08f445fbcc7 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -1026,7 +1026,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) cursor->cursor.size = ~0; - modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE); + modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE, false); ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, 0, &intel_cursor_plane_funcs, diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index f05e0c444618..fba1b6fb38ad 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -554,7 +554,8 @@ static bool check_modifier_display_ver_range(const struct intel_modifier_desc *m static bool plane_has_modifier(struct drm_i915_private *i915, u8 plane_caps, - const struct intel_modifier_desc *md) + const struct intel_modifier_desc *md, + bool is_async_flip) { if (!IS_DISPLAY_VER(i915, md->display_ver.from, md->display_ver.until)) return false; @@ -562,6 +563,9 @@ static bool plane_has_modifier(struct drm_i915_private *i915, if (!plane_caps_contain_all(plane_caps, md->plane_caps)) return false; + if (!(is_async_flip && md->async_flip)) + return false; + /* * Separate AuxCCS and Flat CCS modifiers to be run only on platforms * where supported. @@ -581,26 +585,48 @@ static bool plane_has_modifier(struct drm_i915_private *i915, return true; } +/** + * intel_fb_plane_get_modifiers_count - return the number of supported modifiers for a + * given platform and plane capabilities + * @i915: i915 device instance + * @plane_caps: capabilities for the plane the modifiers are queried for + * @async_flip: flag to convey modifiers that support async flip + * + * Returns: + * Returns the number for modifiers supported by the @i915 platform and @plane_caps + * with/without @async_flip. + */ +int intel_fb_plane_get_modifiers_count(struct drm_i915_private *i915, + u8 plane_caps, bool async_flip) +{ + int count = 1; + int i; + + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { + if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i], async_flip)) + count++; + } + return count; +} + /** * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities * @i915: i915 device instance * @plane_caps: capabilities for the plane the modifiers are queried for + * @async_flip: flag to convey modifiers that support async flip * * Returns: * Returns the list of modifiers allowed by the @i915 platform and @plane_caps. * The caller must free the returned buffer. */ u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, - u8 plane_caps) + u8 plane_caps, bool async_flip) { u64 *list, *p; int count = 1; /* +1 for invalid modifier terminator */ int i; - for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { - if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) - count++; - } + count = intel_fb_plane_get_modifiers_count(i915, plane_caps, async_flip); list = kmalloc_array(count, sizeof(*list), GFP_KERNEL); if (drm_WARN_ON(&i915->drm, !list)) @@ -608,7 +634,7 @@ u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, p = list; for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { - if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) + if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i], async_flip)) *p++ = intel_modifiers[i].modifier; } *p++ = DRM_FORMAT_MOD_INVALID; diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index d78993e5eb62..4ae7cc75fe77 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -41,8 +41,10 @@ bool intel_fb_is_tile4_modifier(u64 modifier); bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane); int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb); +int intel_fb_plane_get_modifiers_count(struct drm_i915_private *i915, + u8 plane_caps, bool async_flip); u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, - u8 plane_caps); + u8 plane_caps, bool async_flip); bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier); const struct drm_format_info * diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index e6fadcef58e0..d1c5a3a3f13e 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -1685,7 +1685,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->id = PLANE_SPRITE0 + sprite; plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); - modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X); + modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X, false); ret = drm_universal_plane_init(display->drm, &plane->base, 0, plane_funcs, diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 038ca2ec5d7a..54cf2c9374cb 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2673,7 +2673,8 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane_type = DRM_PLANE_TYPE_OVERLAY; modifiers = intel_fb_plane_get_modifiers(dev_priv, - skl_get_plane_caps(dev_priv, pipe, plane_id)); + skl_get_plane_caps(dev_priv, pipe, plane_id), + false); ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 0, plane_funcs, From patchwork Tue Nov 5 10:26:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13862780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A326D12678 for ; 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X-CSE-ConnectionGUID: +VrqQ7SHSPy9VAiZ0jWbdg== X-CSE-MsgGUID: qANx2wkBSOa/Yl2UngiU7g== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="34230856" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="34230856" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Nov 2024 02:35:56 -0800 X-CSE-ConnectionGUID: 4kqE3FhDTUy9SdPcbFaklA== X-CSE-MsgGUID: 5TF/mbYOR8GzE+pllpstVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,259,1725346800"; d="scan'208";a="83485581" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa006.fm.intel.com with ESMTP; 05 Nov 2024 02:35:54 -0800 From: Arun R Murthy To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Arun R Murthy Subject: [PATCH 4/4] drm/i915/display: Add async supported formats/modifiers Date: Tue, 5 Nov 2024 15:56:08 +0530 Message-Id: <20241105102608.3912133-5-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241105102608.3912133-1-arun.r.murthy@intel.com> References: <20241105102608.3912133-1-arun.r.murthy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add the formats/modifiers supported by asynchronous flips by the platform based on the plane capabilities. Signed-off-by: Arun R Murthy --- .../drm/i915/display/skl_universal_plane.c | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 54cf2c9374cb..bead0c01af10 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -27,6 +27,18 @@ #include "skl_watermark.h" #include "pxp/intel_pxp.h" +static u32 skl_async_plane_formats[] = { + DRM_FORMAT_RGB565, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XRGB2101010, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_XRGB16161616F, + DRM_FORMAT_XBGR16161616F, +}; + static const u32 skl_plane_formats[] = { DRM_FORMAT_C8, DRM_FORMAT_RGB565, @@ -2660,6 +2672,9 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, formats = skl_get_plane_formats(dev_priv, pipe, plane_id, &num_formats); + plane->base.async_format_count = ARRAY_SIZE(skl_async_plane_formats); + plane->base.async_format_types = skl_async_plane_formats; + if (DISPLAY_VER(dev_priv) >= 12) plane_funcs = &tgl_plane_funcs; else if (DISPLAY_VER(dev_priv) == 11) @@ -2672,6 +2687,13 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, else plane_type = DRM_PLANE_TYPE_OVERLAY; + plane->base.async_modifier_count = intel_fb_plane_get_modifiers_count(dev_priv, + skl_get_plane_caps(dev_priv, pipe, plane_id), + true); + plane->base.async_modifiers = intel_fb_plane_get_modifiers(dev_priv, + skl_get_plane_caps(dev_priv, pipe, plane_id), + true); + modifiers = intel_fb_plane_get_modifiers(dev_priv, skl_get_plane_caps(dev_priv, pipe, plane_id), false);