From patchwork Wed Nov 6 21:58:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13865560 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 48BDBD59F7F for ; Wed, 6 Nov 2024 22:04:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 012E210E795; Wed, 6 Nov 2024 22:04:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="leW3ULPF"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id A695310E0BC for ; Wed, 6 Nov 2024 22:04:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730930655; x=1762466655; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=nG2s8edlRIMjebGn3GAKJHYKslhu9MhAlx5GxeBz784=; b=leW3ULPFfk6ixYxxd7/b52zzKExetzq45MRHBMRzFDEj5oyUnm3FI6Pa PyW0qb54S8xIek4IVnzw7LUTFlrwO/dOKEdbzN0Grq3ETBVYOxuf2wFXc v582nNbrC6fsJ0gcXNjbM32nA2t0ezJhFD0PCQ30Lc3rj8rbv0kMlBJ20 4wY+C4CmpGGSznKnXx+N8IGdAYR6yft3ZliZC/VcHzO9t0OxRhewDSscC ZRDXWPGO2eSJAShOz+s2+RXnvEZ4ZT6D1RQg4e5O9HkxN/c14IhSoZcJ3 qdS/3hSp24S0K9ZUIZ159eiyAxy37QTly4wNSYfdUIQQwMduEtPUE4yRx w==; X-CSE-ConnectionGUID: t4gKdDpQSlaPBPkXSzh7Eg== X-CSE-MsgGUID: R9NqLmtwQeaM1iVYZswRcQ== X-IronPort-AV: E=McAfee;i="6700,10204,11248"; a="42157316" X-IronPort-AV: E=Sophos;i="6.11,264,1725346800"; d="scan'208";a="42157316" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2024 14:04:08 -0800 X-CSE-ConnectionGUID: 9oOYhiTvRAiixri1CPdNGg== X-CSE-MsgGUID: d99Mzv42QC6dBXcHRoy53g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,264,1725346800"; d="scan'208";a="84879544" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Nov 2024 13:59:04 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 06 Nov 2024 23:59:02 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 1/8] drm/i915/pps: Store the power cycle delay without the +1 Date: Wed, 6 Nov 2024 23:58:52 +0200 Message-ID: <20241106215859.25446-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106215859.25446-1-ville.syrjala@linux.intel.com> References: <20241106215859.25446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The code initializing the power sequencing delays is a bit hard to follow. One confusing thing is that we keep doing the +/-1 adjustment for the hardware register value in several places. Simplify this a bit by doing the adjustment only when reading or writing the actual register. This also matches how the LVDS code does things. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pps.c | 28 ++++++++++-------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 093fe37a3983..83d65105f32b 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -1390,7 +1390,7 @@ static void intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) { struct intel_display *display = to_intel_display(intel_dp); - u32 pp_on, pp_off, pp_ctl; + u32 pp_on, pp_off, pp_ctl, power_cycle_delay; struct pps_registers regs; intel_pps_get_registers(intel_dp, ®s); @@ -1415,10 +1415,13 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) pp_div = intel_de_read(display, regs.pp_div); - seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; + power_cycle_delay = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div); } else { - seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; + power_cycle_delay = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl); } + + /* hardware wants +1 in 100ms units */ + seq->t11_t12 = power_cycle_delay ? (power_cycle_delay - 1) * 1000 : 0; } static void @@ -1494,12 +1497,6 @@ static void pps_init_delays_vbt(struct intel_dp *intel_dp, vbt->t11_t12); } - /* T11_T12 delay is special and actually in units of 100ms, but zero - * based in the hw (so we need to add 100 ms). But the sw vbt - * table multiplies it with 1000 to make it in units of 100usec, - * too. */ - vbt->t11_t12 += 100 * 10; - intel_pps_dump_state(intel_dp, "vbt", vbt); } @@ -1516,11 +1513,7 @@ static void pps_init_delays_spec(struct intel_dp *intel_dp, spec->t8 = 50 * 10; /* no limit for t8, use t7 instead */ spec->t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ spec->t10 = 500 * 10; - /* This one is special and actually in units of 100ms, but zero - * based in the hw (so we need to add 100 ms). But the sw vbt - * table multiplies it with 1000 to make it in units of 100usec, - * too. */ - spec->t11_t12 = (510 + 100) * 10; + spec->t11_t12 = 510 * 10; intel_pps_dump_state(intel_dp, "spec", spec); } @@ -1665,11 +1658,14 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd */ if (i915_mmio_reg_valid(regs.pp_div)) intel_de_write(display, regs.pp_div, - REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); + REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, + (100 * div) / 2 - 1) | + REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, + DIV_ROUND_UP(seq->t11_t12, 1000) + 1)); else intel_de_rmw(display, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK, REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, - DIV_ROUND_UP(seq->t11_t12, 1000))); + DIV_ROUND_UP(seq->t11_t12, 1000) + 1)); drm_dbg_kms(display->drm, "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", From patchwork Wed Nov 6 21:58:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13865557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5B94D59F7D for ; Wed, 6 Nov 2024 22:04:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4FC8310E784; Wed, 6 Nov 2024 22:04:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="JAatSVqH"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1079F10E782 for ; Wed, 6 Nov 2024 22:04:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730930654; x=1762466654; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=tu7cwYInbyNms5Y2hHqaDE+XD/Q0WuAOqO1YytzyiUE=; b=JAatSVqHvKjO09/WNCLk5byw+L3T9ymqPdGLbOP/uuqSjCA7XqR4VZal NQYCUEMhmBzpm1OSXkc4WXl63mt6wgUVP32RtAs/ZBSeWJXECmOtdozC0 Q5pozO0pdMYK8BwHfCuUciLZe1cvr1fYQZp+dhm5ViHstPcGjOM5496/p Ujc7CXatyHK2pB9qXgZZE2bQhLWmpnjf7hlVt651Cz6zBBRlmc2KPuXGl +lxOlHW325laIW38+XKlWDEWf4BmFN+xJDDKdjoVD7I2nPv4eH0Cwkd1v vrnO8bUp5UpXkCpfNqB2lF1AV3Krfo94WQFe33gLBf/R2yp76R9OUvCV0 g==; X-CSE-ConnectionGUID: VB1J9cYORKu+DoeTAkgxhw== X-CSE-MsgGUID: qFqSeQk5Rp+s6RvOn6VQ0w== X-IronPort-AV: E=McAfee;i="6700,10204,11248"; a="42157320" X-IronPort-AV: E=Sophos;i="6.11,264,1725346800"; d="scan'208";a="42157320" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2024 14:04:09 -0800 X-CSE-ConnectionGUID: cWntgSzUT56s5xFPIeb8QA== X-CSE-MsgGUID: ZXZRRR+/RWmriehwFBDliA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,264,1725346800"; d="scan'208";a="84879548" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Nov 2024 13:59:06 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 06 Nov 2024 23:59:05 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 2/8] drm/i915/pps: Decouple pps delays from VBT struct definition Date: Wed, 6 Nov 2024 23:58:53 +0200 Message-ID: <20241106215859.25446-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106215859.25446-1-ville.syrjala@linux.intel.com> References: <20241106215859.25446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We currently lack a proper struct definition for the VBT power squecing delays, and instead we use the same struct definition (in intel_bios.h) for both the VBT layout and our driver side state. Decouple those two things by moving the current struct into intel_vbt_defs.h and adding a new one for the driver's use. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bios.c | 15 +++++++++++--- drivers/gpu/drm/i915/display/intel_bios.h | 8 -------- .../drm/i915/display/intel_display_types.h | 15 +++++++++++--- drivers/gpu/drm/i915/display/intel_dp_aux.c | 1 - drivers/gpu/drm/i915/display/intel_pps.c | 20 +++++++++---------- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 8 ++++++++ 6 files changed, 42 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index a4cdd82c4a75..31398de08e7f 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1402,12 +1402,21 @@ parse_power_conservation_features(struct intel_display *display, panel_type); } +static void vbt_edp_to_pps_delays(struct intel_pps_delays *pps, + const struct edp_power_seq *edp_pps) +{ + pps->t1_t3 = edp_pps->t1_t3; + pps->t8 = edp_pps->t8; + pps->t9 = edp_pps->t9; + pps->t10 = edp_pps->t10; + pps->t11_t12 = edp_pps->t11_t12; +} + static void parse_edp(struct intel_display *display, struct intel_panel *panel) { const struct bdb_edp *edp; - const struct edp_power_seq *edp_pps; const struct edp_fast_link_params *edp_link_params; int panel_type = panel->vbt.panel_type; @@ -1428,10 +1437,10 @@ parse_edp(struct intel_display *display, } /* Get the eDP sequencing and link info */ - edp_pps = &edp->power_seqs[panel_type]; edp_link_params = &edp->fast_link_params[panel_type]; - panel->vbt.edp.pps = *edp_pps; + vbt_edp_to_pps_delays(&panel->vbt.edp.pps, + &edp->power_seqs[panel_type]); if (display->vbt.version >= 224) { panel->vbt.edp.rate = diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h index 8b703f6cfe17..f9841f0498c6 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.h +++ b/drivers/gpu/drm/i915/display/intel_bios.h @@ -50,14 +50,6 @@ enum intel_backlight_type { INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE, }; -struct edp_power_seq { - u16 t1_t3; - u16 t8; - u16 t9; - u16 t10; - u16 t11_t12; -} __packed; - /* * MIPI Sequence Block definitions * diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index d3a1aa7c919f..62cf5d007872 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -301,6 +301,15 @@ struct intel_panel_bl_funcs { u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz); }; +/* in 100us units */ +struct intel_pps_delays { + u16 t1_t3; + u16 t8; + u16 t9; + u16 t10; + u16 t11_t12; +}; + enum drrs_type { DRRS_TYPE_NONE, DRRS_TYPE_STATIC, @@ -328,7 +337,7 @@ struct intel_vbt_panel_data { int preemphasis; int vswing; int bpp; - struct edp_power_seq pps; + struct intel_pps_delays pps; u8 drrs_msa_timing_delay; bool low_vswing; bool hobl; @@ -1568,8 +1577,8 @@ struct intel_pps { * requiring a reinitialization. Only relevant on BXT+. */ bool bxt_pps_reset; - struct edp_power_seq pps_delays; - struct edp_power_seq bios_pps_delays; + struct intel_pps_delays pps_delays; + struct intel_pps_delays bios_pps_delays; }; struct intel_psr { diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index 04a7acd7f73c..7daa8a95dc70 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -6,7 +6,6 @@ #include "i915_drv.h" #include "i915_reg.h" #include "i915_trace.h" -#include "intel_bios.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_dp.h" diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 83d65105f32b..c57b9aca5a31 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -1387,7 +1387,7 @@ static void pps_init_timestamps(struct intel_dp *intel_dp) } static void -intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) +intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct intel_pps_delays *seq) { struct intel_display *display = to_intel_display(intel_dp); u32 pp_on, pp_off, pp_ctl, power_cycle_delay; @@ -1426,7 +1426,7 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) static void intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name, - const struct edp_power_seq *seq) + const struct intel_pps_delays *seq) { struct intel_display *display = to_intel_display(intel_dp); @@ -1440,8 +1440,8 @@ static void intel_pps_verify_state(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct edp_power_seq hw; - struct edp_power_seq *sw = &intel_dp->pps.pps_delays; + struct intel_pps_delays hw; + struct intel_pps_delays *sw = &intel_dp->pps.pps_delays; intel_pps_readout_hw_state(intel_dp, &hw); @@ -1453,14 +1453,14 @@ intel_pps_verify_state(struct intel_dp *intel_dp) } } -static bool pps_delays_valid(struct edp_power_seq *delays) +static bool pps_delays_valid(struct intel_pps_delays *delays) { return delays->t1_t3 || delays->t8 || delays->t9 || delays->t10 || delays->t11_t12; } static void pps_init_delays_bios(struct intel_dp *intel_dp, - struct edp_power_seq *bios) + struct intel_pps_delays *bios) { struct intel_display *display = to_intel_display(intel_dp); @@ -1475,7 +1475,7 @@ static void pps_init_delays_bios(struct intel_dp *intel_dp, } static void pps_init_delays_vbt(struct intel_dp *intel_dp, - struct edp_power_seq *vbt) + struct intel_pps_delays *vbt) { struct intel_display *display = to_intel_display(intel_dp); struct intel_connector *connector = intel_dp->attached_connector; @@ -1501,7 +1501,7 @@ static void pps_init_delays_vbt(struct intel_dp *intel_dp, } static void pps_init_delays_spec(struct intel_dp *intel_dp, - struct edp_power_seq *spec) + struct intel_pps_delays *spec) { struct intel_display *display = to_intel_display(intel_dp); @@ -1521,7 +1521,7 @@ static void pps_init_delays_spec(struct intel_dp *intel_dp, static void pps_init_delays(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct edp_power_seq cur, vbt, spec, + struct intel_pps_delays cur, vbt, spec, *final = &intel_dp->pps.pps_delays; lockdep_assert_held(&display->pps.mutex); @@ -1589,7 +1589,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000; struct pps_registers regs; enum port port = dp_to_dig_port(intel_dp)->base.port; - const struct edp_power_seq *seq = &intel_dp->pps.pps_delays; + const struct intel_pps_delays *seq = &intel_dp->pps.pps_delays; lockdep_assert_held(&display->pps.mutex); diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 42022756bbd5..e9b809568cd4 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -1014,6 +1014,14 @@ struct bdb_tv_options { * Block 27 - eDP VBT Block */ +struct edp_power_seq { + u16 t1_t3; + u16 t8; + u16 t9; + u16 t10; + u16 t11_t12; +} __packed; + #define EDP_18BPP 0 #define EDP_24BPP 1 #define EDP_30BPP 2 From patchwork Wed Nov 6 21:58:54 2024 Content-Type: text/plain; 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d="scan'208";a="84879552" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Nov 2024 13:59:09 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 06 Nov 2024 23:59:07 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 3/8] drm/i915/pps: Rename intel_pps_delay members Date: Wed, 6 Nov 2024 23:58:54 +0200 Message-ID: <20241106215859.25446-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106215859.25446-1-ville.syrjala@linux.intel.com> References: <20241106215859.25446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Stop using the semi-random eDP spec T1,T3,... names for the power sequencing delays, and instead call them by their human readable names. Much easier to keep track what delay goes where when you don't have to constantly cross reference against the eDP spec. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bios.c | 10 +- .../drm/i915/display/intel_display_types.h | 10 +- drivers/gpu/drm/i915/display/intel_pps.c | 92 ++++++++++--------- 3 files changed, 58 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 31398de08e7f..e0e4e9b62d8d 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1405,11 +1405,11 @@ parse_power_conservation_features(struct intel_display *display, static void vbt_edp_to_pps_delays(struct intel_pps_delays *pps, const struct edp_power_seq *edp_pps) { - pps->t1_t3 = edp_pps->t1_t3; - pps->t8 = edp_pps->t8; - pps->t9 = edp_pps->t9; - pps->t10 = edp_pps->t10; - pps->t11_t12 = edp_pps->t11_t12; + pps->power_up = edp_pps->t1_t3; + pps->backlight_on = edp_pps->t8; + pps->backlight_off = edp_pps->t9; + pps->power_down = edp_pps->t10; + pps->power_cycle = edp_pps->t11_t12; } static void diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 62cf5d007872..4af40315b410 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -303,11 +303,11 @@ struct intel_panel_bl_funcs { /* in 100us units */ struct intel_pps_delays { - u16 t1_t3; - u16 t8; - u16 t9; - u16 t10; - u16 t11_t12; + u16 power_up; /* eDP: T1+T3 */ + u16 backlight_on; /* eDP: T8 */ + u16 backlight_off; /* eDP: T9 */ + u16 power_down; /* eDP: T10 */ + u16 power_cycle; /* eDP: T11+T12 */ }; enum drrs_type { diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index c57b9aca5a31..ed52f84d4cf3 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -676,7 +676,7 @@ static void wait_panel_power_cycle(struct intel_dp *intel_dp) pps_name(intel_dp)); /* take the difference of current time and panel power off time - * and then make panel wait for t11_t12 if needed. */ + * and then make panel wait for power_cycle if needed. */ panel_power_on_time = ktime_get_boottime(); panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time); @@ -1405,10 +1405,10 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct intel_pps_delays *s pp_off = intel_de_read(display, regs.pp_off); /* Pull timing values out of registers */ - seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); - seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); - seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); - seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); + seq->power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); + seq->backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); + seq->backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); + seq->power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); if (i915_mmio_reg_valid(regs.pp_div)) { u32 pp_div; @@ -1421,7 +1421,7 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct intel_pps_delays *s } /* hardware wants +1 in 100ms units */ - seq->t11_t12 = power_cycle_delay ? (power_cycle_delay - 1) * 1000 : 0; + seq->power_cycle = power_cycle_delay ? (power_cycle_delay - 1) * 1000 : 0; } static void @@ -1431,9 +1431,9 @@ intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name, struct intel_display *display = to_intel_display(intel_dp); drm_dbg_kms(display->drm, - "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", - state_name, - seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); + "%s power_up %d backlight_on %d backlight_off %d power_down %d power_cycle %d\n", + state_name, seq->power_up, seq->backlight_on, + seq->backlight_off, seq->power_down, seq->power_cycle); } static void @@ -1445,8 +1445,11 @@ intel_pps_verify_state(struct intel_dp *intel_dp) intel_pps_readout_hw_state(intel_dp, &hw); - if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || - hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { + if (hw.power_up != sw->power_up || + hw.backlight_on != sw->backlight_on || + hw.backlight_off != sw->backlight_off || + hw.power_down != sw->power_down || + hw.power_cycle != sw->power_cycle) { drm_err(display->drm, "PPS state mismatch\n"); intel_pps_dump_state(intel_dp, "sw", sw); intel_pps_dump_state(intel_dp, "hw", &hw); @@ -1455,8 +1458,8 @@ intel_pps_verify_state(struct intel_dp *intel_dp) static bool pps_delays_valid(struct intel_pps_delays *delays) { - return delays->t1_t3 || delays->t8 || delays->t9 || - delays->t10 || delays->t11_t12; + return delays->power_up || delays->backlight_on || delays->backlight_off || + delays->power_down || delays->power_cycle; } static void pps_init_delays_bios(struct intel_dp *intel_dp, @@ -1491,10 +1494,10 @@ static void pps_init_delays_vbt(struct intel_dp *intel_dp, * seems sufficient to avoid this problem. */ if (intel_has_quirk(display, QUIRK_INCREASE_T12_DELAY)) { - vbt->t11_t12 = max_t(u16, vbt->t11_t12, 1300 * 10); + vbt->power_cycle = max_t(u16, vbt->power_cycle, 1300 * 10); drm_dbg_kms(display->drm, "Increasing T12 panel delay as per the quirk to %d\n", - vbt->t11_t12); + vbt->power_cycle); } intel_pps_dump_state(intel_dp, "vbt", vbt); @@ -1509,11 +1512,11 @@ static void pps_init_delays_spec(struct intel_dp *intel_dp, /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of * our hw here, which are all in 100usec. */ - spec->t1_t3 = 210 * 10; - spec->t8 = 50 * 10; /* no limit for t8, use t7 instead */ - spec->t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ - spec->t10 = 500 * 10; - spec->t11_t12 = 510 * 10; + spec->power_up = 210 * 10; /* T1+T3 */ + spec->backlight_on = 50 * 10; /* no limit for T8, use T7 instead */ + spec->backlight_off = 50 * 10; /* no limit for T9, make it symmetric with T8 */ + spec->power_down = 500 * 10; /* T10 */ + spec->power_cycle = 510 * 10; /* T11+T12 */ intel_pps_dump_state(intel_dp, "spec", spec); } @@ -1539,19 +1542,19 @@ static void pps_init_delays(struct intel_dp *intel_dp) #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ spec.field : \ max(cur.field, vbt.field)) - assign_final(t1_t3); - assign_final(t8); - assign_final(t9); - assign_final(t10); - assign_final(t11_t12); + assign_final(power_up); + assign_final(backlight_on); + assign_final(backlight_off); + assign_final(power_down); + assign_final(power_cycle); #undef assign_final #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) - intel_dp->pps.panel_power_up_delay = get_delay(t1_t3); - intel_dp->pps.backlight_on_delay = get_delay(t8); - intel_dp->pps.backlight_off_delay = get_delay(t9); - intel_dp->pps.panel_power_down_delay = get_delay(t10); - intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12); + intel_dp->pps.panel_power_up_delay = get_delay(power_up); + intel_dp->pps.backlight_on_delay = get_delay(backlight_on); + intel_dp->pps.backlight_off_delay = get_delay(backlight_off); + intel_dp->pps.panel_power_down_delay = get_delay(power_down); + intel_dp->pps.panel_power_cycle_delay = get_delay(power_cycle); #undef get_delay drm_dbg_kms(display->drm, @@ -1566,19 +1569,20 @@ static void pps_init_delays(struct intel_dp *intel_dp) /* * We override the HW backlight delays to 1 because we do manual waits - * on them. For T8, even BSpec recommends doing it. For T9, if we - * don't do this, we'll end up waiting for the backlight off delay - * twice: once when we do the manual sleep, and once when we disable - * the panel and wait for the PP_STATUS bit to become zero. + * on them. For backlight_on, even BSpec recommends doing it. For + * backlight_off, if we don't do this, we'll end up waiting for the + * backlight off delay twice: once when we do the manual sleep, and + * once when we disable the panel and wait for the PP_STATUS bit to + * become zero. */ - final->t8 = 1; - final->t9 = 1; + final->backlight_on = 1; + final->backlight_off = 1; /* - * HW has only a 100msec granularity for t11_t12 so round it up + * HW has only a 100msec granularity for power_cycle so round it up * accordingly. */ - final->t11_t12 = roundup(final->t11_t12, 100 * 10); + final->power_cycle = roundup(final->power_cycle, 100 * 10); } static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd) @@ -1622,10 +1626,10 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd intel_de_write(display, regs.pp_ctrl, pp); } - pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | - REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); - pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | - REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); + pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->power_up) | + REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->backlight_on); + pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->backlight_off) | + REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->power_down); /* Haswell doesn't have any port selection bits for the panel * power sequencer any more. */ @@ -1661,11 +1665,11 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, - DIV_ROUND_UP(seq->t11_t12, 1000) + 1)); + DIV_ROUND_UP(seq->power_cycle, 1000) + 1)); else intel_de_rmw(display, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK, REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, - DIV_ROUND_UP(seq->t11_t12, 1000) + 1)); + DIV_ROUND_UP(seq->power_cycle, 1000) + 1)); drm_dbg_kms(display->drm, "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", From patchwork Wed Nov 6 21:58:55 2024 Content-Type: text/plain; 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d="scan'208";a="84879554" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Nov 2024 13:59:12 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 06 Nov 2024 23:59:10 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 4/8] drm/i915/lvds: Use struct intel_pps_delays for LVDS power sequencing Date: Wed, 6 Nov 2024 23:58:55 +0200 Message-ID: <20241106215859.25446-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106215859.25446-1-ville.syrjala@linux.intel.com> References: <20241106215859.25446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Reuse struct intel_pps_delays for the LVDS power sequencing delays insteda of hand rolling it all. Perhaps in the future we could reuse some of the same PPS code for both LVDS and eDP (assuming we can decouple the PPS code from intel_dp...). Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- .../drm/i915/display/intel_display_types.h | 10 ++-- drivers/gpu/drm/i915/display/intel_lvds.c | 49 ++++++++++--------- 2 files changed, 30 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4af40315b410..961c81681d6f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -303,11 +303,11 @@ struct intel_panel_bl_funcs { /* in 100us units */ struct intel_pps_delays { - u16 power_up; /* eDP: T1+T3 */ - u16 backlight_on; /* eDP: T8 */ - u16 backlight_off; /* eDP: T9 */ - u16 power_down; /* eDP: T10 */ - u16 power_cycle; /* eDP: T11+T12 */ + u16 power_up; /* eDP: T1+T3, LVDS: T1+T2 */ + u16 backlight_on; /* eDP: T8, LVDS: T5 */ + u16 backlight_off; /* eDP: T9, LVDS: T6/TX */ + u16 power_down; /* eDP: T10, LVDS: T3 */ + u16 power_cycle; /* eDP: T11+T12, LVDS: T7+T4 */ }; enum drrs_type { diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 6d7637ad980a..6ffd55c17445 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -57,12 +57,7 @@ /* Private structure for the integrated LVDS support */ struct intel_lvds_pps { - /* 100us units */ - int t1_t2; - int t3; - int t4; - int t5; - int tx; + struct intel_pps_delays delays; int divider; @@ -168,12 +163,12 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, val = intel_de_read(dev_priv, PP_ON_DELAYS(dev_priv, 0)); pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); - pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); - pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); + pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); + pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); val = intel_de_read(dev_priv, PP_OFF_DELAYS(dev_priv, 0)); - pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); - pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); + pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); + pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); val = intel_de_read(dev_priv, PP_DIVISOR(dev_priv, 0)); pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); @@ -186,25 +181,30 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, if (val) val--; /* Convert from 100ms to 100us units */ - pps->t4 = val * 1000; + pps->delays.power_cycle = val * 1000; if (DISPLAY_VER(dev_priv) < 5 && - pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { + pps->delays.power_up == 0 && + pps->delays.backlight_on == 0 && + pps->delays.power_down == 0 && + pps->delays.backlight_off == 0) { drm_dbg_kms(&dev_priv->drm, "Panel power timings uninitialized, " "setting defaults\n"); /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ - pps->t1_t2 = 40 * 10; - pps->t5 = 200 * 10; + pps->delays.power_up = 40 * 10; + pps->delays.backlight_on = 200 * 10; /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ - pps->t3 = 35 * 10; - pps->tx = 200 * 10; + pps->delays.power_down = 35 * 10; + pps->delays.backlight_off = 200 * 10; } - drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " + drm_dbg(&dev_priv->drm, "LVDS PPS:power_up %d power_down %d power_cycle %d backlight_on %d backlight_off %d " "divider %d port %d powerdown_on_reset %d\n", - pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, - pps->divider, pps->port, pps->powerdown_on_reset); + pps->delays.power_up, pps->delays.power_down, + pps->delays.power_cycle, pps->delays.backlight_on, + pps->delays.backlight_off, pps->divider, + pps->port, pps->powerdown_on_reset); } static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, @@ -221,16 +221,17 @@ static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, intel_de_write(dev_priv, PP_ON_DELAYS(dev_priv, 0), REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | - REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | - REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); + REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->delays.power_up) | + REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->delays.backlight_on)); intel_de_write(dev_priv, PP_OFF_DELAYS(dev_priv, 0), - REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | - REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); + REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->delays.power_down) | + REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->delays.backlight_off)); intel_de_write(dev_priv, PP_DIVISOR(dev_priv, 0), REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | - REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); + REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, + DIV_ROUND_UP(pps->delays.power_cycle, 1000) + 1)); } static void intel_pre_enable_lvds(struct intel_atomic_state *state, From patchwork Wed Nov 6 21:58:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13865563 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D73F6D59F7D for ; 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X-CSE-ConnectionGUID: pRgYFMKmReOc2gv+ZJQ7uw== X-CSE-MsgGUID: bjcfh9pZQPOvnEy/ZMSpzA== X-IronPort-AV: E=McAfee;i="6700,10204,11248"; a="42157321" X-IronPort-AV: E=Sophos;i="6.11,264,1725346800"; d="scan'208";a="42157321" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2024 14:04:09 -0800 X-CSE-ConnectionGUID: WMODeUmLQSyP8ZnrdIeVjQ== X-CSE-MsgGUID: bU/p6WfFQiWlfa31OmXnBA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,264,1725346800"; d="scan'208";a="84879556" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Nov 2024 13:59:15 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 06 Nov 2024 23:59:13 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 5/8] drm/i915/pps: Spell out the eDP spec power sequencing delays a bit more clearly Date: Wed, 6 Nov 2024 23:58:56 +0200 Message-ID: <20241106215859.25446-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106215859.25446-1-ville.syrjala@linux.intel.com> References: <20241106215859.25446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We determine the "spec" eDP power sequencing delays by refercing some max values from the eDP spec. Write out each number from the spec explicitly instead of precomputing the final number (that's the job of the computer). Makes it a bit easier to see what the supposed spec defined numbers actually are. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pps.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index ed52f84d4cf3..6946ba0004eb 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -1512,11 +1512,11 @@ static void pps_init_delays_spec(struct intel_dp *intel_dp, /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of * our hw here, which are all in 100usec. */ - spec->power_up = 210 * 10; /* T1+T3 */ + spec->power_up = (10 + 200) * 10; /* T1+T3 */ spec->backlight_on = 50 * 10; /* no limit for T8, use T7 instead */ spec->backlight_off = 50 * 10; /* no limit for T9, make it symmetric with T8 */ spec->power_down = 500 * 10; /* T10 */ - spec->power_cycle = 510 * 10; /* T11+T12 */ + spec->power_cycle = (10 + 500) * 10; /* T11+T12 */ intel_pps_dump_state(intel_dp, "spec", spec); } From patchwork Wed Nov 6 21:58:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13865562 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AFE69D59F78 for ; Wed, 6 Nov 2024 22:04:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B73D710E794; Wed, 6 Nov 2024 22:04:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="eYvL7/q+"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id C1E0B10E784 for ; Wed, 6 Nov 2024 22:04:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730930655; x=1762466655; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ifbOk6oordk8aMah7bf3M3sZmRa3wc7uzHY4m7c6WMw=; b=eYvL7/q+GvOykx/XERvn5dGxfAKMtrq4MJyDz3yU3VqZk3bI7seIDleU ZNpfoqGtbzHV9Zl74ISi81WpnnF6HaGg6g1ttmUM/7nEYkQSi9OcL9qx9 hrN4pIlh+j3akU7mkSO7JhTiDlvrSGhokFGS4lC9boW2sMU++k4GF9d8C vL1r8CIcYyU2izkkQLqUyleBKODC7wwdLDJbUIkAKkiBn1mZfigaI3PnY +6UuG+VSUZoD+fakkqDVUM5NTPMyhyjh/upFm3/5vbhUqsfbHVP/5/BuS WvyOFXk9VK6Ewhs54j7VWevdK3/bCF7tazyNyVSSP6rVtEVJeGWJ4mbwu w==; X-CSE-ConnectionGUID: Bcu/k5QVS1yAsaU0qCe5+w== X-CSE-MsgGUID: ZyM75PEbTr+1fbpo7PyjdQ== X-IronPort-AV: E=McAfee;i="6700,10204,11248"; a="42157322" X-IronPort-AV: E=Sophos;i="6.11,264,1725346800"; d="scan'208";a="42157322" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2024 14:04:09 -0800 X-CSE-ConnectionGUID: dJnjo2NPTbWjFjFU1EF3XA== X-CSE-MsgGUID: 3qjGNnW+Q+2PnF4JrwHNfg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,264,1725346800"; d="scan'208";a="84879559" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Nov 2024 13:59:17 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 06 Nov 2024 23:59:16 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 6/8] drm/i915/pps: Extract msecs_to_pps_units() Date: Wed, 6 Nov 2024 23:58:57 +0200 Message-ID: <20241106215859.25446-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106215859.25446-1-ville.syrjala@linux.intel.com> References: <20241106215859.25446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Replace all the hand rolled *10 stuff with something a bit more descriptive (msecs_to_pps_units()). Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pps.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 6946ba0004eb..5be2903c6aaf 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -1462,6 +1462,12 @@ static bool pps_delays_valid(struct intel_pps_delays *delays) delays->power_down || delays->power_cycle; } +static int msecs_to_pps_units(int msecs) +{ + /* PPS uses 100us units */ + return msecs * 10; +} + static void pps_init_delays_bios(struct intel_dp *intel_dp, struct intel_pps_delays *bios) { @@ -1494,7 +1500,7 @@ static void pps_init_delays_vbt(struct intel_dp *intel_dp, * seems sufficient to avoid this problem. */ if (intel_has_quirk(display, QUIRK_INCREASE_T12_DELAY)) { - vbt->power_cycle = max_t(u16, vbt->power_cycle, 1300 * 10); + vbt->power_cycle = max_t(u16, vbt->power_cycle, msecs_to_pps_units(1300)); drm_dbg_kms(display->drm, "Increasing T12 panel delay as per the quirk to %d\n", vbt->power_cycle); @@ -1510,13 +1516,12 @@ static void pps_init_delays_spec(struct intel_dp *intel_dp, lockdep_assert_held(&display->pps.mutex); - /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of - * our hw here, which are all in 100usec. */ - spec->power_up = (10 + 200) * 10; /* T1+T3 */ - spec->backlight_on = 50 * 10; /* no limit for T8, use T7 instead */ - spec->backlight_off = 50 * 10; /* no limit for T9, make it symmetric with T8 */ - spec->power_down = 500 * 10; /* T10 */ - spec->power_cycle = (10 + 500) * 10; /* T11+T12 */ + /* Upper limits from eDP 1.3 spec */ + spec->power_up = msecs_to_pps_units(10 + 200); /* T1+T3 */ + spec->backlight_on = msecs_to_pps_units(50); /* no limit for T8, use T7 instead */ + spec->backlight_off = msecs_to_pps_units(50); /* no limit for T9, make it symmetric with T8 */ + spec->power_down = msecs_to_pps_units(500); /* T10 */ + spec->power_cycle = msecs_to_pps_units(10 + 500); /* T11+T12 */ intel_pps_dump_state(intel_dp, "spec", spec); } @@ -1582,7 +1587,7 @@ static void pps_init_delays(struct intel_dp *intel_dp) * HW has only a 100msec granularity for power_cycle so round it up * accordingly. */ - final->power_cycle = roundup(final->power_cycle, 100 * 10); + final->power_cycle = roundup(final->power_cycle, msecs_to_pps_units(100)); } static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd) From patchwork Wed Nov 6 21:58:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13865561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22677D59F7E for ; Wed, 6 Nov 2024 22:04:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 52E7410E791; Wed, 6 Nov 2024 22:04:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bHSqlMiW"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6907510E782 for ; Wed, 6 Nov 2024 22:04:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730930654; x=1762466654; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=N2KFMqvdIQH37pV8DztH2bfHM0WH2iPc7NlLaxyd0ac=; b=bHSqlMiWRrEEyPOYyCXh3ujTFcWMLWsDMs0O09ZzMy7znbKB2n3JZME4 WwxpGHmNxcHu3UAEpT6Lm1PHTS1QglfXP5LKGV+pjjI57f3T+quMHbBZ2 1JzlcYnjLu7uzZVbF5L6BqtgWVH4utXsHPAZsvuryhoaj/pusqHGwNgtV v5MvFXRBNR6jGJIc9gn1UQsx1i+riUY1PaYczp/sKHW8eQ0YWsGzgJbqm bDcqsaw+cD82Ru6CJomY0MRR9iuPkotY331sVgQZxLmw8jwBL6lcaL5sg HyPG9G/DLWvdEKCVQ3xqfnAviK6jm6a6nKus82EC/ctFH0FpV8kp4cyz7 w==; X-CSE-ConnectionGUID: jLn+hmXrTs+Wp0t8adBzFw== X-CSE-MsgGUID: giSZstCCT0aY+gHnFyc7Iw== X-IronPort-AV: E=McAfee;i="6700,10204,11248"; a="42157323" X-IronPort-AV: E=Sophos;i="6.11,264,1725346800"; d="scan'208";a="42157323" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2024 14:04:09 -0800 X-CSE-ConnectionGUID: RvzJxoE0QyWh0kKIpKwWyg== X-CSE-MsgGUID: yAxL8iKTR8ysB3GxTE47/Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,264,1725346800"; d="scan'208";a="84879561" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Nov 2024 13:59:20 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 06 Nov 2024 23:59:19 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 7/8] drm/i915/pps: Extract pps_units_to_msecs() Date: Wed, 6 Nov 2024 23:58:58 +0200 Message-ID: <20241106215859.25446-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106215859.25446-1-ville.syrjala@linux.intel.com> References: <20241106215859.25446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Add pps_units_to_msecs() as the counterpart to msecs_pps_units_to(). Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pps.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 5be2903c6aaf..378a525eec16 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -1468,6 +1468,12 @@ static int msecs_to_pps_units(int msecs) return msecs * 10; } +static int pps_units_to_msecs(int val) +{ + /* PPS uses 100us units */ + return DIV_ROUND_UP(val, 10); +} + static void pps_init_delays_bios(struct intel_dp *intel_dp, struct intel_pps_delays *bios) { @@ -1554,7 +1560,7 @@ static void pps_init_delays(struct intel_dp *intel_dp) assign_final(power_cycle); #undef assign_final -#define get_delay(field) (DIV_ROUND_UP(final->field, 10)) +#define get_delay(field) pps_units_to_msecs(final->field) intel_dp->pps.panel_power_up_delay = get_delay(power_up); intel_dp->pps.backlight_on_delay = get_delay(backlight_on); intel_dp->pps.backlight_off_delay = get_delay(backlight_off); From patchwork Wed Nov 6 21:58:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13865555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 450D3D59F75 for ; Wed, 6 Nov 2024 22:04:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C5F7110E0BC; Wed, 6 Nov 2024 22:04:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="g5SB2ubK"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id EA68D10E0BC for ; Wed, 6 Nov 2024 22:04:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730930654; x=1762466654; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=CoQwGlu58bXh9l9MkL/aE6sACsol59EXptdiRhrmIgg=; b=g5SB2ubKuR3P7BXFTWjFwS7FT6DlIH045KiHlF4QhNdIoVjn21Br6RCN OV11ROY2jfhlvgSkTNalS1mMltFYS+joxF/K3Q6SaDJSfDflzzsQWlnaE 9pPW+MOZZBst0ey+rrm7wqBrG4J2r+BVEB7bIat6fEAjnzdtfGSMpmPwx NzWL37hWo+TQG7QshFsEhZBxrHQHY41BDSgS8IitgGhuOjHjQsqPU+pTI Iw7YGq1lOY0l4CRUOpJKotmCvmWE034OD1AFnv3BjUM3RgN2QIPQj34QJ 8/gJEKxLArcsU1SeUQ5mWgttSlPAOzcD0wGH2qKpaOGsULK6ZmT1Bf/Uz w==; X-CSE-ConnectionGUID: MA/FtGHSTsGbeQS9HHwjhA== X-CSE-MsgGUID: iGZKYkjaS8yHLkX+De11eA== X-IronPort-AV: E=McAfee;i="6700,10204,11248"; a="42157324" X-IronPort-AV: E=Sophos;i="6.11,264,1725346800"; d="scan'208";a="42157324" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2024 14:04:09 -0800 X-CSE-ConnectionGUID: 5/RjfJLMQCqsBJpuRCaP0Q== X-CSE-MsgGUID: y3DUBTaSRRmwd0q/CcPPDA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,264,1725346800"; d="scan'208";a="84879566" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 06 Nov 2024 13:59:23 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 06 Nov 2024 23:59:22 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 8/8] drm/i915/pps: Eliminate pointless get_delay() macro Date: Wed, 6 Nov 2024 23:58:59 +0200 Message-ID: <20241106215859.25446-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106215859.25446-1-ville.syrjala@linux.intel.com> References: <20241106215859.25446-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Now that we have pps_units_to_msecs(), get_delay() looks rather pointless. Nuke it. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pps.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 378a525eec16..173bcae5f0e2 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -1560,13 +1560,11 @@ static void pps_init_delays(struct intel_dp *intel_dp) assign_final(power_cycle); #undef assign_final -#define get_delay(field) pps_units_to_msecs(final->field) - intel_dp->pps.panel_power_up_delay = get_delay(power_up); - intel_dp->pps.backlight_on_delay = get_delay(backlight_on); - intel_dp->pps.backlight_off_delay = get_delay(backlight_off); - intel_dp->pps.panel_power_down_delay = get_delay(power_down); - intel_dp->pps.panel_power_cycle_delay = get_delay(power_cycle); -#undef get_delay + intel_dp->pps.panel_power_up_delay = pps_units_to_msecs(final->power_up); + intel_dp->pps.backlight_on_delay = pps_units_to_msecs(final->backlight_on); + intel_dp->pps.backlight_off_delay = pps_units_to_msecs(final->backlight_off); + intel_dp->pps.panel_power_down_delay = pps_units_to_msecs(final->power_down); + intel_dp->pps.panel_power_cycle_delay = pps_units_to_msecs(final->power_cycle); drm_dbg_kms(display->drm, "panel power up delay %d, power down delay %d, power cycle delay %d\n",