From patchwork Tue Mar 12 18:13:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10849775 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D21AE186E for ; Tue, 12 Mar 2019 18:14:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C0291284C9 for ; Tue, 12 Mar 2019 18:14:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B3CE12869A; Tue, 12 Mar 2019 18:14:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 889A128681 for ; Tue, 12 Mar 2019 18:14:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727327AbfCLSOT (ORCPT ); Tue, 12 Mar 2019 14:14:19 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:58296 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727531AbfCLSOR (ORCPT ); Tue, 12 Mar 2019 14:14:17 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id BD95F619CF; Tue, 12 Mar 2019 18:14:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1552414455; bh=aNzkhEBdMH/+RdBcUjDsck1i/+rqLAmasAElAo9C2u0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Blx8KfFocf3V/7A5gw807gfysqQHTwtoGbz9dputmh4aN8TWgNT4M4cZ0iBmybH6E iRygIfL7Km4tYZEiBAf1VSxSaW8VTQYDTywITFc6W2E/1xbAj3BvIt5tvxx/dhtaQm dKVKqEVSMW+Pj+yDP/HHLVD2IM74bkJ47Ql9mCn8= Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E1446619AE; Tue, 12 Mar 2019 18:14:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1552414449; bh=aNzkhEBdMH/+RdBcUjDsck1i/+rqLAmasAElAo9C2u0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k+KLN5/2+BUIH2KHS4mIDzgUdvXg0v7ee7k+IYMts+b1lGDKFbohWH6nsCNutdcUP 7h2FQgw191I11skwcjlpskwLdQUrjkTteW19dppOrsQIaY3T4f38j/ilhraBTS4+3j TRokdOoF8arO9ODO7dw1AHLE0gGo3yio+YVZ4tEg= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E1446619AE Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: Bjorn Andersson , Sean Paul , linux-arm-msm@vger.kernel.org, Kees Cook , Sharat Masetty , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Douglas Anderson , Rob Clark , David Airlie , Jonathan Marek , Mamta Shukla , Daniel Vetter Subject: [PATCH v1 1/4] drm/msm/gpu: Move zap shader loading to adreno Date: Tue, 12 Mar 2019 12:13:39 -0600 Message-Id: <1552414422-9568-2-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552414422-9568-1-git-send-email-jcrouse@codeaurora.org> References: <1552414422-9568-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP a5xx and a6xx both share (mostly) the same code to load the zap shader and bring the GPU out of secure mode. Move the formerly 5xx specific code to adreno to make it available for a6xx too. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 109 +----------------------------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 113 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++ 3 files changed, 120 insertions(+), 108 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index d5f5e56..e5fcefa 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -15,9 +15,6 @@ #include #include #include -#include -#include -#include #include #include #include @@ -30,94 +27,6 @@ static void a5xx_dump(struct msm_gpu *gpu); #define GPU_PAS_ID 13 -static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname) -{ - struct device *dev = &gpu->pdev->dev; - const struct firmware *fw; - struct device_node *np; - struct resource r; - phys_addr_t mem_phys; - ssize_t mem_size; - void *mem_region = NULL; - int ret; - - if (!IS_ENABLED(CONFIG_ARCH_QCOM)) - return -EINVAL; - - np = of_get_child_by_name(dev->of_node, "zap-shader"); - if (!np) - return -ENODEV; - - np = of_parse_phandle(np, "memory-region", 0); - if (!np) - return -EINVAL; - - ret = of_address_to_resource(np, 0, &r); - if (ret) - return ret; - - mem_phys = r.start; - mem_size = resource_size(&r); - - /* Request the MDT file for the firmware */ - fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); - if (IS_ERR(fw)) { - DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname); - return PTR_ERR(fw); - } - - /* Figure out how much memory we need */ - mem_size = qcom_mdt_get_size(fw); - if (mem_size < 0) { - ret = mem_size; - goto out; - } - - /* Allocate memory for the firmware image */ - mem_region = memremap(mem_phys, mem_size, MEMREMAP_WC); - if (!mem_region) { - ret = -ENOMEM; - goto out; - } - - /* - * Load the rest of the MDT - * - * Note that we could be dealing with two different paths, since - * with upstream linux-firmware it would be in a qcom/ subdir.. - * adreno_request_fw() handles this, but qcom_mdt_load() does - * not. But since we've already gotten thru adreno_request_fw() - * we know which of the two cases it is: - */ - if (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY) { - ret = qcom_mdt_load(dev, fw, fwname, GPU_PAS_ID, - mem_region, mem_phys, mem_size, NULL); - } else { - char *newname; - - newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); - - ret = qcom_mdt_load(dev, fw, newname, GPU_PAS_ID, - mem_region, mem_phys, mem_size, NULL); - kfree(newname); - } - if (ret) - goto out; - - /* Send the image to the secure world */ - ret = qcom_scm_pas_auth_and_reset(GPU_PAS_ID); - if (ret) - DRM_DEV_ERROR(dev, "Unable to authorize the image\n"); - -out: - if (mem_region) - memunmap(mem_region); - - release_firmware(fw); - - return ret; -} - static void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -563,8 +472,6 @@ static int a5xx_zap_shader_resume(struct msm_gpu *gpu) static int a5xx_zap_shader_init(struct msm_gpu *gpu) { static bool loaded; - struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - struct platform_device *pdev = gpu->pdev; int ret; /* @@ -574,23 +481,9 @@ static int a5xx_zap_shader_init(struct msm_gpu *gpu) if (loaded) return a5xx_zap_shader_resume(gpu); - /* We need SCM to be able to load the firmware */ - if (!qcom_scm_is_available()) { - DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n"); - return -EPROBE_DEFER; - } - - /* Each GPU has a target specific zap shader firmware name to use */ - if (!adreno_gpu->info->zapfw) { - DRM_DEV_ERROR(&pdev->dev, - "Zap shader firmware file not specified for this target\n"); - return -ENODEV; - } - - ret = zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw); + ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); loaded = !ret; - return ret; } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 2789847..a9eb58c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -19,13 +19,126 @@ #include #include +#include #include +#include #include #include +#include #include "adreno_gpu.h" #include "msm_gem.h" #include "msm_mmu.h" +static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, + u32 pasid) +{ + struct device *dev = &gpu->pdev->dev; + const struct firmware *fw; + struct device_node *np; + struct resource r; + phys_addr_t mem_phys; + ssize_t mem_size; + void *mem_region = NULL; + int ret; + + if (!IS_ENABLED(CONFIG_ARCH_QCOM)) + return -EINVAL; + + np = of_get_child_by_name(dev->of_node, "zap-shader"); + if (!np) + return -ENODEV; + + np = of_parse_phandle(np, "memory-region", 0); + if (!np) + return -EINVAL; + + ret = of_address_to_resource(np, 0, &r); + if (ret) + return ret; + + mem_phys = r.start; + mem_size = resource_size(&r); + + /* Request the MDT file for the firmware */ + fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); + if (IS_ERR(fw)) { + DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname); + return PTR_ERR(fw); + } + + /* Figure out how much memory we need */ + mem_size = qcom_mdt_get_size(fw); + if (mem_size < 0) { + ret = mem_size; + goto out; + } + + /* Allocate memory for the firmware image */ + mem_region = memremap(mem_phys, mem_size, MEMREMAP_WC); + if (!mem_region) { + ret = -ENOMEM; + goto out; + } + + /* + * Load the rest of the MDT + * + * Note that we could be dealing with two different paths, since + * with upstream linux-firmware it would be in a qcom/ subdir.. + * adreno_request_fw() handles this, but qcom_mdt_load() does + * not. But since we've already gotten through adreno_request_fw() + * we know which of the two cases it is: + */ + if (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY) { + ret = qcom_mdt_load(dev, fw, fwname, pasid, + mem_region, mem_phys, mem_size, NULL); + } else { + char *newname; + + newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); + + ret = qcom_mdt_load(dev, fw, newname, pasid, + mem_region, mem_phys, mem_size, NULL); + kfree(newname); + } + if (ret) + goto out; + + /* Send the image to the secure world */ + ret = qcom_scm_pas_auth_and_reset(pasid); + if (ret) + DRM_DEV_ERROR(dev, "Unable to authorize the image\n"); + +out: + if (mem_region) + memunmap(mem_region); + + release_firmware(fw); + + return ret; +} + +int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct platform_device *pdev = gpu->pdev; + + /* We need SCM to be able to load the firmware */ + if (!qcom_scm_is_available()) { + DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n"); + return -EPROBE_DEFER; + } + + /* Each GPU has a target specific zap shader firmware name to use */ + if (!adreno_gpu->info->zapfw) { + DRM_DEV_ERROR(&pdev->dev, + "Zap shader firmware file not specified for this target\n"); + return -ENODEV; + } + + return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); +} + int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 5db459b..0925606e 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -252,6 +252,12 @@ void adreno_gpu_state_destroy(struct msm_gpu_state *state); int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state); int adreno_gpu_state_put(struct msm_gpu_state *state); +/* + * For a5xx and a6xx targets load the zap shader that is used to pull the GPU + * out of secure mode + */ +int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid); + /* ringbuffer helpers (the parts that are adreno specific) */ static inline void From patchwork Tue Mar 12 18:13:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10849783 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8BD116C2 for ; Tue, 12 Mar 2019 18:14:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 78D4128D01 for ; Tue, 12 Mar 2019 18:14:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6D2AE296B7; Tue, 12 Mar 2019 18:14:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E88EE28D01 for ; Tue, 12 Mar 2019 18:14:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727148AbfCLSOf (ORCPT ); Tue, 12 Mar 2019 14:14:35 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:58244 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727522AbfCLSOQ (ORCPT ); Tue, 12 Mar 2019 14:14:16 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E52C761AA2; Tue, 12 Mar 2019 18:14:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1552414455; bh=XavfODKbiYd3VUlO1pljeUXeZYLnBdMdaR2DWcS0Jjs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M3ehYlM3ux2SwmB7hkQOS42TY8kjmVX4Ap6TEqsMh6Rhxq1pXpd3pzLrJeP1tIZCi A42TddoRBmadbVQRKhSf2sbKo049PQWKA5T41ffg+aSNqijIQk7TdC3b+DcgRsAhuz F5qFXCgHBPngnK1FPqqX5oZYvJ6+MLcwQixoSaw4= Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id CCF87619D0; Tue, 12 Mar 2019 18:14:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1552414451; bh=XavfODKbiYd3VUlO1pljeUXeZYLnBdMdaR2DWcS0Jjs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NHINJMBrQ0nIJTVSwRpCmKbfxfoKgfYSE2MAJhuC3lVNa2ZAcXEygzmoqtAk6GsgF KgfdQEgjVEvMXyUqdsiQxr+0RYXn0J9kV5ISd80p6z/HfbjiNtFUw/2b9KqJ3XsVkB WE7+3leoW/0oglufdV7Q3Cz1f6j72CswhobHqy0Q= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org CCF87619D0 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: Bjorn Andersson , Arnd Bergmann , Sean Paul , Thomas Zimmermann , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Clark , David Airlie , Jonathan Marek , Daniel Mack , Mamta Shukla , Daniel Vetter Subject: [PATCH v1 2/4] drm/msm/a6xx: Add zap shader load Date: Tue, 12 Mar 2019 12:13:40 -0600 Message-Id: <1552414422-9568-3-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552414422-9568-1-git-send-email-jcrouse@codeaurora.org> References: <1552414422-9568-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The a6xx GPU powers on in secure mode which restricts what memory it can write to. To get out of secure mode the GPU driver can write to REG_A6XX_RBBM_SECVID_TRUST_CNTL but on targets that are "secure" that register region is blocked and writes will cause the system to go down. For those targets we need to execute a special sequence that involves loadinga special shader that clears the GPU registers and use a PM4 sequence to pull the GPU out of secure. Add support for loading the zap shader and executing the secure sequence. For targets that do not support SCM or the specific SCM sequence this should fail and we would fall back to writing the register. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 +++++++++++++++++++++++++++++- drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index fefe773..5983e47 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -10,6 +10,8 @@ #include +#define GPU_PAS_ID 13 + static inline bool _a6xx_check_idle(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -343,6 +345,20 @@ static int a6xx_ucode_init(struct msm_gpu *gpu) return 0; } +static int a6xx_zap_shader_init(struct msm_gpu *gpu) +{ + static bool loaded; + int ret; + + if (loaded) + return 0; + + ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); + + loaded = !ret; + return ret; +} + #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ @@ -491,7 +507,27 @@ static int a6xx_hw_init(struct msm_gpu *gpu) if (ret) goto out; - gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); + /* + * Try to load a zap shader into the secure world. If successful + * we can use the CP to switch out of secure mode. If not then we + * have no resource but to try to switch ourselves out manually. If we + * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will + * be blocked and a permissions violation will soon follow. + */ + ret = a6xx_zap_shader_init(gpu); + if (!ret) { + OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); + OUT_RING(gpu->rb[0], 0x00000000); + + a6xx_flush(gpu, gpu->rb[0]); + if (!a6xx_idle(gpu, gpu->rb[0])) + return -EINVAL; + } else { + /* Print a warning so if we die, we know why */ + dev_warn_once(gpu->dev->dev, + "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); + gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); + } out: /* diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 714ed65..ead5f6a 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -155,6 +155,7 @@ static const struct adreno_info gpulist[] = { .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a6xx_gpu_init, + .zapfw = "a630_zap.mdt", }, }; From patchwork Tue Mar 12 18:13:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10849781 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E2B241850 for ; Tue, 12 Mar 2019 18:14:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D23FB28D01 for ; Tue, 12 Mar 2019 18:14:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C65AA296B7; Tue, 12 Mar 2019 18:14:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7288A28D01 for ; Tue, 12 Mar 2019 18:14:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726974AbfCLSOe (ORCPT ); Tue, 12 Mar 2019 14:14:34 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:58586 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727524AbfCLSOT (ORCPT ); Tue, 12 Mar 2019 14:14:19 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 1A8CD61F48; Tue, 12 Mar 2019 18:14:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1552414459; bh=TItnokO3ptuUROJyjnRI1pbipmM6zmQ9NJP7PbJyjek=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eWuUHuxkrjuxdvr198s0t4+cD34AtoW/OTnmcvEi4MLp7OIIxMYpljwe/eSF2K9Jd hiu68X8h8FQ2y+B2fD9SWS0saDojjV45wWfdXpQ4VcK6N71ToJTxiTcyFha06JwJay URp1t8cui3kNUU3foGHcxbaId5Z2OWwHONWAhDHk= Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B52A661A9A; Tue, 12 Mar 2019 18:14:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1552414453; bh=TItnokO3ptuUROJyjnRI1pbipmM6zmQ9NJP7PbJyjek=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AAuNZPUl4HGrkDvywbmZLIrmwCgAT99CXt3UyjnfgXtvoVfmhmjkGscVYyPIrPhZC srvYSOYGl2hR0fCCrd8clCm6z9LqzCRjNk6AQ5oiK6GrsRI44fX61Ty1P5OJa0zb0m hqUJhmF8vhdhfShO+D6h12UoEYmYsryogyzWnMZQ= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B52A661A9A Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: Bjorn Andersson , Sean Paul , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Herring , Rob Clark , David Airlie , Mark Rutland , Daniel Vetter Subject: [PATCH v1 3/4] dt-bindings: drm/msm/gpu: Document a5xx / a6xx zap shader region Date: Tue, 12 Mar 2019 12:13:41 -0600 Message-Id: <1552414422-9568-4-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552414422-9568-1-git-send-email-jcrouse@codeaurora.org> References: <1552414422-9568-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Describe the zap-shader node that defines a reserved memory region to store the zap shader. Signed-off-by: Jordan Crouse --- Documentation/devicetree/bindings/display/msm/gpu.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index aad1aef..1e6d870 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -25,6 +25,9 @@ Required properties: - qcom,gmu: For GMU attached devices a phandle to the GMU device that will control the power for the GPU. Applicable targets: - qcom,adreno-630.2 +- zap-shader: For a5xx and a6xx devices this node contains a memory-region that + points to reserved memory to store the zap shader that can be used to help + bring the GPU out of secure mode. Example 3xx/4xx/a5xx: @@ -71,5 +74,9 @@ Example a6xx (with GMU): operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + + zap-shader { + memory-region = <&zap_shader_region>; + }; }; }; From patchwork Tue Mar 12 18:13:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10849779 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ABAEB6C2 for ; Tue, 12 Mar 2019 18:14:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 953F728D01 for ; Tue, 12 Mar 2019 18:14:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 86820296B7; Tue, 12 Mar 2019 18:14:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C87328D01 for ; Tue, 12 Mar 2019 18:14:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726994AbfCLSOY (ORCPT ); Tue, 12 Mar 2019 14:14:24 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:58650 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727264AbfCLSOU (ORCPT ); Tue, 12 Mar 2019 14:14:20 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E369E61CC5; Tue, 12 Mar 2019 18:14:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1552414459; bh=gvKE9Gn+LhYE/7yYVNegmkYny91RgmV05gJf1qgucNE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=H5wjMcJy5L1y83PIgcewZsYueakIHdX59s4NT1wfcvfuTb/TciBlp3UbQIoafzW+e Dl92YBM7bFbfAsYxY8UIDry+HnNGW0gkMGIjz0BIpe1Tu7m0+IxKjYj0G3EKc7yN5h D+kIraIe68YSeBAipJem57SkQON7+RrcIArcbZ7c= Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 7FD25619CF; Tue, 12 Mar 2019 18:14:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1552414454; bh=gvKE9Gn+LhYE/7yYVNegmkYny91RgmV05gJf1qgucNE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mHJxj16DmYG2hRI9zUupVB+e8ZIfVTNGAcc7Jl4MHlCEUvD4gl2mhfA0VaBXe056W 7ou3JlkR0suuR4m9yS3IQXehhS+pDj5y8OUNgfdH3j+vtTZrL6qX8kKDECvXRCS4A5 w8T44+KCih6Q/MfexT85ag88KhWIkJyFR/adS69M= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7FD25619CF Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Cc: Bjorn Andersson , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , Rob Herring , David Brown , Mark Rutland Subject: [PATCH v1 4/4] arm64: dts: sdm845: Add zap shader region for GPU Date: Tue, 12 Mar 2019 12:13:42 -0600 Message-Id: <1552414422-9568-5-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552414422-9568-1-git-send-email-jcrouse@codeaurora.org> References: <1552414422-9568-1-git-send-email-jcrouse@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some Adreno GPU targets require a special zap shader to bring the GPU out of secure mode. Define a region to allocate and store the zap shader. Signed-off-by: Jordan Crouse --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index fed7a29..526456d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -100,6 +100,11 @@ no-map; }; + zap_shader_region: memory@8c415000 { + reg = <0 0x8c415000 0 0x2000>; + no-map; + }; + mpss_region: memory@8e000000 { reg = <0 0x8e000000 0 0x7800000>; no-map; @@ -109,6 +114,8 @@ reg = <0 0x96500000 0 0x200000>; no-map; }; + + }; cpus { @@ -1514,6 +1521,10 @@ qcom,gmu = <&gmu>; + zap-shader { + memory-region = <&zap_shader_region>; + }; + gpu_opp_table: opp-table { compatible = "operating-points-v2";