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Fri, 8 Nov 2024 21:48:55 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv1 1/7] genirq/msi: Allow preset IOVA in struct msi_desc for MSI doorbell address Date: Fri, 8 Nov 2024 21:48:46 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A102:EE_|BL3PR12MB6475:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f5d5392-9d74-41d5-4c0a-08dd008235ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: t/S9K0XP4NZ0tg1+bxB+qfMa9SC0pV7WHw1QHoPygbgdTHgg3p7RzN5Pa6M1YqXoRwFRlyAYZ85gPdxplb1oQmzoeydmoPbInJWXEPUOYgKiG7KEC8C6OjUmdGEgrD5MT77Rsslxks782kTRGitx1vv0JxjNDYu4lytP9guzv6yC1g9LUIPR0shtj9d3HmUGKKaOJhinu3AKwZn48J++zDxjh6+L58Sgl1JWtvV4QBy9m3bMRUZYhnqawjUyiIMXNJk15gMyl43wVBgWNyuJhCz+tTmqpyqo/idCGQSBJwSWwFKAvXFDjL+P33YSBxXDYBKpbg+lWdfxF6MHFCOSvznpM1GkMz+neEq2fnlOMep+0wUqELkWY5P9OsvFCSemDzm2Ujx7J6GSNOrbJJTsAtNhA/xHxtHxPmNksa0NLUhyBbAHppRf5Qjmqg7m/D1wAHfZ7uUvSwqKQuAxC0E4JQi9q+evY9unS7otiEDiAm7VKeFXAAd2mzeyNeUh0zmxFQplTpWXQMc2fGdkAYagkd7D3j7BdnyqhoTX6SJodapG998cI9PVzhEsyAHp0zxoW4Jk3X0aBM5LeJKWPRguHniMnw8wySpWSd0hBH0LD1eUVLn4onJhok5w6boAvH4GTwN8BZ5qe9ueypTD8RDz/a9jIms44gw0nQNKAXYtjhs5fzbRTo5ySer4+M74F/WCWkBaZsQQEB0UV9xNixH+BLt9cB1UqxklH2VLWIZiB6htP0RCDLex02zilyJv6kuFw3LnXEPMCuxf2HFudNbEM04g/+XgHD4wKCmHl3kkjkS2HcKLfkME60EiVaKQzQKxZNkVzahd19R5DSOSe9L2x7sfAPR6wNNU8ZAYGiPxY7e4NjvM8i4Lezp+yA05Yg0fbpNoF0CS2AWmk+czNM4ywOBa2RsR0alV26f+dMU7XsnFrArwajyjC7n5vdbds4w/e7OJp45TOjLbFI6axyqRAn0GVS1IEeY82hsxX28PuF2eM+xeV82TI2Ytm8EtgBEhh9ePMzsYcp1Wh2WpA8X38AQqoSX9MBg2SXMcVEZ30l9t2daTP8hSVX0YVVV19XZMrHwgunky/Y5KB8Ptbj0Qnzukieh1iNc/fT9oS7zQY483Q/to69Tz4rkHNzQvhSJ76RKeixaxgloPzMBWCg0E7vR6AmWjNMQMBQg0KILfVqCaRWT2YlWT2S1XuXZm50rfD2Dm53bCXm2VSQtNlrQm6q07fmsslwyT4Ot3iJPv5H0tws+47sAVcMfFbaLEU2+zN8EA8Njy39xyR+TuwHOG/M8O5ynxgjU2cjNIgkaVIyDVnNlN2cSiPXVBFA2AwydoMJkzrY0wcGIO7tpyDtzNzaATWz4/CQqjNS8a7Bcchh+EBsY4mHC2ewxWjjDT15rYmvoeqHdtic0lVSBGZS9pzA== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:00.4743 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f5d5392-9d74-41d5-4c0a-08dd008235ea X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6475 Currently, the IOVA and its mapping (to physical doorbell address) is done by the dma-iommu via the iommu_cookie in the struct msi_desc, which is the structure used by three parties: genirq, irqchip and dma-iommu. However, when dealing with a nested translation on ARM64, the MSI doorbell address is behind the SMMU (IOMMU on ARM64), thus HW needs to be programed with the stage-1 IOVA, i.e. guest-level IOVA, rather than asking dma-iommu to allocate one. To support a guest-programmable pathway, first we need to make sure struct msi_desc will allow a preset IOVA v.s. using iommu_cookie. Add an msi_iova to the structure and init its value to PHYS_ADDR_MAX. And provide a helper for drivers to get the msi_iova out of an msi_desc object. A following patch will change msi_setup_msi_descs and msix_setup_msi_descs to call msi_domain_insert_msi_desc and finish the actual value forwarding. Signed-off-by: Nicolin Chen --- include/linux/msi.h | 11 +++++++++++ kernel/irq/msi.c | 6 ++++++ 2 files changed, 17 insertions(+) diff --git a/include/linux/msi.h b/include/linux/msi.h index b10093c4d00e..873094743065 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -185,6 +185,7 @@ struct msi_desc { struct irq_affinity_desc *affinity; #ifdef CONFIG_IRQ_MSI_IOMMU const void *iommu_cookie; + dma_addr_t msi_iova; #endif #ifdef CONFIG_SYSFS struct device_attribute *sysfs_attrs; @@ -296,6 +297,11 @@ static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc, { desc->iommu_cookie = iommu_cookie; } + +static inline dma_addr_t msi_desc_get_iova(struct msi_desc *desc) +{ + return desc->msi_iova; +} #else static inline const void *msi_desc_get_iommu_cookie(struct msi_desc *desc) { @@ -306,6 +312,11 @@ static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc, const void *iommu_cookie) { } + +static inline dma_addr_t msi_desc_get_iova(struct msi_desc *desc) +{ + return PHYS_ADDR_MAX; +} #endif int msi_domain_insert_msi_desc(struct device *dev, unsigned int domid, diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c index 3a24d6b5f559..f3159ec0f036 100644 --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -81,6 +81,9 @@ static struct msi_desc *msi_alloc_desc(struct device *dev, int nvec, desc->dev = dev; desc->nvec_used = nvec; +#ifdef CONFIG_IRQ_MSI_IOMMU + desc->msi_iova = PHYS_ADDR_MAX; +#endif if (affinity) { desc->affinity = kmemdup_array(affinity, nvec, sizeof(*desc->affinity), GFP_KERNEL); if (!desc->affinity) { @@ -158,6 +161,9 @@ int msi_domain_insert_msi_desc(struct device *dev, unsigned int domid, /* Copy type specific data to the new descriptor. */ desc->pci = init_desc->pci; +#ifdef CONFIG_IRQ_MSI_IOMMU + desc->msi_iova = init_desc->msi_iova; +#endif return msi_insert_desc(dev, desc, domid, init_desc->msi_index); } From patchwork Sat Nov 9 05:48:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13869261 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2069.outbound.protection.outlook.com [40.107.92.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 795CC145B03; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:04.6618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 06986a8a-70ad-459e-1c8e-08dd00823862 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7936 Now struct msi_desc can carry a preset IOVA for MSI doorbell address. This is typically preset by user space when engaging a 2-stage translation. So, use the preset IOVA instead of kernel-level IOVA allocations in dma-iommu. Signed-off-by: Nicolin Chen --- drivers/irqchip/irq-gic-v3-its.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index ab597e74ba08..bc1768576546 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1723,6 +1723,8 @@ static u64 its_irq_get_msi_base(struct its_device *its_dev) static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) { struct its_device *its_dev = irq_data_get_irq_chip_data(d); + struct msi_desc *desc = irq_data_get_msi_desc(d); + dma_addr_t iova = msi_desc_get_iova(desc); struct its_node *its; u64 addr; @@ -1733,7 +1735,13 @@ static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) msg->address_hi = upper_32_bits(addr); msg->data = its_get_event_id(d); - iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg); + /* Bypass iommu_dma_compose_msi_msg if msi_iova is preset */ + if (iova == PHYS_ADDR_MAX) { + iommu_dma_compose_msi_msg(desc, msg); + } else { + msg->address_lo = lower_32_bits(iova); + msg->address_hi = upper_32_bits(iova); + } } static int its_irq_set_irqchip_state(struct irq_data *d, @@ -3570,6 +3578,7 @@ static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, { msi_alloc_info_t *info = args; struct its_device *its_dev = info->scratchpad[0].ptr; + dma_addr_t iova = msi_desc_get_iova(info->desc); struct its_node *its = its_dev->its; struct irq_data *irqd; irq_hw_number_t hwirq; @@ -3580,9 +3589,13 @@ static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, if (err) return err; - err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev)); - if (err) - return err; + /* Bypass iommu_dma_prepare_msi if msi_iova is preset */ + if (iova == PHYS_ADDR_MAX) { + err = iommu_dma_prepare_msi(info->desc, + its->get_msi_base(its_dev)); + if (err) + return err; + } for (i = 0; i < nr_irqs; i++) { err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i); From patchwork Sat Nov 9 05:48:48 2024 Content-Type: text/plain; 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Fri, 8 Nov 2024 21:48:58 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv1 3/7] PCI/MSI: Pass in msi_iova to msi_domain_insert_msi_desc Date: Fri, 8 Nov 2024 21:48:48 -0800 Message-ID: <32fe78c5ec4a08bf0414d80ce9ed9121270b9cb0.1731130093.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE9:EE_|MN2PR12MB4390:EE_ X-MS-Office365-Filtering-Correlation-Id: 11d964e9-49a7-44e8-c6a8-08dd008235bf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: Iwzk/sRcq3Sfumzqc/pu1OcERoHst/OzZ6ikpkHYwAg0+UivW3AbAHlAeXAyeuztMLKZVZG7C/Zw0fwIG3VPTVji3aOh+XTm97mKN/X6H7A5L6rpMQwBSBx86nvY9+M3OL7wwGCglkdr61xvG9POWqvycIknGPBz7UPMM2K7wqZoBcG9a8rU4tNieO7egF7FqRXQEHObU/rTTYxrWj9FZeqmW/liFDXxD8n9XYDwrdZ+HP48mIGAvUuZcYWiPPgjo5QP8jkgpzNNJLVM8aPGkrelgqOxClUXoWJAmZqnAdfKKIxFuabxpNlpqHBJgzrvnTlyQjr79M2eR4QR0P3jQztC8UtM8qUrBgAsBVLmGQ99zksmcFBNKTdjeFbSzkxggmFiZrXLukjTQ3V2QepSZESzN6d9YqVp2o6TGuP7THPRlaPA0aZBUHVLkOR/evsDfI5CJI8HAijE5w7zy6xQ0LTApwSutvpSgkjoyL014TgWZAFiL5XPIufOrsku4dJUUYw6oiLX2zm8doPAEZYQ9OLQLBgNx57j49krFKpTJ5TB/n3tEJC3m75YricxbRn9clYmH0ZgS0YnmyQEegFArdMihl0nP+H3BtZfOQouCO6rFQqOy2ywJDj+9F8twXq553CzraveNFTD3Z4MhFOSuwVV8vThi13/7zABwpc4CSNf5lug/TwAFkdeA6mXCPdQMS1hbdInFup/EuM/0Q9eLuC9uinGi5P6cqwB7RQ/gnv+tsNtZX8UrGtMv2csvYBCF3m1fRHzxf25Xg58jUnIwLqv6ZD5C9KSVf5VydsWfDqZoGL35EF8GyFptPAEzSaUjm9Jg6eb/JKAfAS2t1MCnBMxYGkXby82oZPb8dvt3Evd5uRBorJShui+ul5+RjzjW5WVlhLCHRcnBDJjDmCTYyNOfGV4oIRcHGEOmjJAlL1jHO9Av3RcI0rCvrZnvoyWgwDFMQioO+qL5LYXw3uxUgs/Mpsq5fstntra4N5853eY3jYSRRPiNp7wzW7x/S879AlLs8bqdnjpzWX003so5mTiTvTkv1aEg74I/hO3HaEACw/6Oy7kruZ63o+Tkj2IcvFJBFB4fVkRZCZKH+YKJuJjaIfrXc8m/7RJuZLJVX1SqQFW5qcIYE9XE6VdmXJQC6Mn9qrGQwcGSQsXnnUwV7jfqex3HFnnvgcwJJGfKg1v29svKzTSIvc9K0VaAWGBnkWv7EwjkHzpPyLDF06cM54A1ydolfN9LbY+a68rm+uj7Xd1mP3mxgK9apVWS9Ty7qLa0GfcSREPEp7/h38Q0krUmDkbw/n1yLCgeLe4L+1Mx+BChu+TJa3YmmG2nSSPCYYwWi1sdAdHg9k3ZxGG5/Wip+5hRKK3D4WU7Ex21NqCU2LOn4UB/0jQv3PLRSryLOFmjPOfwWZniDNC8vgAQA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:00.3675 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 11d964e9-49a7-44e8-c6a8-08dd008235bf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4390 msi_setup_msi_descs and msix_setup_msi_descs are the two callers of genirq helper msi_domain_insert_msi_desc that is now ready for a preset msi_iova. So, do the same in these two callers. Note MSIx supports multiple entries, so use struct msix_entry to pass msi_iova in. Signed-off-by: Nicolin Chen --- include/linux/pci.h | 1 + drivers/pci/msi/msi.c | 18 ++++++++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/include/linux/pci.h b/include/linux/pci.h index 573b4c4c2be6..68ebb9d42f7f 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1652,6 +1652,7 @@ int pci_set_vga_state(struct pci_dev *pdev, bool decode, struct msix_entry { u32 vector; /* Kernel uses to write allocated vector */ u16 entry; /* Driver uses to specify entry, OS writes */ + u64 iova; /* Kernel uses to override doorbell address */ }; #ifdef CONFIG_PCI_MSI diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index 3a45879d85db..95caa81d3421 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -282,7 +282,7 @@ static void pci_msi_set_enable(struct pci_dev *dev, int enable) pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); } -static int msi_setup_msi_desc(struct pci_dev *dev, int nvec, +static int msi_setup_msi_desc(struct pci_dev *dev, int nvec, dma_addr_t iova, struct irq_affinity_desc *masks) { struct msi_desc desc; @@ -312,6 +312,10 @@ static int msi_setup_msi_desc(struct pci_dev *dev, int nvec, else desc.pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_32; +#ifdef CONFIG_IRQ_MSI_IOMMU + desc.msi_iova = iova; +#endif + /* Save the initial mask status */ if (desc.pci.msi_attrib.can_mask) pci_read_config_dword(dev, desc.pci.mask_pos, &desc.pci.msi_mask); @@ -349,7 +353,7 @@ static int msi_verify_entries(struct pci_dev *dev) * which could have been allocated. */ static int msi_capability_init(struct pci_dev *dev, int nvec, - struct irq_affinity *affd) + struct irq_affinity *affd, dma_addr_t iova) { struct irq_affinity_desc *masks = NULL; struct msi_desc *entry, desc; @@ -370,7 +374,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec, masks = irq_create_affinity_masks(nvec, affd); msi_lock_descs(&dev->dev); - ret = msi_setup_msi_desc(dev, nvec, masks); + ret = msi_setup_msi_desc(dev, nvec, iova, masks); if (ret) goto fail; @@ -456,7 +460,7 @@ int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, return -ENOSPC; } - rc = msi_capability_init(dev, nvec, affd); + rc = msi_capability_init(dev, nvec, affd, PHYS_ADDR_MAX); if (rc == 0) return nvec; @@ -625,6 +629,12 @@ static int msix_setup_msi_descs(struct pci_dev *dev, struct msix_entry *entries, memset(&desc, 0, sizeof(desc)); for (i = 0, curmsk = masks; i < nvec; i++, curmsk++) { +#ifdef CONFIG_IRQ_MSI_IOMMU + if (entries && entries[i].iova) + desc.msi_iova = (dma_addr_t)entries[i].iova; + else + desc.msi_iova = PHYS_ADDR_MAX; +#endif desc.msi_index = entries ? entries[i].entry : i; desc.affinity = masks ? curmsk : NULL; desc.pci.msi_attrib.is_virtual = desc.msi_index >= vec_count; From patchwork Sat Nov 9 05:48:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13869263 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2057.outbound.protection.outlook.com [40.107.92.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 987FD14BF8F; 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Signed-off-by: Nicolin Chen --- drivers/pci/msi/msi.h | 3 ++- drivers/pci/msi/api.c | 6 ++++-- drivers/pci/msi/msi.c | 4 ++-- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/pci/msi/msi.h b/drivers/pci/msi/msi.h index ee53cf079f4e..8009d69bf9a5 100644 --- a/drivers/pci/msi/msi.h +++ b/drivers/pci/msi/msi.h @@ -93,7 +93,8 @@ extern int pci_msi_enable; void pci_msi_shutdown(struct pci_dev *dev); void pci_msix_shutdown(struct pci_dev *dev); void pci_free_msi_irqs(struct pci_dev *dev); -int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, struct irq_affinity *affd); +int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, + struct irq_affinity *affd, dma_addr_t iova); int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, int minvec, int maxvec, struct irq_affinity *affd, int flags); void __pci_restore_msi_state(struct pci_dev *dev); diff --git a/drivers/pci/msi/api.c b/drivers/pci/msi/api.c index b956ce591f96..99ade7f69cd4 100644 --- a/drivers/pci/msi/api.c +++ b/drivers/pci/msi/api.c @@ -29,7 +29,8 @@ */ int pci_enable_msi(struct pci_dev *dev) { - int rc = __pci_enable_msi_range(dev, 1, 1, NULL); + int rc = __pci_enable_msi_range(dev, 1, 1, NULL, + PHYS_ADDR_MAX); if (rc < 0) return rc; return 0; @@ -274,7 +275,8 @@ int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, } if (flags & PCI_IRQ_MSI) { - nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd); + nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, + affd, PHYS_ADDR_MAX); if (nvecs > 0) return nvecs; } diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index 95caa81d3421..25da0435c674 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -417,7 +417,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec, } int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, - struct irq_affinity *affd) + struct irq_affinity *affd, dma_addr_t iova) { int nvec; int rc; @@ -460,7 +460,7 @@ int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, return -ENOSPC; } - rc = msi_capability_init(dev, nvec, affd, PHYS_ADDR_MAX); + rc = msi_capability_init(dev, nvec, affd, iova); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:12.6663 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a84e2032-2e31-45be-a94f-08dd00823d2e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A104.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8103 Extract a common function from the existing callers, to prepare for a new helper that provides an array of msi_iovas. Also, extract the msi_iova(s) from the array and pass in properly down to __pci_enable_msi/msix_range(). Signed-off-by: Nicolin Chen --- drivers/pci/msi/api.c | 113 ++++++++++++++++++++++++++---------------- 1 file changed, 70 insertions(+), 43 deletions(-) diff --git a/drivers/pci/msi/api.c b/drivers/pci/msi/api.c index 99ade7f69cd4..dff3d7350b38 100644 --- a/drivers/pci/msi/api.c +++ b/drivers/pci/msi/api.c @@ -204,6 +204,72 @@ void pci_disable_msix(struct pci_dev *dev) } EXPORT_SYMBOL(pci_disable_msix); +static int __pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags, + struct irq_affinity *affd, + dma_addr_t *msi_iovas) +{ + struct irq_affinity msi_default_affd = {0}; + int nvecs = -ENOSPC; + + if (flags & PCI_IRQ_AFFINITY) { + if (!affd) + affd = &msi_default_affd; + } else { + if (WARN_ON(affd)) + affd = NULL; + } + + if (flags & PCI_IRQ_MSIX) { + struct msix_entry *entries = NULL; + + if (msi_iovas) { + int count = max_vecs - min_vecs + 1; + int i; + + entries = kcalloc(max_vecs - min_vecs + 1, + sizeof(*entries), GFP_KERNEL); + if (!entries) + return -ENOMEM; + for (i = 0; i < count; i++) { + entries[i].entry = i; + entries[i].iova = msi_iovas[i]; + } + } + + nvecs = __pci_enable_msix_range(dev, entries, min_vecs, + max_vecs, affd, flags); + kfree(entries); + if (nvecs > 0) + return nvecs; + } + + if (flags & PCI_IRQ_MSI) { + nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd, + msi_iovas ? *msi_iovas : + PHYS_ADDR_MAX); + if (nvecs > 0) + return nvecs; + } + + /* use INTx IRQ if allowed */ + if (flags & PCI_IRQ_INTX) { + if (min_vecs == 1 && dev->irq) { + /* + * Invoke the affinity spreading logic to ensure that + * the device driver can adjust queue configuration + * for the single interrupt case. + */ + if (affd) + irq_create_affinity_masks(1, affd); + pci_intx(dev, 1); + return 1; + } + } + + return nvecs; +} + /** * pci_alloc_irq_vectors() - Allocate multiple device interrupt vectors * @dev: the PCI device to operate on @@ -235,8 +301,8 @@ EXPORT_SYMBOL(pci_disable_msix); int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, unsigned int max_vecs, unsigned int flags) { - return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, - flags, NULL); + return __pci_alloc_irq_vectors(dev, min_vecs, max_vecs, + flags, NULL, NULL); } EXPORT_SYMBOL(pci_alloc_irq_vectors); @@ -256,47 +322,8 @@ int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, unsigned int max_vecs, unsigned int flags, struct irq_affinity *affd) { - struct irq_affinity msi_default_affd = {0}; - int nvecs = -ENOSPC; - - if (flags & PCI_IRQ_AFFINITY) { - if (!affd) - affd = &msi_default_affd; - } else { - if (WARN_ON(affd)) - affd = NULL; - } - - if (flags & PCI_IRQ_MSIX) { - nvecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs, - affd, flags); - if (nvecs > 0) - return nvecs; - } - - if (flags & PCI_IRQ_MSI) { - nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, - affd, PHYS_ADDR_MAX); - if (nvecs > 0) - return nvecs; - } - - /* use INTx IRQ if allowed */ - if (flags & PCI_IRQ_INTX) { - if (min_vecs == 1 && dev->irq) { - /* - * Invoke the affinity spreading logic to ensure that - * the device driver can adjust queue configuration - * for the single interrupt case. - */ - if (affd) - irq_create_affinity_masks(1, affd); - pci_intx(dev, 1); - return 1; - } - } - - return nvecs; + return __pci_alloc_irq_vectors(dev, min_vecs, max_vecs, + flags, affd, NULL); } EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity); From patchwork Sat Nov 9 05:48:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13869262 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2055.outbound.protection.outlook.com [40.107.237.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52BBE146017; Sat, 9 Nov 2024 05:49:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.55 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131354; cv=fail; b=GOx3GhLYNNDDeuD1MEl49BYM8648/DZYb1uLwqWZ7iOOQOB2HTEplaEElZxWti29Ziy/ieffCwXOQcG9cO41vzFofv/iTipRcltR4q8FBXu284GzmGIaTafpjmpjwK1afhQOgNhbJI/gFpSA/aeJV/ngkWE/bID7K3pXA8madKY= ARC-Message-Signature: i=2; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:05.5258 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81d2d01d-8d46-48b0-deda-08dd008238d2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9413 Now, the common __pci_alloc_irq_vectors() accepts an array of msi_iovas, which is a list of preset IOVAs for MSI doorbell addresses. Add a helper that would pass in a list. A following patch will call this to forward msi_iovas from user space. Signed-off-by: Nicolin Chen --- include/linux/pci.h | 17 +++++++++++++++++ drivers/pci/msi/api.c | 21 +++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index 68ebb9d42f7f..6423bee3b207 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1678,6 +1678,9 @@ int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, unsigned int max_vecs, unsigned int flags, struct irq_affinity *affd); +int pci_alloc_irq_vectors_iovas(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags, + dma_addr_t *msi_iovas); bool pci_msix_can_alloc_dyn(struct pci_dev *dev); struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, @@ -1714,6 +1717,13 @@ pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, return -ENOSPC; } static inline int +pci_alloc_irq_vectors_iovas(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags, + dma_addr_t *msi_iovas) + + return -ENOSPC; /* No support if !CONFIG_PCI_MSI */ +} +static inline int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, unsigned int max_vecs, unsigned int flags) { @@ -2068,6 +2078,13 @@ pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, return -ENOSPC; } static inline int +pci_alloc_irq_vectors_iovas(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags, + dma_addr_t *msi_iovas) +{ + return -ENOSPC; +} +static inline int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, unsigned int max_vecs, unsigned int flags) { diff --git a/drivers/pci/msi/api.c b/drivers/pci/msi/api.c index dff3d7350b38..4e90ef8f571c 100644 --- a/drivers/pci/msi/api.c +++ b/drivers/pci/msi/api.c @@ -327,6 +327,27 @@ int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, } EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity); +/** + * pci_alloc_irq_vectors_iovas() - Allocate multiple device interrupt + * vectors with preset msi_iovas + * @dev: the PCI device to operate on + * @min_vecs: minimum required number of vectors (must be >= 1) + * @max_vecs: maximum desired number of vectors + * @flags: allocation flags, as in pci_alloc_irq_vectors() + * @msi_iovas: list of IOVAs for MSI between [min_vecs, max_vecs] + * + * Same as pci_alloc_irq_vectors(), but with the extra @msi_iovas parameter. + * Check that function docs, and &struct irq_affinity, for more details. + */ +int pci_alloc_irq_vectors_iovas(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags, + dma_addr_t *msi_iovas) +{ + return __pci_alloc_irq_vectors(dev, min_vecs, max_vecs, + flags, NULL, msi_iovas); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:15.5882 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 898678ff-363d-4644-f709-08dd00823ee2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A104.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4451 Add a new VFIO_IRQ_SET_ACTION_PREPARE to set VFIO_IRQ_SET_DATA_MSI_IOVA, giving user space an interface to forward to kernel the stage-1 IOVA (of a 2-stage translation: IOVA->IPA->PA) for an MSI doorbell address, since the ITS hardware needs to be programmed with the top level IOVA address, in order to work with the IOMMU on ARM64. Signed-off-by: Nicolin Chen --- include/linux/vfio_pci_core.h | 1 + include/uapi/linux/vfio.h | 8 ++++-- drivers/vfio/pci/vfio_pci_intrs.c | 41 ++++++++++++++++++++++++++++++- drivers/vfio/vfio_main.c | 3 +++ 4 files changed, 50 insertions(+), 3 deletions(-) diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index fbb472dd99b3..08027b8331f0 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -63,6 +63,7 @@ struct vfio_pci_core_device { int irq_type; int num_regions; struct vfio_pci_region *region; + dma_addr_t *msi_iovas; u8 msi_qmax; u8 msix_bar; u16 msix_size; diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 2b68e6cdf190..d6be351abcde 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -590,6 +590,8 @@ struct vfio_irq_set { #define VFIO_IRQ_SET_ACTION_MASK (1 << 3) /* Mask interrupt */ #define VFIO_IRQ_SET_ACTION_UNMASK (1 << 4) /* Unmask interrupt */ #define VFIO_IRQ_SET_ACTION_TRIGGER (1 << 5) /* Trigger interrupt */ +#define VFIO_IRQ_SET_DATA_MSI_IOVA (1 << 6) /* Data is MSI IOVA (u64) */ +#define VFIO_IRQ_SET_ACTION_PREPARE (1 << 7) /* Prepare interrupt */ __u32 index; __u32 start; __u32 count; @@ -599,10 +601,12 @@ struct vfio_irq_set { #define VFIO_IRQ_SET_DATA_TYPE_MASK (VFIO_IRQ_SET_DATA_NONE | \ VFIO_IRQ_SET_DATA_BOOL | \ - VFIO_IRQ_SET_DATA_EVENTFD) + VFIO_IRQ_SET_DATA_EVENTFD | \ + VFIO_IRQ_SET_DATA_MSI_IOVA) #define VFIO_IRQ_SET_ACTION_TYPE_MASK (VFIO_IRQ_SET_ACTION_MASK | \ VFIO_IRQ_SET_ACTION_UNMASK | \ - VFIO_IRQ_SET_ACTION_TRIGGER) + VFIO_IRQ_SET_ACTION_TRIGGER | \ + VFIO_IRQ_SET_ACTION_PREPARE) /** * VFIO_DEVICE_RESET - _IO(VFIO_TYPE, VFIO_BASE + 11) * diff --git a/drivers/vfio/pci/vfio_pci_intrs.c b/drivers/vfio/pci/vfio_pci_intrs.c index 8382c5834335..18bcdc5b1ef5 100644 --- a/drivers/vfio/pci/vfio_pci_intrs.c +++ b/drivers/vfio/pci/vfio_pci_intrs.c @@ -383,7 +383,7 @@ static int vfio_msi_enable(struct vfio_pci_core_device *vdev, int nvec, bool msi /* return the number of supported vectors if we can't get all: */ cmd = vfio_pci_memory_lock_and_enable(vdev); - ret = pci_alloc_irq_vectors(pdev, 1, nvec, flag); + ret = pci_alloc_irq_vectors_iovas(pdev, 1, nvec, flag, vdev->msi_iovas); if (ret < nvec) { if (ret > 0) pci_free_irq_vectors(pdev); @@ -685,6 +685,9 @@ static int vfio_pci_set_msi_trigger(struct vfio_pci_core_device *vdev, if (irq_is(vdev, index) && !count && (flags & VFIO_IRQ_SET_DATA_NONE)) { vfio_msi_disable(vdev, msix); + /* FIXME we need a better cleanup routine */ + kfree(vdev->msi_iovas); + vdev->msi_iovas = NULL; return 0; } @@ -728,6 +731,39 @@ static int vfio_pci_set_msi_trigger(struct vfio_pci_core_device *vdev, return 0; } +static int vfio_pci_set_msi_prepare(struct vfio_pci_core_device *vdev, + unsigned index, unsigned start, + unsigned count, uint32_t flags, void *data) +{ + uint64_t *iovas = data; + unsigned int i; + + if (!(irq_is(vdev, index) || is_irq_none(vdev))) + return -EINVAL; + + if (flags & VFIO_IRQ_SET_DATA_NONE) { + if (!count) + return -EINVAL; + /* FIXME support partial unset */ + kfree(vdev->msi_iovas); + vdev->msi_iovas = NULL; + return 0; + } + + if (!(flags & VFIO_IRQ_SET_DATA_MSI_IOVA)) + return -EOPNOTSUPP; + if (!IS_ENABLED(CONFIG_IRQ_MSI_IOMMU)) + return -EOPNOTSUPP; + if (!vdev->msi_iovas) + vdev->msi_iovas = kcalloc(count, sizeof(dma_addr_t), GFP_KERNEL); + if (!vdev->msi_iovas) + return -ENOMEM; + for (i = 0; i < count; i++) + vdev->msi_iovas[i] = iovas[i]; + + return 0; +} + static int vfio_pci_set_ctx_trigger_single(struct eventfd_ctx **ctx, unsigned int count, uint32_t flags, void *data) @@ -837,6 +873,9 @@ int vfio_pci_set_irqs_ioctl(struct vfio_pci_core_device *vdev, uint32_t flags, case VFIO_IRQ_SET_ACTION_TRIGGER: func = vfio_pci_set_msi_trigger; break; + case VFIO_IRQ_SET_ACTION_PREPARE: + func = vfio_pci_set_msi_prepare; + break; } break; case VFIO_PCI_ERR_IRQ_INDEX: diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c index a5a62d9d963f..61211c082a64 100644 --- a/drivers/vfio/vfio_main.c +++ b/drivers/vfio/vfio_main.c @@ -1554,6 +1554,9 @@ int vfio_set_irqs_validate_and_prepare(struct vfio_irq_set *hdr, int num_irqs, case VFIO_IRQ_SET_DATA_EVENTFD: size = sizeof(int32_t); break; + case VFIO_IRQ_SET_DATA_MSI_IOVA: + size = sizeof(uint64_t); + break; default: return -EINVAL; }