From patchwork Sat Nov 9 05:48:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13869269 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2061.outbound.protection.outlook.com [40.107.92.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D37B1422A2; Sat, 9 Nov 2024 05:49:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.61 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131347; cv=fail; b=grjAtl5E2v5P3gTG5Mo8RDi+x2VsdBpkVIpJZlqP9cKu+7FN3HYj+Fhd/qvYWPdTpVFD8HFhq8Z0x5MRBFKo+NPIZ85qKKyJf2RZZWxM+pkhlU8vLnPM0Y4dGdgKLBVFo18dGftYtBswBi5mKbtvSJp+gm5e3sxUbBLons3r/f4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131347; c=relaxed/simple; bh=5BumytWSkFhG3+elXDqyCD+enOUCf/4J5M0Cis4hV8s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sarq4zAAa6GIw+qwiphWKyNkEkMv1oqwj1jU8sUVnLePG9qpQ/Z8lGj7Pz7iorVop3LottwqTMH9UHiiEFq11GoWtgopaPMi2uSuPAplQzWykZklSJtqKp46ah354ksj7IYnsplZd2UV4Hear+telXloPHaof6fESfk0G5GbcMs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=OSWkJMtx; arc=fail smtp.client-ip=40.107.92.61 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="OSWkJMtx" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=XTupTSBhp99HnwYx/mD6r5Z3dpDYxGldo6jHq75avYgdU8/56hX5QNIBRJUqY560/1sUq3r0M8VhR7GzF9sU1i7rsVeHRdmC0AEU6JCJtQ4qokdo6zYmkxd8obN/Uw5e0XMxyOnwMqe42ASZt/FpflfY0VZntEInjkS7qiZlCazaAHLRgSsu1cJk7OrJbulcAm/yZ4UK1JJUcp4qhv0dqGsWQWYlWWiIGFrQ7YFqyXVBJoPCJicZwgKOksq+j6yDGzzNq7zi/Lj0/rG9KLLpSy6/+VLEAJK1ZEZg64dWffHn6SZM73ReYAE1VOojwej40jqniCYBWWn2iP6lS58ffw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ruRAryFycAyiD/dpV5N9aeYNczxwUmEkz1V3M3BrpVc=; b=CnKw0BK63Vbugn4nLCwK7XXjlulQrjYWYNbjxL6gpufZ6mrZpCGfm8MfbBpQEllUddFyWdQdQl6u/JamMcJ4ztmk39NbAZtvsOgfxs7BQDoU/k8AbAaWbw0lbSm1CFv+19faKuO9n5sUGsVNT26VtawTfW7yL4TLINzmxoyGqCv4BPbWmAGLjsi1tzUz2/6jk6RBJHdLxlHRzLzaTAv9VtRp5lywWJZaUWuWUdMxzb4YxCKR7SerH9pWM3zss7+vGUj+EqVK/PUHssgOLRFxMUU+OH0WlrNXSTEEZxJxJfL8+DIsD58A3Wh6eg2Ff/xi1txrGW86wtewiDl4TPodwA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ruRAryFycAyiD/dpV5N9aeYNczxwUmEkz1V3M3BrpVc=; b=OSWkJMtxk9X6Q3uyxjDS972ylr2ymka91VRSXH0LzTYpCcV3vgDxIDYMLL9RBymlwIxkcG13rZDWPswvrRjkMR5B+FuiKLFlBGvoL2bbM2R/SOs9UC0nTWO3YeKYiSJmXMH+r7mAbwZTIKqXO2OgX2+A/dcG2yKvc0Hlz8g8TWyMG2rM9aKcI9dO62OKP50TRhMRn4A/k5tXbFfLvetDVv5oHOmRQJpHGg0H5d1tviwKDgpjrYEDn3RRshiib3xrBkHEKkUwMg+KARKbnrVu9wOv6pwF8XCxC8LHjVaAiYdIH3MWzeTYCemxDlGE7/qonHfvWsWHIacvDh5tKNox5Q== Received: from MN2PR01CA0044.prod.exchangelabs.com (2603:10b6:208:23f::13) by BL3PR12MB6475.namprd12.prod.outlook.com (2603:10b6:208:3bb::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.22; Sat, 9 Nov 2024 05:49:00 +0000 Received: from BL02EPF0001A102.namprd05.prod.outlook.com (2603:10b6:208:23f:cafe::e0) by MN2PR01CA0044.outlook.office365.com (2603:10b6:208:23f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.21 via Frontend Transport; Sat, 9 Nov 2024 05:49:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BL02EPF0001A102.mail.protection.outlook.com (10.167.241.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Sat, 9 Nov 2024 05:49:00 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 8 Nov 2024 21:48:57 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 8 Nov 2024 21:48:56 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 8 Nov 2024 21:48:55 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv1 1/7] genirq/msi: Allow preset IOVA in struct msi_desc for MSI doorbell address Date: Fri, 8 Nov 2024 21:48:46 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A102:EE_|BL3PR12MB6475:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f5d5392-9d74-41d5-4c0a-08dd008235ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: t/S9K0XP4NZ0tg1+bxB+qfMa9SC0pV7WHw1QHoPygbgdTHgg3p7RzN5Pa6M1YqXoRwFRlyAYZ85gPdxplb1oQmzoeydmoPbInJWXEPUOYgKiG7KEC8C6OjUmdGEgrD5MT77Rsslxks782kTRGitx1vv0JxjNDYu4lytP9guzv6yC1g9LUIPR0shtj9d3HmUGKKaOJhinu3AKwZn48J++zDxjh6+L58Sgl1JWtvV4QBy9m3bMRUZYhnqawjUyiIMXNJk15gMyl43wVBgWNyuJhCz+tTmqpyqo/idCGQSBJwSWwFKAvXFDjL+P33YSBxXDYBKpbg+lWdfxF6MHFCOSvznpM1GkMz+neEq2fnlOMep+0wUqELkWY5P9OsvFCSemDzm2Ujx7J6GSNOrbJJTsAtNhA/xHxtHxPmNksa0NLUhyBbAHppRf5Qjmqg7m/D1wAHfZ7uUvSwqKQuAxC0E4JQi9q+evY9unS7otiEDiAm7VKeFXAAd2mzeyNeUh0zmxFQplTpWXQMc2fGdkAYagkd7D3j7BdnyqhoTX6SJodapG998cI9PVzhEsyAHp0zxoW4Jk3X0aBM5LeJKWPRguHniMnw8wySpWSd0hBH0LD1eUVLn4onJhok5w6boAvH4GTwN8BZ5qe9ueypTD8RDz/a9jIms44gw0nQNKAXYtjhs5fzbRTo5ySer4+M74F/WCWkBaZsQQEB0UV9xNixH+BLt9cB1UqxklH2VLWIZiB6htP0RCDLex02zilyJv6kuFw3LnXEPMCuxf2HFudNbEM04g/+XgHD4wKCmHl3kkjkS2HcKLfkME60EiVaKQzQKxZNkVzahd19R5DSOSe9L2x7sfAPR6wNNU8ZAYGiPxY7e4NjvM8i4Lezp+yA05Yg0fbpNoF0CS2AWmk+czNM4ywOBa2RsR0alV26f+dMU7XsnFrArwajyjC7n5vdbds4w/e7OJp45TOjLbFI6axyqRAn0GVS1IEeY82hsxX28PuF2eM+xeV82TI2Ytm8EtgBEhh9ePMzsYcp1Wh2WpA8X38AQqoSX9MBg2SXMcVEZ30l9t2daTP8hSVX0YVVV19XZMrHwgunky/Y5KB8Ptbj0Qnzukieh1iNc/fT9oS7zQY483Q/to69Tz4rkHNzQvhSJ76RKeixaxgloPzMBWCg0E7vR6AmWjNMQMBQg0KILfVqCaRWT2YlWT2S1XuXZm50rfD2Dm53bCXm2VSQtNlrQm6q07fmsslwyT4Ot3iJPv5H0tws+47sAVcMfFbaLEU2+zN8EA8Njy39xyR+TuwHOG/M8O5ynxgjU2cjNIgkaVIyDVnNlN2cSiPXVBFA2AwydoMJkzrY0wcGIO7tpyDtzNzaATWz4/CQqjNS8a7Bcchh+EBsY4mHC2ewxWjjDT15rYmvoeqHdtic0lVSBGZS9pzA== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:00.4743 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f5d5392-9d74-41d5-4c0a-08dd008235ea X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6475 Currently, the IOVA and its mapping (to physical doorbell address) is done by the dma-iommu via the iommu_cookie in the struct msi_desc, which is the structure used by three parties: genirq, irqchip and dma-iommu. However, when dealing with a nested translation on ARM64, the MSI doorbell address is behind the SMMU (IOMMU on ARM64), thus HW needs to be programed with the stage-1 IOVA, i.e. guest-level IOVA, rather than asking dma-iommu to allocate one. To support a guest-programmable pathway, first we need to make sure struct msi_desc will allow a preset IOVA v.s. using iommu_cookie. Add an msi_iova to the structure and init its value to PHYS_ADDR_MAX. And provide a helper for drivers to get the msi_iova out of an msi_desc object. A following patch will change msi_setup_msi_descs and msix_setup_msi_descs to call msi_domain_insert_msi_desc and finish the actual value forwarding. Signed-off-by: Nicolin Chen --- include/linux/msi.h | 11 +++++++++++ kernel/irq/msi.c | 6 ++++++ 2 files changed, 17 insertions(+) diff --git a/include/linux/msi.h b/include/linux/msi.h index b10093c4d00e..873094743065 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -185,6 +185,7 @@ struct msi_desc { struct irq_affinity_desc *affinity; #ifdef CONFIG_IRQ_MSI_IOMMU const void *iommu_cookie; + dma_addr_t msi_iova; #endif #ifdef CONFIG_SYSFS struct device_attribute *sysfs_attrs; @@ -296,6 +297,11 @@ static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc, { desc->iommu_cookie = iommu_cookie; } + +static inline dma_addr_t msi_desc_get_iova(struct msi_desc *desc) +{ + return desc->msi_iova; +} #else static inline const void *msi_desc_get_iommu_cookie(struct msi_desc *desc) { @@ -306,6 +312,11 @@ static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc, const void *iommu_cookie) { } + +static inline dma_addr_t msi_desc_get_iova(struct msi_desc *desc) +{ + return PHYS_ADDR_MAX; +} #endif int msi_domain_insert_msi_desc(struct device *dev, unsigned int domid, diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c index 3a24d6b5f559..f3159ec0f036 100644 --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -81,6 +81,9 @@ static struct msi_desc *msi_alloc_desc(struct device *dev, int nvec, desc->dev = dev; desc->nvec_used = nvec; +#ifdef CONFIG_IRQ_MSI_IOMMU + desc->msi_iova = PHYS_ADDR_MAX; +#endif if (affinity) { desc->affinity = kmemdup_array(affinity, nvec, sizeof(*desc->affinity), GFP_KERNEL); if (!desc->affinity) { @@ -158,6 +161,9 @@ int msi_domain_insert_msi_desc(struct device *dev, unsigned int domid, /* Copy type specific data to the new descriptor. */ desc->pci = init_desc->pci; +#ifdef CONFIG_IRQ_MSI_IOMMU + desc->msi_iova = init_desc->msi_iova; +#endif return msi_insert_desc(dev, desc, domid, init_desc->msi_index); } From patchwork Sat Nov 9 05:48:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13869271 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2069.outbound.protection.outlook.com [40.107.92.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 795CC145B03; Sat, 9 Nov 2024 05:49:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.69 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131350; cv=fail; b=HVnsw0bioB5CgPWFa7I1tNFmotV9ASySEKvQc1jKh146nu01bGbxifXRTRWive9ML8cZ7unEMkZ0LzF4FhNEF/2GjTHKHh4fJ0lifTSxwHKOv9NwM9fGlvhVvEZbqXTacY9sEO6VoxNvV6BI6gNsWtfEMGFpX6AlOwxuL3kF2zI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131350; c=relaxed/simple; bh=JwzUwfIt4MrboCmOVnxjFEP5Csdi97KdI5la+oLJxU4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=P1LbYvr86o5ur9kAJqN+WJ0blKgKkFGn1jeRSTMVcMv9KqoTNnAX4jlLQrdtv4U40iRSUl9yVvY6Ua2smzOH4NDd1ukvwxy6m0H8VaxESEIz4Lol/kvmXHhud8GP3raPYGnXaBuZcjiHdqMReadMI1D20xQkwpZTbz7Tq/a7ws4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=X0x/5xTN; arc=fail smtp.client-ip=40.107.92.69 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="X0x/5xTN" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=TwZ0Nz362B6f8I2BTz2R8d7DD4YWW1vleQPJZGSMtlFEWD16V24pxTx1//qhhWEBvczAbGgoW4p76r/gduXFA+2kvYllClqDpsrIAdR4/8t0xNlSEaaig639oJUQ8+YTyalv0ZmpsrtWVru8483ruwQtAvwFNDfVI6yG3IJPgFPekCUIGOvsmlEMw7pcTDpNpYsDjWKo/f9ji2A1ooIaDdzUeoHnDvXtbHqF/8wXp99nu7bPlzCHOPBp/9L4DjASph7fXTIeN0/xvl6WKymChmrYDwj9FFQy93pMCl3UVZGD9h/f6pgb1JDNf4pD1lup1iN4bSYW0BIglsXQ+atnvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Ic9WcFlijRl4/3uLjlD1vQwG/b5CUE426R7AuROnUeE=; b=FO1WQqKBgY5UWmYr4H24C3pcLyc+czCreWX2uB4RrIDPRIY+GJsKl1HyDvrUTRwca5NlkfQtoaJa4afunihNSbkGNmWooJmkSdPP1aZj0PyPbM62n4NezpOQ0NpzGri9/BHjpOoQ2ASA4lxg8qOsRYZwEa5bkVgrA17RmQPI3b5B/MWpNHcb1khhempugiB27z8rAbwvT2/XmDloJ3WJrB38JXAfUSB5h7vSkUXu4NSv8l5FctD2XjxkkkrR2Rrj2zxDifQS4bV3Euh+ahtrwcHNSCgKIduU7+VUmPkXSaBzb1jpiNsUjxjXqUDVjIUsJf7H238nf4HwT2F+CId9jw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Ic9WcFlijRl4/3uLjlD1vQwG/b5CUE426R7AuROnUeE=; b=X0x/5xTNz0fIXUzi7yfo7tMxrFyAgtatTNG699SMKLHmPqnJ3mNzO5K1QgpBJiGP+LuzjoD0taPr9Yodz/mGPo1QkMfBzruDSh1EwYLl2zJ8Il2eEZqLm9e/ATzWGBkLpVVi/j2Ahj/lizVNdWRpHyQ3DXsp/TFUTj1Z3AwRu1meC8jDMPtvgQMiBDZNaSc//61/vLi7RVbVPmTwAV+kGuWOWepA1zfpWXlRQyzglOzDsuiPXEM4fFI+3l+rif5qcsYI8MruVQkKGuoI0Dqy62ySTBWZv9Y6BJh4kFIS8l+zbNRE5zw64wFirCjMMGAXaoq0vyczO2UPcik/XxtzpQ== Received: from MN2PR01CA0052.prod.exchangelabs.com (2603:10b6:208:23f::21) by SN7PR12MB7936.namprd12.prod.outlook.com (2603:10b6:806:347::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.20; Sat, 9 Nov 2024 05:49:05 +0000 Received: from BL02EPF0001A102.namprd05.prod.outlook.com (2603:10b6:208:23f:cafe::19) by MN2PR01CA0052.outlook.office365.com (2603:10b6:208:23f::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.21 via Frontend Transport; Sat, 9 Nov 2024 05:49:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BL02EPF0001A102.mail.protection.outlook.com (10.167.241.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Sat, 9 Nov 2024 05:49:04 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 8 Nov 2024 21:48:58 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 8 Nov 2024 21:48:58 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 8 Nov 2024 21:48:57 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv1 2/7] irqchip/gic-v3-its: Bypass iommu_cookie if desc->msi_iova is preset Date: Fri, 8 Nov 2024 21:48:47 -0800 Message-ID: <4e675b8ae803a478d10e675407ee1ff5f1f65890.1731130093.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A102:EE_|SN7PR12MB7936:EE_ X-MS-Office365-Filtering-Correlation-Id: 06986a8a-70ad-459e-1c8e-08dd00823862 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: 1jTsxvCDGd/a+9zyaIoGl2ei6eED4I4AhNSdgS76MOaORRekaXizy6KBOTxn3QMdZ/7X1Dd2gNFje1lbjTPbGF3NUGLbalEk+pjvxMRG+6uVQViukkvsAzn0a8mxSbs2XEVxyEYu9oAGb6r2pEaPJOYgr6jSTU35fg8KYEPNv/zchhXaODHS01I3Sq1RFGHSrKGPYSZ504eU5i2zWY5Fl1PwOqEGFuvejgjeITJJZfwUdVROIdiv7Bv93jXCKs+DaJFctp8W32uK7k8F6Yr2iOiBj0bHmDfk3gvGuri6EmFl1BWmtDhxeWda/v2gw9V8tJajrFaPseRV1mnUOFVNYbgMKqIKCVYZVzNkYZfWrGcQA716xHrhcb2HwTlQsStkTxaA/SJ7AsPi9xItWBxVZ9x8mIzjUmhxUvaMoufaPvUTib2AcHg1zntP8Fc9FitIp7dlhvWSQDmiHFspCa66xATzuCRWizrfMX0np+8gliL6ofweQLyUtbGfqg1YSlODxopEOVdiSWrTeTLguTjcSe5u9bTW45PxZpC4eU/Sukb2scS+rXHowSrLk9hjYlokoxF+GdFZXgOidHRFoJkvauDyIpCJEEjkwYQN/SOs6sCUr2iclNIF10VMlLnap/dzMYfUgMH9q2IVAQQ3tZTuBrIt9Se8VhnlrbB4h8BeEl/yjUZSphpj18g7l0DL5T789rjuG2Kswvpxj+7iBb80ZSejQ/5lB2jsjjOFJ+EmuK9Z1AUS1kydJCT+0zvJzUMWzrtz9kW4/Gk94eF90UqH3OhBBUC0EpueEl70CN4j/8rTRo1IijbBBSQzJxlv8E5tfJYUygS+cmb9OE7IJVjhn+byWJq2eHHB3s3x5mkvLRBI/x8sYQk3EktZCGynkGmrwCcJkoWS0M2wFNTGfv04GXtNBfUDZxmiM/PahMPKgXlSV4He5c31icSH2G3hAqrzoxt1Ekd7x9K9d2PIhTuxQSePcwl8WF05wQeVBooFB4ekVYWB/B2JooryOeLI+LLyPtY0W+lesSv2LkFo59pSn8UzBpI2IvLWew09rSGg7aYY0gKmXNFUdc0fCcozqc96zZU0cBHFmHpyoiA4HY1ahI/0yrnV0W57ex+ypfxWzBNHjLHSpuFIKf3VAtaYFteAVWitiRRb4YQXo/NhAIfBUS4YzNwqx12DxeED4aKaYMtIPzdXv2qGSlLYvsvOEPBDywtx+mhjXQNGBuxLn7+Q+zm4DfG6fBNr+/jnMtux+tVukeeTAiiyEYkNAh2IovaA3BaDCv+s7ZInuYM/BFwYkO4OL8n+1vFy2baiZa1TJoA/BrsXh1rOJMkjlhc33J6soGbMPAF5An2l22BP3/6e3uL5Cd10GVaW4/9O3kRYaFTTjBOKvrxtE3J0qvAsBZPAvy174IorYnyRiLAlkzcmjQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:04.6618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 06986a8a-70ad-459e-1c8e-08dd00823862 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7936 Now struct msi_desc can carry a preset IOVA for MSI doorbell address. This is typically preset by user space when engaging a 2-stage translation. So, use the preset IOVA instead of kernel-level IOVA allocations in dma-iommu. Signed-off-by: Nicolin Chen --- drivers/irqchip/irq-gic-v3-its.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index ab597e74ba08..bc1768576546 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1723,6 +1723,8 @@ static u64 its_irq_get_msi_base(struct its_device *its_dev) static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) { struct its_device *its_dev = irq_data_get_irq_chip_data(d); + struct msi_desc *desc = irq_data_get_msi_desc(d); + dma_addr_t iova = msi_desc_get_iova(desc); struct its_node *its; u64 addr; @@ -1733,7 +1735,13 @@ static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) msg->address_hi = upper_32_bits(addr); msg->data = its_get_event_id(d); - iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg); + /* Bypass iommu_dma_compose_msi_msg if msi_iova is preset */ + if (iova == PHYS_ADDR_MAX) { + iommu_dma_compose_msi_msg(desc, msg); + } else { + msg->address_lo = lower_32_bits(iova); + msg->address_hi = upper_32_bits(iova); + } } static int its_irq_set_irqchip_state(struct irq_data *d, @@ -3570,6 +3578,7 @@ static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, { msi_alloc_info_t *info = args; struct its_device *its_dev = info->scratchpad[0].ptr; + dma_addr_t iova = msi_desc_get_iova(info->desc); struct its_node *its = its_dev->its; struct irq_data *irqd; irq_hw_number_t hwirq; @@ -3580,9 +3589,13 @@ static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, if (err) return err; - err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev)); - if (err) - return err; + /* Bypass iommu_dma_prepare_msi if msi_iova is preset */ + if (iova == PHYS_ADDR_MAX) { + err = iommu_dma_prepare_msi(info->desc, + its->get_msi_base(its_dev)); + if (err) + return err; + } for (i = 0; i < nr_irqs; i++) { err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i); From patchwork Sat Nov 9 05:48:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13869270 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2057.outbound.protection.outlook.com [40.107.96.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91B0A143C63; Sat, 9 Nov 2024 05:49:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.96.57 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131349; cv=fail; b=F3ISVQdx+njaGXW++yCRJCRZ3jhSMTSxwQf+oF8tgIcFimzS1X33csoWoLpjIGHZ7/+4kDdgjAadIHex5s12wluBVNWmX+qWmaZP1lHD1VJAC4MHzvWUfmJwhgyPcjtKSI43RUDUHXBh5pWxDX3hbqC0ADEbAoB0v78flC8lNZM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131349; c=relaxed/simple; bh=eZLahTikRNRUaHH4pZY2Hw9vVCJ6h1D4j0g5q8bvhZ0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ytg9RLqJQ7MDDQmJn4LMzqYb4YJqG0HIGD3c7hsf/mDnRpTtTGcnq7DoaUKMlHmEJaTmk9lOGR9/S+ZjNl6CYOqMmIM3PzrcaSo9skB+NE4W2K2VxlAWsABAbTYIZPv/j+YcKo7hpm/zuGxGX5zQLCjzbc2YpVg9s+EchB07IIY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ABe8A5CN; arc=fail smtp.client-ip=40.107.96.57 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ABe8A5CN" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=uP9PeMqGyWX6FsyOgYUqEvv/zYwq2y4WIx2SnVAdeSqRgAztttpifcrtaCYKBPFnxq0kPLqIrpEcIaG8C0hHIlg2u8ppzd55NSaW8/c2zm2UmTLj/3j5JCJBP/A8t5+YHPYRiW6c47Iu51/BZ8bjO8JF8+rTr1b7IGspypCkj0w0EONXUdrJhiFx4hG0w7KPdIcEjXUAMDjoResiBi3md0rWp25CpEt0dOZLIV6s22Z+y47WaBNkOrPmFy7gCMbMkIT+tVppDia7e+ufoRu94HP03VTc0ybyi5V37lz70iQsKvDDBDNbo9hjQTQ5T6plK5EQwNnaeB4nJ6ymZUpsSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=XSeFbvMpl5Yo9vXT0GJbfiR8ITLquv0llC5EFsauH+Q=; b=Q/MF8RseTUJZzj+6OREdyQK7I+h7AIk7lHhuclH8KGVSsfB+f0I6KrcLS3R7WoqveCK64Ca7qZx0+bZBrwiZ1ZKhqxCXVZdf5GqdN3cXAjQoj3lFEzfSXU1HdhyAnh2LIzGpAsttRSny3XT+cITJoljSsvyOus3kHYEOjWcNHLiTIvJQE/Azo5jJL85Q3XMoAYY8iEWhafiftM4/nyc2ppo+LJ0YIrm4VglZdqxsrZ6/vFSAx0cw77nfsQjvI1yVYYzJ8Y/VHvrgKARclq3sp+XsTSi8hJ7NtnHu43wkV4/JCm22BADqqFy1Jnjet7aBhK+EX2eQFmLav0rXuSzRPA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XSeFbvMpl5Yo9vXT0GJbfiR8ITLquv0llC5EFsauH+Q=; b=ABe8A5CNg4f2JUiwPo5a4XC+M8LeIGGugk0pFY/ApX5tYMHf5IYnSsy+laCkTvVxBbbsvzKkiVbeNddGdnLImnPld/Db5t9Gj1ihElYmFOYKqnCESLHXZ0p/RO+0BcQ4+j3rcJlM0i+RMylEQwylJPQzBzwCP7Vl2k6/c9JkP/wibV6O32hyWBg2Eb+20G7/hM7TXKnwbSDHTN7pBxH5VVzMuNQFZfUrxHAtUIF7jVFwJajLQe6uNCzLKJ4lzF7VWNwM4jP7BXOtJG2PmTS8Coo6wQRfJbC6mQv4WSClD46d4K6PFM6Ww9CibZ+CLW5jly65r8sGFxG679NvlZnISQ== Received: from SJ0PR03CA0226.namprd03.prod.outlook.com (2603:10b6:a03:39f::21) by MN2PR12MB4390.namprd12.prod.outlook.com (2603:10b6:208:26e::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.21; Sat, 9 Nov 2024 05:49:01 +0000 Received: from SJ1PEPF00001CE9.namprd03.prod.outlook.com (2603:10b6:a03:39f:cafe::2c) by SJ0PR03CA0226.outlook.office365.com (2603:10b6:a03:39f::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.20 via Frontend Transport; Sat, 9 Nov 2024 05:49:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SJ1PEPF00001CE9.mail.protection.outlook.com (10.167.242.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Sat, 9 Nov 2024 05:49:00 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 8 Nov 2024 21:49:00 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 8 Nov 2024 21:48:59 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 8 Nov 2024 21:48:58 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv1 3/7] PCI/MSI: Pass in msi_iova to msi_domain_insert_msi_desc Date: Fri, 8 Nov 2024 21:48:48 -0800 Message-ID: <32fe78c5ec4a08bf0414d80ce9ed9121270b9cb0.1731130093.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE9:EE_|MN2PR12MB4390:EE_ X-MS-Office365-Filtering-Correlation-Id: 11d964e9-49a7-44e8-c6a8-08dd008235bf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: Iwzk/sRcq3Sfumzqc/pu1OcERoHst/OzZ6ikpkHYwAg0+UivW3AbAHlAeXAyeuztMLKZVZG7C/Zw0fwIG3VPTVji3aOh+XTm97mKN/X6H7A5L6rpMQwBSBx86nvY9+M3OL7wwGCglkdr61xvG9POWqvycIknGPBz7UPMM2K7wqZoBcG9a8rU4tNieO7egF7FqRXQEHObU/rTTYxrWj9FZeqmW/liFDXxD8n9XYDwrdZ+HP48mIGAvUuZcYWiPPgjo5QP8jkgpzNNJLVM8aPGkrelgqOxClUXoWJAmZqnAdfKKIxFuabxpNlpqHBJgzrvnTlyQjr79M2eR4QR0P3jQztC8UtM8qUrBgAsBVLmGQ99zksmcFBNKTdjeFbSzkxggmFiZrXLukjTQ3V2QepSZESzN6d9YqVp2o6TGuP7THPRlaPA0aZBUHVLkOR/evsDfI5CJI8HAijE5w7zy6xQ0LTApwSutvpSgkjoyL014TgWZAFiL5XPIufOrsku4dJUUYw6oiLX2zm8doPAEZYQ9OLQLBgNx57j49krFKpTJ5TB/n3tEJC3m75YricxbRn9clYmH0ZgS0YnmyQEegFArdMihl0nP+H3BtZfOQouCO6rFQqOy2ywJDj+9F8twXq553CzraveNFTD3Z4MhFOSuwVV8vThi13/7zABwpc4CSNf5lug/TwAFkdeA6mXCPdQMS1hbdInFup/EuM/0Q9eLuC9uinGi5P6cqwB7RQ/gnv+tsNtZX8UrGtMv2csvYBCF3m1fRHzxf25Xg58jUnIwLqv6ZD5C9KSVf5VydsWfDqZoGL35EF8GyFptPAEzSaUjm9Jg6eb/JKAfAS2t1MCnBMxYGkXby82oZPb8dvt3Evd5uRBorJShui+ul5+RjzjW5WVlhLCHRcnBDJjDmCTYyNOfGV4oIRcHGEOmjJAlL1jHO9Av3RcI0rCvrZnvoyWgwDFMQioO+qL5LYXw3uxUgs/Mpsq5fstntra4N5853eY3jYSRRPiNp7wzW7x/S879AlLs8bqdnjpzWX003so5mTiTvTkv1aEg74I/hO3HaEACw/6Oy7kruZ63o+Tkj2IcvFJBFB4fVkRZCZKH+YKJuJjaIfrXc8m/7RJuZLJVX1SqQFW5qcIYE9XE6VdmXJQC6Mn9qrGQwcGSQsXnnUwV7jfqex3HFnnvgcwJJGfKg1v29svKzTSIvc9K0VaAWGBnkWv7EwjkHzpPyLDF06cM54A1ydolfN9LbY+a68rm+uj7Xd1mP3mxgK9apVWS9Ty7qLa0GfcSREPEp7/h38Q0krUmDkbw/n1yLCgeLe4L+1Mx+BChu+TJa3YmmG2nSSPCYYwWi1sdAdHg9k3ZxGG5/Wip+5hRKK3D4WU7Ex21NqCU2LOn4UB/0jQv3PLRSryLOFmjPOfwWZniDNC8vgAQA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:00.3675 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 11d964e9-49a7-44e8-c6a8-08dd008235bf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4390 msi_setup_msi_descs and msix_setup_msi_descs are the two callers of genirq helper msi_domain_insert_msi_desc that is now ready for a preset msi_iova. So, do the same in these two callers. Note MSIx supports multiple entries, so use struct msix_entry to pass msi_iova in. Signed-off-by: Nicolin Chen --- include/linux/pci.h | 1 + drivers/pci/msi/msi.c | 18 ++++++++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/include/linux/pci.h b/include/linux/pci.h index 573b4c4c2be6..68ebb9d42f7f 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1652,6 +1652,7 @@ int pci_set_vga_state(struct pci_dev *pdev, bool decode, struct msix_entry { u32 vector; /* Kernel uses to write allocated vector */ u16 entry; /* Driver uses to specify entry, OS writes */ + u64 iova; /* Kernel uses to override doorbell address */ }; #ifdef CONFIG_PCI_MSI diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index 3a45879d85db..95caa81d3421 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -282,7 +282,7 @@ static void pci_msi_set_enable(struct pci_dev *dev, int enable) pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); } -static int msi_setup_msi_desc(struct pci_dev *dev, int nvec, +static int msi_setup_msi_desc(struct pci_dev *dev, int nvec, dma_addr_t iova, struct irq_affinity_desc *masks) { struct msi_desc desc; @@ -312,6 +312,10 @@ static int msi_setup_msi_desc(struct pci_dev *dev, int nvec, else desc.pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_32; +#ifdef CONFIG_IRQ_MSI_IOMMU + desc.msi_iova = iova; +#endif + /* Save the initial mask status */ if (desc.pci.msi_attrib.can_mask) pci_read_config_dword(dev, desc.pci.mask_pos, &desc.pci.msi_mask); @@ -349,7 +353,7 @@ static int msi_verify_entries(struct pci_dev *dev) * which could have been allocated. */ static int msi_capability_init(struct pci_dev *dev, int nvec, - struct irq_affinity *affd) + struct irq_affinity *affd, dma_addr_t iova) { struct irq_affinity_desc *masks = NULL; struct msi_desc *entry, desc; @@ -370,7 +374,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec, masks = irq_create_affinity_masks(nvec, affd); msi_lock_descs(&dev->dev); - ret = msi_setup_msi_desc(dev, nvec, masks); + ret = msi_setup_msi_desc(dev, nvec, iova, masks); if (ret) goto fail; @@ -456,7 +460,7 @@ int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, return -ENOSPC; } - rc = msi_capability_init(dev, nvec, affd); + rc = msi_capability_init(dev, nvec, affd, PHYS_ADDR_MAX); if (rc == 0) return nvec; @@ -625,6 +629,12 @@ static int msix_setup_msi_descs(struct pci_dev *dev, struct msix_entry *entries, memset(&desc, 0, sizeof(desc)); for (i = 0, curmsk = masks; i < nvec; i++, curmsk++) { +#ifdef CONFIG_IRQ_MSI_IOMMU + if (entries && entries[i].iova) + desc.msi_iova = (dma_addr_t)entries[i].iova; + else + desc.msi_iova = PHYS_ADDR_MAX; +#endif desc.msi_index = entries ? entries[i].entry : i; desc.affinity = masks ? curmsk : NULL; desc.pci.msi_attrib.is_virtual = desc.msi_index >= vec_count; From patchwork Sat Nov 9 05:48:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13869273 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2057.outbound.protection.outlook.com [40.107.92.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 987FD14BF8F; Sat, 9 Nov 2024 05:49:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.57 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131358; cv=fail; b=SPjnf0PoMGPcPUubHoERUJMTk3CXAnS5UT4WO9OOR3Ma+qb65pbjLKkcO0G+pxw9wvo/rVLpNmr7q5gnHXIC7hZ8SDfsY7xBFWSAKHr2llSxsxFlUK3gpKMyaI9sw237zPU1XUB6MkWCs/10Q1EMvCvjnmM/24uxrBBJSL5RvIY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131358; c=relaxed/simple; bh=bXFYO9rTdO6i2O/H47RIRRSCcdl5k5Z7u1d2cCLTd/Q=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=J0oO5EnW7FE4kIlVl1VO7uqWOOQLxKIf+dMjWLYAKHgaArKtQjbrqCDwHrhdlPsSnkOx/EVrwSxd7+Bgzlx3W/za031unrbD6Yi9vRzltb7n0QcBIYAc+VFs4O6+63tWsZmQm4Exgqba+cWac6X+6BFoqkebWWam31fhkR9kbgk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Vs4BBe/q; arc=fail smtp.client-ip=40.107.92.57 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Vs4BBe/q" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=V19DnOCfd36gGSO+A/Bb93wEjA1lZ0qI8TqhDJi2GhPrq35zNUQ2Gva5CnSuyzJWvmMRPxMnSw/oI+S+Qu/rsrxY3puQ7sq1dLyHmtuSpenzFBT5q7JQZITTJXtFAX2gRAg1eGgvi3g+zYbHWGVhWQ/ytR5JaCoDCQZTGEDVVZavtuNEV/INld4wumkvDEM2JeP6q1U+wCXGQq8VfdEfpy6JPl9ivuO8yAPGYcDKELOojYZU1sr+qLnBmL9ADgiuYPv9hSd8l9ht8NzK3a8xXLzTnLcMqqwtSPgdPhP6qxedJq1mlMz/LkPksMyFrkjJISYbzZYt8zJINZUCQS3xsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+91tI5iywXyBRXTWmayMkejXNh87K1xSpnzg/y9ISXE=; b=n1piVh0feFcTSJpbk0p9pcRjqGAXrhFtIRV88HQXNsqjrJwm7XszU2ojSX5d7VnJsqeVr2uyuSYPGsspQtlNZZWtJrIiIBbU1exAPJWeEFkbgZu/+xEPwR1CyfAWDWYsE/TvICZr1p26N35aytq3hfnupgM1m0p6FLDU9Wyd8HQblfpl1OUdtquZSIL+D5TrpleL8jXzGYayJIgXW5MA5bcvcHss0mv1lvC2jyeOACKgWG1ltBQW4miyvEuMi5u5KqspCB98iwln1fGGQ6d49X0COUm9/Hx1YR9iklW3YPc6AhpdcOeZIFBUPS0TUHgrT7QDRrbWH1evH/WaOIJrPg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+91tI5iywXyBRXTWmayMkejXNh87K1xSpnzg/y9ISXE=; b=Vs4BBe/qpOPBDbc4pg3LEy2v3NPlIyeVfDU9+8ScQ7wu9R58OxCC2hMsAXmJRFtPM9kMfH+GHxM7w/Wp2AJcsnMsUCPm8BWz4TxSv+uL6pDmVzuWIsmMwN1ErVd0nc/CVolcMKUPbcDPfAhsu6x/OyJpDaPJ9kUbqeVsvkQoA1Yjai2TYV2IBAoaXBQiYKv3CaPHqWBv8x6gOUkD5mH0bj6KFqjy2QIhPx5GcRr8yzmngIVLNVGnwDxY9kM9E8AJLqK/rYBRdPtR94JgwgbiOt60+MLxeWbFvSZ6HjnEYcPqbMEKs8jFDu2fYtjGDbQy42463uaBM5Iz3mzczd+ffQ== Received: from BN9PR03CA0252.namprd03.prod.outlook.com (2603:10b6:408:ff::17) by DS7PR12MB8372.namprd12.prod.outlook.com (2603:10b6:8:eb::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.22; Sat, 9 Nov 2024 05:49:09 +0000 Received: from BL02EPF0001A104.namprd05.prod.outlook.com (2603:10b6:408:ff:cafe::3c) by BN9PR03CA0252.outlook.office365.com (2603:10b6:408:ff::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.20 via Frontend Transport; Sat, 9 Nov 2024 05:49:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BL02EPF0001A104.mail.protection.outlook.com (10.167.241.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Sat, 9 Nov 2024 05:49:08 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 8 Nov 2024 21:49:01 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 8 Nov 2024 21:49:01 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 8 Nov 2024 21:49:00 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv1 4/7] PCI/MSI: Allow __pci_enable_msi_range to pass in iova Date: Fri, 8 Nov 2024 21:48:49 -0800 Message-ID: <7406707cbcf225fe8f6ec3ce497bdcfc51f27afb.1731130093.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A104:EE_|DS7PR12MB8372:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a22acb9-c352-4df2-63ca-08dd00823ac0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: +BxGLQyfguj1Hwk2IQFxNgNS/8XzZOQ0d+YklEHOPj3HusDo+AS++Y5mFjwOpyLLdRrae+JaLcyXACFQ6iskc/sRbSAdyk/m/Due9m5ohc2RuFDlqKX+pcEEDlCertcX+HZGQIWh5jjFmZzufR9OsscyWRyLCXKacHSrwENe1ckFg0rvYLpc83H2VHL94/Eeyku7WfQjif0rMmzOxKIiAzvHid9MwX8BUj8yhiqWM77XO+g85okVLHe+lekTzXAHjS55p/1OdxFH6sa2TOGoUfAJa/gMWBP/w8M8JhfmPnUf59LPAFnxNGnOCw3HhMwOowyjfs298jbIJH/cNV8AEF9iLyFUow0d9HQxLXqN1ecZjESTpvcHf5qQQ6mMNAOsk7rLYT1kHMcBWruvtr4QEM4flgSYYCk65KlX8/Ri5R3KpoFFOrQQVdhGao5ktboGbOljvG+vvwgiACL/NxREwNrX7CnsjPb5ddGR9l8vY8DHMn4jr3dQZ+KJU1YWs2ttZYs/3/NuU7Bhsj97ShziyaHlWjaHTBtV+bZ0upYeO7kieYAI+YsFoAAqyR9ZNeU5c4jxOYpKzBsGYXSwb+QdC+BrReodGVJURiYqX6Qxj0L7e9c2PtLwtzexJRHlw2/j+CSfZKI7flGg4sBg96HwLsYIKZkkNdVjI64IuruIt0D2Eln3UhvdWunAzVamzXvf8bBdcm9hnavshGoz+CeReF6R5Vb8iR8bWjxgJl5lcGj7CeNIj3BVPmr7rG7VP+JhF0Jz0LkVFqy+DLUG2wzXyXNdqPJw0T6eAz1R089QYfzXXEtHR2JdC3NKzAj0Nsaqfo3FropJx3yPQW0aUWEMTVHV+sWc1sYsa6lWMve2LbBgjVG8OnvzPVqU25M9Wpgj4aNH7BNx11onfur+vErH515y6IoS0QBXHj6GQglpnrWFbV6n6HuQZiulQyERShX+EFYKVFqhWm0x8fDJRHRKCLMXIv6HUWRJUpUMOCPlUqDzbe2+PB/X7C/ULIZkQmEE42iNcQ6GU1X0CbhQ6pvxcj1BHtcgRsMPSxqno497m+ku82cz6v5EFucZlfy0bsPu9FnTzt4Tivka7A9fcvHVdnRRdl+1+W5+YnjUkBUGwfJP0IN46gmfoCRDDIwU60uGg6/4Pi3bC6b87yBRLUqhERR6lNMibgBtTzhi8GkXM5G1vTWhgRTJMFir1t0RNl8++8nYuXUAWEibuUh/V6FRIyrZy45axEgvxR3y+M4FFAN+7crVnVnZjhq/6E/U4VasL+NOEMIw5l0VMclHvRH9xYjZOHdSid9PiAMwlFIEb99aYH5/zvmykFMBwTTdRa9TVJPO04WztyF4+367bcOhk78+TvNKJcAf6i1EH8OWm8OR5iGy1y5+Ys2Eal1jEMDdkgNYWBsP8hYayV/nf/lZvw== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:08.6351 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a22acb9-c352-4df2-63ca-08dd00823ac0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A104.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8372 The previous patch passes in the msi_iova to msi_capability_init, so this allows its caller to do the same. Signed-off-by: Nicolin Chen --- drivers/pci/msi/msi.h | 3 ++- drivers/pci/msi/api.c | 6 ++++-- drivers/pci/msi/msi.c | 4 ++-- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/pci/msi/msi.h b/drivers/pci/msi/msi.h index ee53cf079f4e..8009d69bf9a5 100644 --- a/drivers/pci/msi/msi.h +++ b/drivers/pci/msi/msi.h @@ -93,7 +93,8 @@ extern int pci_msi_enable; void pci_msi_shutdown(struct pci_dev *dev); void pci_msix_shutdown(struct pci_dev *dev); void pci_free_msi_irqs(struct pci_dev *dev); -int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, struct irq_affinity *affd); +int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, + struct irq_affinity *affd, dma_addr_t iova); int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, int minvec, int maxvec, struct irq_affinity *affd, int flags); void __pci_restore_msi_state(struct pci_dev *dev); diff --git a/drivers/pci/msi/api.c b/drivers/pci/msi/api.c index b956ce591f96..99ade7f69cd4 100644 --- a/drivers/pci/msi/api.c +++ b/drivers/pci/msi/api.c @@ -29,7 +29,8 @@ */ int pci_enable_msi(struct pci_dev *dev) { - int rc = __pci_enable_msi_range(dev, 1, 1, NULL); + int rc = __pci_enable_msi_range(dev, 1, 1, NULL, + PHYS_ADDR_MAX); if (rc < 0) return rc; return 0; @@ -274,7 +275,8 @@ int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, } if (flags & PCI_IRQ_MSI) { - nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd); + nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, + affd, PHYS_ADDR_MAX); if (nvecs > 0) return nvecs; } diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index 95caa81d3421..25da0435c674 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -417,7 +417,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec, } int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, - struct irq_affinity *affd) + struct irq_affinity *affd, dma_addr_t iova) { int nvec; int rc; @@ -460,7 +460,7 @@ int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, return -ENOSPC; } - rc = msi_capability_init(dev, nvec, affd, PHYS_ADDR_MAX); + rc = msi_capability_init(dev, nvec, affd, iova); if (rc == 0) return nvec; From patchwork Sat Nov 9 05:48:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13869274 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2062.outbound.protection.outlook.com [40.107.237.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEF2A14EC6E; Sat, 9 Nov 2024 05:49:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.62 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131360; cv=fail; b=plau+gu537ZQB63+tH3PASPieVTRpmiUeZ3liXd8dwqFPVCxr++vDHWrM8mT46Dnx9RPjZcweK3kri3Cxe7I9DfmZPiB/EgYFcTJj5bms3MGPAcESRg5pgIRZmuFtPVEUS78ikKGPUK8h5tCZ8NZOzd2h4yezbx0LMVxDc9ylWM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131360; c=relaxed/simple; bh=23xKKbf/j1S6hNl4xZwEF2353LFR75gZbNylkWy0VPY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FKw7h4psDDdZP6YkJ2rMj0QHtSJQY+hXY+L0Da4Jn995axawGRReP8R/n8G7S8dRD46bKhljNNmINya8BqX9vOwv2nH1LNiw/xGcBG/xxTgYl38TkIdTx1q+qYHgTetk3A9wgywfrAVdrAxiL6nkjlm4ggUPUJHxXcBF9xFiAfA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=j6AuxkNK; arc=fail smtp.client-ip=40.107.237.62 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="j6AuxkNK" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=l8B+ABRE8I4yx5KqnT+cYj0+3YHmJQjoLxWtdbMKY5MnIR+9OoG86gtl7+hP1edz+UqoPyU0Ak11erq2G8peQ++1P232GFF7yBpBGuWW3hz6JsrgiBCzmGJAf4O8qtIQxz/uApXQzY6SfHt5xgADR/yn1puIon0vLGgiWZurNxYyYe99q9V7m/RNEFblxZ0i8UpeI3y7A8XyGpo/2PGyQwQxTWKP8oD1AMgjGvevZTws2mvkWk2QxDfE+iDcZb6S6TCiIK3R0xKOOWnt9MW7+ROBMUmCwo8XfkuddL2ihh/uf3fRw4pcjImPnDRNb5k2BoHgrcZvAi7yGSIsAQAHew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VDCsucoqKNwEFGz7GO3myzJx524PBXAsZR6DsVkLebw=; b=c6J3dMcfEmE8JLWH769wZ5yrTsNNak7qi2OtOQbXQdDh46jNeW94NB5LDBhFVrh5bOPeSuxtZQgnNY88IFz/e+d3wbTQq3mD7SG+aQXDdjkNLhMYDfU11e/70WSRfOZ9HjUs7UZbb8oqIKNrJUXaIb4r+/5HxB4vGT7eJ6NmhZfyR7Ob0KpND8QQ2cgQ8LUbm6YjoDjPMIAdTcvcdjdinFwPED/0X9b3y5Apwlebz1FyuvoQxpiqC2lYhll11SbqHzbvJlm3FYsQVzwNexVZRaFesKK1P7sxoBo1XXp7o4xHBIXHqeRD5O+Ar7nTPk7vPKU5f5G5Wf2QfAsyYyw7xw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VDCsucoqKNwEFGz7GO3myzJx524PBXAsZR6DsVkLebw=; b=j6AuxkNK8uCesbS92SMSGvXKbPSjND/KaCgAvrDZKiXldI+9UX3okxt683Zd3F7z7UCgzUWnZBH8DMymVZ633XveNuIM1yFEtroY0MsQ3I+krmvgiXJLspB0eQ41YJTICs03iMH6AKwHR7sM43JHK0R1vmZLLsrY5pwUXhzqbOuQdxPr/RpzSKrUw2kgqkiQm9LmY+y5PUI8Xe/VPGTa6qCJG40Lnm7hTZO93ilLhIQ0DgiSyQePZ/e05dMnarx1IqR8Nq5xdBUYr+9onfB31XPqOwsJZBzWLGFMRHIVw0KCcs+4B/QKqDM8BL8dpNECHGHA2GuqPsUda0ssY2xFdg== Received: from BN9PR03CA0262.namprd03.prod.outlook.com (2603:10b6:408:ff::27) by SN7PR12MB8103.namprd12.prod.outlook.com (2603:10b6:806:355::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.19; Sat, 9 Nov 2024 05:49:13 +0000 Received: from BL02EPF0001A104.namprd05.prod.outlook.com (2603:10b6:408:ff:cafe::a5) by BN9PR03CA0262.outlook.office365.com (2603:10b6:408:ff::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.21 via Frontend Transport; Sat, 9 Nov 2024 05:49:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BL02EPF0001A104.mail.protection.outlook.com (10.167.241.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Sat, 9 Nov 2024 05:49:12 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 8 Nov 2024 21:49:03 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 8 Nov 2024 21:49:02 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 8 Nov 2024 21:49:01 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv1 5/7] PCI/MSI: Extract a common __pci_alloc_irq_vectors function Date: Fri, 8 Nov 2024 21:48:50 -0800 Message-ID: <0c09c2b1cef3eb085a2f4fd33105eb18aed2b611.1731130093.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A104:EE_|SN7PR12MB8103:EE_ X-MS-Office365-Filtering-Correlation-Id: a84e2032-2e31-45be-a94f-08dd00823d2e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: jU6MCsoweLdVtWf3F1s+Vge4zLy4yxylCa+JsSdnVT62SYTR8w9DNhU03YB0BGf6pSFaRxtxiqHSJGjLQeAWbFyzL+aKAUWU3OHU6tySbixiFFxMVyQb03wNP3ZU7TXrIIWQEtM/Cj2yzxPTxdeqUZBfO1tHgtk4iMTVA7DM/Ryve3WVH6mONgewTRKkiRUNV2UTcZBeTkwq3ee7/Pf0b0lWc6aP/xQ75TETGoAnpOEhIfERfbTenYdhanqo0ZTMftVIqr4D2mctFh/aag4LO1x/vtR/XKAmLYMDUCXEC4hv3njMMJvTfn8mA0RX7/QgFsX3vfMEg/R9IakQP2pstJIZmWzppPKDtqgix7cboHsQgmVAn/iKFN+SHeCT64hNAwjM+KdLkwWt1yfJkr4pENYoe5UQm67M7AvPu0HT/+yagE0vaMBhnwQ0VBZOuJm2kIBpuyjwFeTAjswKThCvIcs6wxV2p+GVHIYojQ7zAjjgchF+jHJCJ+aHwSsCAGtcE4UXsbrh1gdfLkSWyG3N4hbspaJJJ1AHkmutq6eFeA63+qve6lR91VLpIODqjDrdxtVTHvAQxfhj3T+jH8ug4NXqggV6ufAv/bZ0IjF4CzLWkm1DBAitOg6AjAOqz8ufx5Bw4YejD9N65iM9cqCEguP0rJWCt3eTcvziJDCjDA67jUlck2nRK5ZSb78FJm07lWvE5XhqmPNWEmoOc6w6XobJXoLkBqxDPVg1sp518xbeGYzjFxcv9aDqyih9lb4QhkE2zCJAcT5emd71kS+rHQRBduig0Sm5MrKJ4nwAkXBw8IDBmG6BamuEm87j0ei2D++my7uE1PpdlIgLwPjX194kHWqbGQ2an/awDuKCE0rE+M6hDUbYTBbswd+iGhD0ycPjwQKEdHYCv6YUuNl312MaQ9SIJpM+nHAKs97RdLtYcyeaAsYg92UAklNj4M+3WnEstexyfFVJxzloAu0Rha8qfy5aDQxhf7w8v/n06/k3oui06Y2cF8dWs2RDYF9z+g/WkG4Bfx5iqhS6yAkIzN+2qz7xYevXk2rXjztDZLxRnNRertLd/on6kALPJoUbiv1k8wiO0ghMMMZwp6BfmwJP5plkHz0mQeunmUaHafaAKncu7qaqpGYIZ8Ss9rCPkTg8V+Cgnf/Mw2TakP7W/ddTr0TWL3Xi3LfTwUVkKe5hKOT5ak5BFge14w2ZB5ohdhs5sWhDwfZOYYwhlK+ExHNMuz7AcoeO/JpZkF0lgqP/1NaKygJlje8YN/8Dg6pd3YKSeeTaWcPJcIeYqJ3MRBFVztujxqBpE0hTAPIWoks5s5ZganaEl++b0u+FLjI3Fn6Gmi5/Gt4t3ndjvxge9hAtiu7ZBA8nVS6EiGsX3AHIRalxALHDx5MRHw/Nq2WMA6wVwSLqBDXr9PgxVIDwsw== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:12.6663 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a84e2032-2e31-45be-a94f-08dd00823d2e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A104.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8103 Extract a common function from the existing callers, to prepare for a new helper that provides an array of msi_iovas. Also, extract the msi_iova(s) from the array and pass in properly down to __pci_enable_msi/msix_range(). Signed-off-by: Nicolin Chen --- drivers/pci/msi/api.c | 113 ++++++++++++++++++++++++++---------------- 1 file changed, 70 insertions(+), 43 deletions(-) diff --git a/drivers/pci/msi/api.c b/drivers/pci/msi/api.c index 99ade7f69cd4..dff3d7350b38 100644 --- a/drivers/pci/msi/api.c +++ b/drivers/pci/msi/api.c @@ -204,6 +204,72 @@ void pci_disable_msix(struct pci_dev *dev) } EXPORT_SYMBOL(pci_disable_msix); +static int __pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags, + struct irq_affinity *affd, + dma_addr_t *msi_iovas) +{ + struct irq_affinity msi_default_affd = {0}; + int nvecs = -ENOSPC; + + if (flags & PCI_IRQ_AFFINITY) { + if (!affd) + affd = &msi_default_affd; + } else { + if (WARN_ON(affd)) + affd = NULL; + } + + if (flags & PCI_IRQ_MSIX) { + struct msix_entry *entries = NULL; + + if (msi_iovas) { + int count = max_vecs - min_vecs + 1; + int i; + + entries = kcalloc(max_vecs - min_vecs + 1, + sizeof(*entries), GFP_KERNEL); + if (!entries) + return -ENOMEM; + for (i = 0; i < count; i++) { + entries[i].entry = i; + entries[i].iova = msi_iovas[i]; + } + } + + nvecs = __pci_enable_msix_range(dev, entries, min_vecs, + max_vecs, affd, flags); + kfree(entries); + if (nvecs > 0) + return nvecs; + } + + if (flags & PCI_IRQ_MSI) { + nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd, + msi_iovas ? *msi_iovas : + PHYS_ADDR_MAX); + if (nvecs > 0) + return nvecs; + } + + /* use INTx IRQ if allowed */ + if (flags & PCI_IRQ_INTX) { + if (min_vecs == 1 && dev->irq) { + /* + * Invoke the affinity spreading logic to ensure that + * the device driver can adjust queue configuration + * for the single interrupt case. + */ + if (affd) + irq_create_affinity_masks(1, affd); + pci_intx(dev, 1); + return 1; + } + } + + return nvecs; +} + /** * pci_alloc_irq_vectors() - Allocate multiple device interrupt vectors * @dev: the PCI device to operate on @@ -235,8 +301,8 @@ EXPORT_SYMBOL(pci_disable_msix); int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, unsigned int max_vecs, unsigned int flags) { - return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, - flags, NULL); + return __pci_alloc_irq_vectors(dev, min_vecs, max_vecs, + flags, NULL, NULL); } EXPORT_SYMBOL(pci_alloc_irq_vectors); @@ -256,47 +322,8 @@ int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, unsigned int max_vecs, unsigned int flags, struct irq_affinity *affd) { - struct irq_affinity msi_default_affd = {0}; - int nvecs = -ENOSPC; - - if (flags & PCI_IRQ_AFFINITY) { - if (!affd) - affd = &msi_default_affd; - } else { - if (WARN_ON(affd)) - affd = NULL; - } - - if (flags & PCI_IRQ_MSIX) { - nvecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs, - affd, flags); - if (nvecs > 0) - return nvecs; - } - - if (flags & PCI_IRQ_MSI) { - nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, - affd, PHYS_ADDR_MAX); - if (nvecs > 0) - return nvecs; - } - - /* use INTx IRQ if allowed */ - if (flags & PCI_IRQ_INTX) { - if (min_vecs == 1 && dev->irq) { - /* - * Invoke the affinity spreading logic to ensure that - * the device driver can adjust queue configuration - * for the single interrupt case. - */ - if (affd) - irq_create_affinity_masks(1, affd); - pci_intx(dev, 1); - return 1; - } - } - - return nvecs; + return __pci_alloc_irq_vectors(dev, min_vecs, max_vecs, + flags, affd, NULL); } EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity); From patchwork Sat Nov 9 05:48:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13869272 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2055.outbound.protection.outlook.com [40.107.237.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52BBE146017; Sat, 9 Nov 2024 05:49:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.55 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131354; cv=fail; b=GOx3GhLYNNDDeuD1MEl49BYM8648/DZYb1uLwqWZ7iOOQOB2HTEplaEElZxWti29Ziy/ieffCwXOQcG9cO41vzFofv/iTipRcltR4q8FBXu284GzmGIaTafpjmpjwK1afhQOgNhbJI/gFpSA/aeJV/ngkWE/bID7K3pXA8madKY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131354; c=relaxed/simple; bh=VnEMmiaRgkL4C/i+0GkJb+PpJHjLpECLTKZqGdwB7ME=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bs/xymkSlgENk1uAzYw1BXjxS9B/ijdHIPzqdK21RvxxYJbI1sf+BkcFYJF+a23tLXDqTS5TL50TuGtu3+VSdiAweL98W1ce+DjytboKq0QuJ68T5HcofovSlaVcZ0dXKthiYacqBlidzv/bBZSS+DU96khZMkHIUluDHSLoSws= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=c9uet8y9; arc=fail smtp.client-ip=40.107.237.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="c9uet8y9" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=US4K42SuNqFEK6PQ32VQN7J7Rr6oqUS+X3rXfswDJhNFpMh4OjZdkJZonTiMRnavJs9Sim81FG27sbiZfZwbCDBAfXvKGv5WFJOtij19hsnM1jJlYV13q2pctU4a1z/BB2MCtKISVuyYHwlfbKQN2VHU+gaEwxTl05G6S6H9Ec8zLfwfRh74HNcSTzIaA+T3SRVDcCKg1pw2JlnzlY8f9Pf+LuZ8oH+DGq5CuSwnoBhf9hPluoeDMSnKCT+Y02V04BCn2/dxIDulYtFQ8turbVv5XlmT2KjBiEwPMErW0NwlLgcM1li/aY1YvXbkyxUzxDWnw2ADw8dprGhr0adXpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ubjJGxVvR0IyR7uOemJ+yodiGotqSCH73iEvc6maiKI=; b=GpYSEN0e5xLjAc3ON3BLzYzYfqjQ3TAfJU4/qI2Qu49gonXIfO8LTRo7gvzvTj4leG9R5+sI77Blc08bRRZjGZxKOOIpxM/4v/2vkPC8MYl+zKBRwQ2ZIIVwoblWFzNuXb6m2eW9CCOP8rjqh0uEQYtVVsy0maQTHw1s+hGe0qhs87sA+ep7Y14XwCE5AaGJqUMPTwXaSboQOtcxVv5h9Z8U1di/g3/rfXQbGMAVKwkOjPX8hcvV4UX8o60BJNDDJQGgq0/l/F4rqmnfg8QEVFzqnOCFZ4lmp8ci0ULV4IWxDjYhAEjPQiiB48Dy2tqbR7coI+OJ6jj/Vzvn/mdhgg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ubjJGxVvR0IyR7uOemJ+yodiGotqSCH73iEvc6maiKI=; b=c9uet8y9QeJI+pWsC+GHvzY7182QoYe6S/musLxj8mwzSJffnMcPKqhPn2X0Y3/xHVxFdKdV2P+8eKfuJi5YwKtUJ65TsVlbJ4zHJsUvsbEwEGx9lD/kcB97fTzNzzcvV7cFbJXIyOiWqcShRX9xTcdD04pJqGOXU2evLrDwXxjk5UNKMNIgutjjJIwzfm+cC4neueGI3IZmsLJZ6/d/NTVO9AEdeUCUyBjpUhRgtbymozgA7CMjbmPRC2YlAIH05im1mRW9MSsvV4iAErnsMvBxf2J472G9qowOgyYmML6N98S2zgDbYuBx/R3c0yNmJZgwhf3Ibh+xooTX2FidYQ== Received: from SJ0PR03CA0350.namprd03.prod.outlook.com (2603:10b6:a03:39c::25) by DM3PR12MB9413.namprd12.prod.outlook.com (2603:10b6:8:1af::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.20; Sat, 9 Nov 2024 05:49:06 +0000 Received: from SJ1PEPF00001CE8.namprd03.prod.outlook.com (2603:10b6:a03:39c:cafe::2f) by SJ0PR03CA0350.outlook.office365.com (2603:10b6:a03:39c::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.21 via Frontend Transport; Sat, 9 Nov 2024 05:49:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SJ1PEPF00001CE8.mail.protection.outlook.com (10.167.242.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Sat, 9 Nov 2024 05:49:05 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 8 Nov 2024 21:49:04 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 8 Nov 2024 21:49:04 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 8 Nov 2024 21:49:03 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv1 6/7] PCI/MSI: Add pci_alloc_irq_vectors_iovas helper Date: Fri, 8 Nov 2024 21:48:51 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE8:EE_|DM3PR12MB9413:EE_ X-MS-Office365-Filtering-Correlation-Id: 81d2d01d-8d46-48b0-deda-08dd008238d2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|7416014|36860700013; X-Microsoft-Antispam-Message-Info: 0E/YFO/Kzn+RYX+eaPQLSEKCnx1s9jeJBxXoYYNmiyuqg7tRRaQ1SxhzYdqWRLS0TfFFAOMtJsvBFSOirKWOPIkwJDNNHY23eTD5Xf257Yd+gmMOKrmXa6YD9eC/bfSNwRBSw7VJ0rnVWA42Nx21fYNicaq4sx3jQoEdB6ikNAcr+kywv7sv9G1q8uqpe8mMb4+N4v1tnQ+HcJ/iL7iJRPCclAMbX5qwN8qkjT8OqbY7e13fvpXJT3ayraDXY/aUl7I0dz/Eax8tCLFVu+qV+lpoMSKGUJBT5DtxRk3uKQ+bK1H6XiVNdeXmrTrTcvLvPJPfqC6X5AJRE181B6n41rsxIxcKmQ6/Ou341VdSZ7Bah3/nAGJ8pPUaGO8/bbGYkriNCHXSlhr3vDbrt0Sm5oJ8osh4dULKj0O8ihJLsjjytf7W0wTPMPGQEWM2L2ncKP4L/KhB7O/+JU6+9U5oI5277liOBr8e1fxW+75zhFpqzNyc89RAMepQirVqxNV2P+LDmy/3N4VUq9NjX7/pYqQt4xGwKrOYK/TI8QsYkqyl3nJDtWR9laAw77rUTb8qKWCn8foi0lYcrI8hgoUOY9pjCwWOtOQVLuCbeKfmsxm7SCAk50JzRSFXChz/mlWHTaS2RGLKFprHole98yfGhZpK62JHPlZU4B0X8Lfbeh/NFNNHorTZojmIpK0HnL6wHYqstOvTgUe+3Rul4pZeh19a/hFElRtrJgzLZT3oRapDF7TnqDcxmjA+aqbJdIMqrn+HzaamecgZ4eZ49LBaXRc3vNUDIV9UPTFuCndrDHxs1KOmvIS1xXgn0bNwBCRVGOVQSjPdgBf20QAOC0Z8RsIrgYqs5M69kmc6XqbbpoahdDOZBbb0lpbt3Oe0RSbNtOIcj3kOs3q6S/z0FBkBPPVAN1Q13IiwsFeU0SGvS7dsudDnPj/71bXtGpTFizClgXnMwChSbB/9d5HYrG6rVBrob0bR5AueuT8DkfttiOBu2FfOf38qFhhnSSkJSZuGGxGHp+U1otWv/ON+LxNltQ+GMd1+jn2oKVeIEnifXJ9jB75ny8XYtzfYPaYuutcNeZX4djWID6IfewETTgjFfvTmtGUhwIn3JrsqilTp3GmZ6DJpHjW+PuG+KaAcHDSdGoU+Cc3DuJ4+T8fERPwsmomcILBeL+6g0dvWqaxTtMFOW4J6o7aWJb9ciQDd9jYZWt+g3xKvyWIdZk+1WQ+PMumVZeIjEuU/ZEJ9//z1JotsMmshwFPL91PnzpKfK5C448I20gEg1uyq/swpe/0Cgi9Zex4c6RzzHaVtR3ROMq3boFLRgFd4dRCm1mHVuyCRRzjMECUzDrsdOATl8+OuwTRyEkS2oamjUyhghZvi11GLYy6tuZl+rJU7Q8kfBeclx/mr0hDkpR/xfnYaiVsMxw== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:05.5258 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81d2d01d-8d46-48b0-deda-08dd008238d2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9413 Now, the common __pci_alloc_irq_vectors() accepts an array of msi_iovas, which is a list of preset IOVAs for MSI doorbell addresses. Add a helper that would pass in a list. A following patch will call this to forward msi_iovas from user space. Signed-off-by: Nicolin Chen --- include/linux/pci.h | 17 +++++++++++++++++ drivers/pci/msi/api.c | 21 +++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index 68ebb9d42f7f..6423bee3b207 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1678,6 +1678,9 @@ int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, unsigned int max_vecs, unsigned int flags, struct irq_affinity *affd); +int pci_alloc_irq_vectors_iovas(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags, + dma_addr_t *msi_iovas); bool pci_msix_can_alloc_dyn(struct pci_dev *dev); struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, @@ -1714,6 +1717,13 @@ pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, return -ENOSPC; } static inline int +pci_alloc_irq_vectors_iovas(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags, + dma_addr_t *msi_iovas) + + return -ENOSPC; /* No support if !CONFIG_PCI_MSI */ +} +static inline int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, unsigned int max_vecs, unsigned int flags) { @@ -2068,6 +2078,13 @@ pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, return -ENOSPC; } static inline int +pci_alloc_irq_vectors_iovas(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags, + dma_addr_t *msi_iovas) +{ + return -ENOSPC; +} +static inline int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, unsigned int max_vecs, unsigned int flags) { diff --git a/drivers/pci/msi/api.c b/drivers/pci/msi/api.c index dff3d7350b38..4e90ef8f571c 100644 --- a/drivers/pci/msi/api.c +++ b/drivers/pci/msi/api.c @@ -327,6 +327,27 @@ int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, } EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity); +/** + * pci_alloc_irq_vectors_iovas() - Allocate multiple device interrupt + * vectors with preset msi_iovas + * @dev: the PCI device to operate on + * @min_vecs: minimum required number of vectors (must be >= 1) + * @max_vecs: maximum desired number of vectors + * @flags: allocation flags, as in pci_alloc_irq_vectors() + * @msi_iovas: list of IOVAs for MSI between [min_vecs, max_vecs] + * + * Same as pci_alloc_irq_vectors(), but with the extra @msi_iovas parameter. + * Check that function docs, and &struct irq_affinity, for more details. + */ +int pci_alloc_irq_vectors_iovas(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags, + dma_addr_t *msi_iovas) +{ + return __pci_alloc_irq_vectors(dev, min_vecs, max_vecs, + flags, NULL, msi_iovas); +} +EXPORT_SYMBOL(pci_alloc_irq_vectors_iovas); + /** * pci_irq_vector() - Get Linux IRQ number of a device interrupt vector * @dev: the PCI device to operate on From patchwork Sat Nov 9 05:48:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 13869275 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2084.outbound.protection.outlook.com [40.107.94.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D7DD14F123; Sat, 9 Nov 2024 05:49:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.84 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131363; cv=fail; b=TYylpRAQPvvGc7nasOF0bPya5keR322nD9UdLnmdHh6J7Ha/kpgx+df2CxQLpQrphDpSHku9snwn+8q1EuFpNwDKMrMZyqyRB4oLNkFOXUju9ysXSBeBYuiAXQOsTbCxusym1Xf3B84/DrjRsV78lvHiQ4pGyXVf649U+iVgNuw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131363; c=relaxed/simple; bh=fWWVhuTgIN+k4aCR4wZtrLhtBFrDVpDURMi9/t/A1cM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=J7kO7zkwhxdLI6DZg88Kh+K8J1ZRhTICO8/xtFJIKjUuxzsVT3cnyYx0OZN/Us4apB6bkHwnOVFZWllttuFDH4i8GPa5SrrK2M2CCmr4T5qsGodtcXtjdjHblVL7v1tDKiDgDR0krotQnZCFFKCJzM8AbjJiu46pXiEEAOLJN58= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Z6bmEvCY; arc=fail smtp.client-ip=40.107.94.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Z6bmEvCY" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=DD3rD0o7L7KNV7xADbDvxWZ/kJprdmyOS6nEQKV8HLSGqYxUkS7T7UUwYncORRT3MuT1fze100i9+PzPoSd1vNTY/3ww6QajclZCtfpB7QbwOkKwtsXt3OXho5m/epNXz22fyvpJUOVcGN6YW2CcK0JmtSSFQiiQYUMtoLlZYebrvx92L4aQzxGISW4LwCQGFpfSa5IhresMSokLLRMzD65t5HuBa/dFyfhhX8a1343PFnE63vqB/yDz+oQHpdv4qRWPBRNzyVYkKxXhra0QBp5fSIGCXW0PgSvk5LgmWCt552LUcL0od2OAWgjAK5PQ0q27AWMwWJUvIRIUyDpK3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=AtB4Nuk3NENW+kApVPhvU7iI6WEUv4ZRQySPYM2noOs=; b=ojRdGwIUVth2XPvrlV83XEcTag6+rxzHMj7GFsEqMj5NWrC+iqU/XOjj3O40DS/7pjDGMqBf3L82QHDVKyN8LAwjGN9QztL6FWONphDzT/JhvGds5sto2bf+eHpMaCDVrQny1rAs+d0I83GRp00fZPC8IUSvH/0I8DF119x5B3zX2NUHDfeppcb8uFSXBxY3bc7QkYAoInjsUOWzaF7AIRUB40P/Hlv5F4dNjwYqfKxpgv2lg9Mgz7AFi77VS/NK3LrqFo0s2KjTMsSqwofx1pc8rnWrKPaoD7ODHLxMCZvqlvpSt2sM4QZUfLH/0HuJeKeWFia+u958eMrtYtIh+g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AtB4Nuk3NENW+kApVPhvU7iI6WEUv4ZRQySPYM2noOs=; b=Z6bmEvCYADAsWltbQQ6DOkWJluZtJ9s2STKtN43jgQhEKsmRBTrTCFiObVJhQvSVUTjvA/x06nU3vJXWA0EsW25CyNEXPihe+tD46ZTpThPtBDvnV6Z08sS6hII9SbBtGu9CtbFMDbp3brr9VJMKpWJ0oBKJtoJLzx1QDQtYr1beQYCjrvtRPdYaZSQQtwdDGZeuTbSQVg3ahw9O2iff6yDShR4TAcuocRgDhg/JZWWkWdXL1rML4BxiguSmefsAoUD+iyKi2RC9vHGuNF6oKWvE6up5SBR8F/uncI61rzgYmd1w7kgQmP9uQPdPyTayuEjWf5pJi7ou1GuKVWdgkw== Received: from BN9PR03CA0253.namprd03.prod.outlook.com (2603:10b6:408:ff::18) by DM6PR12MB4451.namprd12.prod.outlook.com (2603:10b6:5:2ab::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.21; Sat, 9 Nov 2024 05:49:16 +0000 Received: from BL02EPF0001A104.namprd05.prod.outlook.com (2603:10b6:408:ff:cafe::2e) by BN9PR03CA0253.outlook.office365.com (2603:10b6:408:ff::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.21 via Frontend Transport; Sat, 9 Nov 2024 05:49:15 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BL02EPF0001A104.mail.protection.outlook.com (10.167.241.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8137.17 via Frontend Transport; Sat, 9 Nov 2024 05:49:15 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 8 Nov 2024 21:49:06 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 8 Nov 2024 21:49:05 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 8 Nov 2024 21:49:04 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv1 7/7] vfio/pci: Allow preset MSI IOVAs via VFIO_IRQ_SET_ACTION_PREPARE Date: Fri, 8 Nov 2024 21:48:52 -0800 Message-ID: <07623edc330420376e235607285a0f56b54787f2.1731130093.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A104:EE_|DM6PR12MB4451:EE_ X-MS-Office365-Filtering-Correlation-Id: 898678ff-363d-4644-f709-08dd00823ee2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: 4RGZzPd0VzgeAZB96EogBoPROCYecdCFNJKjuqpVSdZIWrM21uOMeRDfslRiHxHgaKIDQyhuTpCOfy6lyng/pa3h6lj1fnDdDY+szsz/zqocJx8we8mMTB1GUMS9f3G/iRx6SBQl34QV+lTNkUne/iKNPTzJ8wi44SZSS1UW5ulRe3v5E6LWjgfMmhAVTQ+Yxmj9cZV4xPG6T+GWlS6pu3GgjqQ1HLWPJ+an+cvhnSt5zAv3X44rvYhZJserliTGicLU13mkZS6G6qF9G6uyG5xqnrArXAniW+5nAYirVpq9z5hyvhgN7VkioNevU4GA7UyZTHAUpI9tiCAmkz3KQjx5g0cpEI7z4xOpgaEpYIK61SI8XLHhzy7/hOZflcgpxJcCgiPmLkO6MK59C7Xm83xqsdQWbETlYO27v01Uqw24yz4kgHDHu9nGh0gYQiR6Rc07Dq23qgI4AikTLHpRH5hD6mGwY92Iu7SkP8rvEAs/HRPUcf1i63r4zJ1Rhnu2EPJV1tX8rxDrofbdhcpUIyx8xXR+pOAUmK0ulE3QUjOCgtUu3spKxHpb4LtBk9QPwxZk4uDDdGq7Bj98wAxmBcpKsex3FOlO02ZxN7UoUy0NI7vFGZt7V8BVW2X0nzkh2NvGYenqkQgqtd+Q9i1v25hzDOl4neLHZk0NGPipSLQfPz3blqodfGcHnhYyBpgM2IrHnDX3eEeXsO3PRAbEHlNVe8pJmVu3tx3Oi9dFEc0zIPbKRw3xd+gp+wKUeJygnu00sfrWo/ef98jTWMnTmeVIXXB1Yia1XjjS4vi4SkobnS3KHLVYN1BCz3WT9M5SQbjX7KOqAvm/66MeWcptuvNsWtIIOOL6DL14u5dYiSGsk04r1MPJMrNEktTkgTUdUEuh3svwpgJJ3PmEVRVnxowSWt9r3/pJB4JRt7oTCQV5765TWn/qr48lay59LkUqxza2kJvlROc5jglpIAeoG+Wp+svBz0wESY0dM/kSV9MuXpupCxKU1IwWY0WA7AA/s7yC2MuCi+CZ3iVHBFKwO4swZIqODUClajQY4rU3eCoXKbQjV6bC+e3Yz73MT2oFMP3YGkPLbaD4J3AyTv2ycdexADB86Pz2JXB5u4hHpNK8CQ+ZiAfPWEbpwsEIpw+z5M50Ww5tHnEoII+FqLfQX8Ju7MU3Sgpin2yxlmACfljDSZsQVWNRIk8eCy5wSvMabhk5L8Tix3anxvzw7I9WfCP416JezQrWtXVj0+ZON7g3lz4vJadC5kvH5+v5ybSIlW8i+hM+av2WVy/xtiljdP+L4CF/xHe/9mvOmXCZwEpe7ubCBarhqE9CQsFYIXw6r5M0jzayiW9iLoZG5fxzve04tTXzH98jYM0+EMq8RbePLR3jT5oKcdJeep6oGZ2rDqf32aZCk7cIpA7HMgqiHQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:15.5882 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 898678ff-363d-4644-f709-08dd00823ee2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A104.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4451 Add a new VFIO_IRQ_SET_ACTION_PREPARE to set VFIO_IRQ_SET_DATA_MSI_IOVA, giving user space an interface to forward to kernel the stage-1 IOVA (of a 2-stage translation: IOVA->IPA->PA) for an MSI doorbell address, since the ITS hardware needs to be programmed with the top level IOVA address, in order to work with the IOMMU on ARM64. Signed-off-by: Nicolin Chen --- include/linux/vfio_pci_core.h | 1 + include/uapi/linux/vfio.h | 8 ++++-- drivers/vfio/pci/vfio_pci_intrs.c | 41 ++++++++++++++++++++++++++++++- drivers/vfio/vfio_main.c | 3 +++ 4 files changed, 50 insertions(+), 3 deletions(-) diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index fbb472dd99b3..08027b8331f0 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -63,6 +63,7 @@ struct vfio_pci_core_device { int irq_type; int num_regions; struct vfio_pci_region *region; + dma_addr_t *msi_iovas; u8 msi_qmax; u8 msix_bar; u16 msix_size; diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 2b68e6cdf190..d6be351abcde 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -590,6 +590,8 @@ struct vfio_irq_set { #define VFIO_IRQ_SET_ACTION_MASK (1 << 3) /* Mask interrupt */ #define VFIO_IRQ_SET_ACTION_UNMASK (1 << 4) /* Unmask interrupt */ #define VFIO_IRQ_SET_ACTION_TRIGGER (1 << 5) /* Trigger interrupt */ +#define VFIO_IRQ_SET_DATA_MSI_IOVA (1 << 6) /* Data is MSI IOVA (u64) */ +#define VFIO_IRQ_SET_ACTION_PREPARE (1 << 7) /* Prepare interrupt */ __u32 index; __u32 start; __u32 count; @@ -599,10 +601,12 @@ struct vfio_irq_set { #define VFIO_IRQ_SET_DATA_TYPE_MASK (VFIO_IRQ_SET_DATA_NONE | \ VFIO_IRQ_SET_DATA_BOOL | \ - VFIO_IRQ_SET_DATA_EVENTFD) + VFIO_IRQ_SET_DATA_EVENTFD | \ + VFIO_IRQ_SET_DATA_MSI_IOVA) #define VFIO_IRQ_SET_ACTION_TYPE_MASK (VFIO_IRQ_SET_ACTION_MASK | \ VFIO_IRQ_SET_ACTION_UNMASK | \ - VFIO_IRQ_SET_ACTION_TRIGGER) + VFIO_IRQ_SET_ACTION_TRIGGER | \ + VFIO_IRQ_SET_ACTION_PREPARE) /** * VFIO_DEVICE_RESET - _IO(VFIO_TYPE, VFIO_BASE + 11) * diff --git a/drivers/vfio/pci/vfio_pci_intrs.c b/drivers/vfio/pci/vfio_pci_intrs.c index 8382c5834335..18bcdc5b1ef5 100644 --- a/drivers/vfio/pci/vfio_pci_intrs.c +++ b/drivers/vfio/pci/vfio_pci_intrs.c @@ -383,7 +383,7 @@ static int vfio_msi_enable(struct vfio_pci_core_device *vdev, int nvec, bool msi /* return the number of supported vectors if we can't get all: */ cmd = vfio_pci_memory_lock_and_enable(vdev); - ret = pci_alloc_irq_vectors(pdev, 1, nvec, flag); + ret = pci_alloc_irq_vectors_iovas(pdev, 1, nvec, flag, vdev->msi_iovas); if (ret < nvec) { if (ret > 0) pci_free_irq_vectors(pdev); @@ -685,6 +685,9 @@ static int vfio_pci_set_msi_trigger(struct vfio_pci_core_device *vdev, if (irq_is(vdev, index) && !count && (flags & VFIO_IRQ_SET_DATA_NONE)) { vfio_msi_disable(vdev, msix); + /* FIXME we need a better cleanup routine */ + kfree(vdev->msi_iovas); + vdev->msi_iovas = NULL; return 0; } @@ -728,6 +731,39 @@ static int vfio_pci_set_msi_trigger(struct vfio_pci_core_device *vdev, return 0; } +static int vfio_pci_set_msi_prepare(struct vfio_pci_core_device *vdev, + unsigned index, unsigned start, + unsigned count, uint32_t flags, void *data) +{ + uint64_t *iovas = data; + unsigned int i; + + if (!(irq_is(vdev, index) || is_irq_none(vdev))) + return -EINVAL; + + if (flags & VFIO_IRQ_SET_DATA_NONE) { + if (!count) + return -EINVAL; + /* FIXME support partial unset */ + kfree(vdev->msi_iovas); + vdev->msi_iovas = NULL; + return 0; + } + + if (!(flags & VFIO_IRQ_SET_DATA_MSI_IOVA)) + return -EOPNOTSUPP; + if (!IS_ENABLED(CONFIG_IRQ_MSI_IOMMU)) + return -EOPNOTSUPP; + if (!vdev->msi_iovas) + vdev->msi_iovas = kcalloc(count, sizeof(dma_addr_t), GFP_KERNEL); + if (!vdev->msi_iovas) + return -ENOMEM; + for (i = 0; i < count; i++) + vdev->msi_iovas[i] = iovas[i]; + + return 0; +} + static int vfio_pci_set_ctx_trigger_single(struct eventfd_ctx **ctx, unsigned int count, uint32_t flags, void *data) @@ -837,6 +873,9 @@ int vfio_pci_set_irqs_ioctl(struct vfio_pci_core_device *vdev, uint32_t flags, case VFIO_IRQ_SET_ACTION_TRIGGER: func = vfio_pci_set_msi_trigger; break; + case VFIO_IRQ_SET_ACTION_PREPARE: + func = vfio_pci_set_msi_prepare; + break; } break; case VFIO_PCI_ERR_IRQ_INDEX: diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c index a5a62d9d963f..61211c082a64 100644 --- a/drivers/vfio/vfio_main.c +++ b/drivers/vfio/vfio_main.c @@ -1554,6 +1554,9 @@ int vfio_set_irqs_validate_and_prepare(struct vfio_irq_set *hdr, int num_irqs, case VFIO_IRQ_SET_DATA_EVENTFD: size = sizeof(int32_t); break; + case VFIO_IRQ_SET_DATA_MSI_IOVA: + size = sizeof(uint64_t); + break; default: return -EINVAL; }