From patchwork Sun Nov 10 14:00:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chukun Pan X-Patchwork-Id: 13870023 Received: from mail-m25496.xmail.ntesmail.com (mail-m25496.xmail.ntesmail.com [103.129.254.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2A21200A0; Sun, 10 Nov 2024 18:36:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.129.254.96 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731263817; cv=none; b=au9l5+w12ZKVroaFrRA8F5F2a0nDTskME3zrf0/oI7N57hML+s9EhCXopLwnpCUCEKGpHkrP6cK2LuIO6WNGtHkswW6uJLQAsFBySHPWLF41///TQpwCwM5ru8v1FPcnfNARUOmaV/A83QPLFwrDQKB9kEFppNxaAYakyS1FZvg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731263817; c=relaxed/simple; bh=VEiCcVBUQAXwHu1ffrHgeG5LsZdIgEmHmhV+woKGDz4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nZrWIk2IAtA31+MLUd3mKunralWVOy309EttKH/rxtwSdgDYPtsAu7NTIuHFLs7zLUCXpzzXbdwkWPmxyIS7HYEhk8Ln4F8m3yEDMN75iNBAjfD/ZuIrh0y+kEpRvgDwDRTbY8yTDodyXYZUdjic9GnS1Urk156/nNg5P6v9hFs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn; spf=pass smtp.mailfrom=jmu.edu.cn; arc=none smtp.client-ip=103.129.254.96 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=jmu.edu.cn Received: from amadeus-Vostro-3710.lan (unknown [113.116.6.44]) by smtp.qiye.163.com (Hmail) with ESMTP id 24fe03a5; Sun, 10 Nov 2024 22:00:41 +0800 (GMT+08:00) From: Chukun Pan To: Bjorn Andersson Cc: Konrad Dybcio , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Chukun Pan Subject: [PATCH v4 3/4] arm64: dts: qcom: ipq6018: move mp5496 regulator out of soc dtsi Date: Sun, 10 Nov 2024 22:00:18 +0800 Message-Id: <20241110140019.3426181-4-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241110140019.3426181-1-amadeus@jmu.edu.cn> References: <20241110140019.3426181-1-amadeus@jmu.edu.cn> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDGElIVkJPQxpKTUgfTkMeQlYeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlKSkhVSkpNVU1VT09ZV1kWGg8SFR0UWUFZT0tIVUpLSUJNSEtVSktLVUtZBg ++ X-HM-Tid: 0a93166077ea03a2kunm24fe03a5 X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6OhQ6ARw6EzIsPC0BIz84Nygz CgsKCTVVSlVKTEhKSU9MSU9KQ0JIVTMWGhIXVRoWGh8eDgg7ERYOVR4fDlUYFUVZV1kSC1lBWUpK SFVKSk1VTVVPT1lXWQgBWUFIT0lNNwY+ Some IPQ60xx SoCs don't come with the mp5496 pmic chip. The mp5496 pmic was never part of the IPQ60xx SoC, it's optional, so we moved it out of the soc dtsi. Signed-off-by: Chukun Pan --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 2 +- arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 35 ++++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 -------- 3 files changed, 36 insertions(+), 15 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index f5f4827c0e17..9c69d3027b43 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "ipq6018.dtsi" +#include "ipq6018-mp5496.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; diff --git a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi new file mode 100644 index 000000000000..fe2152df69f4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * ipq6018-mp5496.dtsi describes common properties (e.g. regulators) that + * apply to most devices that make use of the IPQ6018 SoC and MP5496 PMIC. + */ + +#include "ipq6018.dtsi" + +&cpu0 { + cpu-supply = <&ipq6018_s2>; +}; + +&cpu1 { + cpu-supply = <&ipq6018_s2>; +}; + +&cpu2 { + cpu-supply = <&ipq6018_s2>; +}; + +&cpu3 { + cpu-supply = <&ipq6018_s2>; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq6018_s2: s2 { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1062500>; + regulator-always-on; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 7514919132b6..a02aa641cb90 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -43,7 +43,6 @@ cpu0: cpu@0 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -56,7 +55,6 @@ cpu1: cpu@1 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -69,7 +67,6 @@ cpu2: cpu@2 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -82,7 +79,6 @@ cpu3: cpu@3 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -184,16 +180,6 @@ glink-edge { rpm_requests: rpm-requests { compatible = "qcom,rpm-ipq6018", "qcom,glink-smd-rpm"; qcom,glink-channels = "rpm_requests"; - - regulators { - compatible = "qcom,rpm-mp5496-regulators"; - - ipq6018_s2: s2 { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1062500>; - regulator-always-on; - }; - }; }; }; };