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Tue, 12 Nov 2024 07:41:09 +0000 Received: from KL1PR0601MB5773.apcprd06.prod.outlook.com ([fe80::b56a:3ef:aa9d:c82]) by KL1PR0601MB5773.apcprd06.prod.outlook.com ([fe80::b56a:3ef:aa9d:c82%4]) with mapi id 15.20.8137.018; Tue, 12 Nov 2024 07:41:09 +0000 From: Rex Nie To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, airlied@gmail.com, simona@ffwll.ch, avrac@freebox.fr Cc: sean@poorly.run, marijn.suijten@somainline.org, jani.nikula@intel.com, mgonzalez@freebox.fr, rex.nie@jaguarmicro.com, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, angus.chen@jaguarmicro.com Subject: [PATCH] drm/msm/hdmi: simplify code in pll_get_integloop_gain Date: Tue, 12 Nov 2024 15:41:00 +0800 Message-Id: <20241112074101.2206-1-rex.nie@jaguarmicro.com> X-Mailer: git-send-email 2.39.0.windows.2 X-ClientProxiedBy: SG2PR02CA0133.apcprd02.prod.outlook.com (2603:1096:4:188::18) To KL1PR0601MB5773.apcprd06.prod.outlook.com (2603:1096:820:b1::13) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: KL1PR0601MB5773:EE_|SEZPR06MB7059:EE_ X-MS-Office365-Filtering-Correlation-Id: d4796e07-7e94-4fb1-f00a-08dd02ed5fac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|52116014|7416014|376014|366016|38350700014; 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The condition base <= 2046 always true. Fixes: caedbf17c48d ("drm/msm: add msm8998 hdmi phy/pll support") Signed-off-by: Rex Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c index e6ffaf92d26d..1c4211cfa2a4 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c @@ -137,7 +137,7 @@ static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk, base <<= (digclk_divsel == 2 ? 1 : 0); - return (base <= 2046 ? base : 2046); + return base; } static inline u32 pll_get_pll_cmp(u64 fdata, unsigned long ref_clk)