From patchwork Tue Nov 12 14:38:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Klokov X-Patchwork-Id: 13872322 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6789DD42B8D for ; Tue, 12 Nov 2024 14:39:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tAs2Z-00019v-Rx; Tue, 12 Nov 2024 09:38:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tAs2Y-00019F-DP; Tue, 12 Nov 2024 09:38:46 -0500 Received: from mta-03.yadro.com ([89.207.88.253]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tAs2V-0000OH-GZ; Tue, 12 Nov 2024 09:38:45 -0500 DKIM-Filter: OpenDKIM Filter v2.11.0 mta-03.yadro.com 475CBE0002 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=syntacore.com; s=mta-04; t=1731422316; bh=kcBKHWOqWJd93VotvuEaZnhi/IDn7x3R36Qg7KqnjNM=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:From; b=b3fKQqbu4AFb5dKexkpHsffg9QJPAWErb+nV2+Gelf0KVZDqPlLRfDiVVNCP53QGs jHmUUrtQSEVPEhUhlsbZjTLHPMX+MaP1O7YaQg2BM4ACudnXrcFAl127E3TIAbTtPx GHtGVXjRA5PyqpDAGVKZ5VVjNLE7ixsIH3s0m+euCNUkDkXjSdn/laJTNQ1gEjgAjC reuj/CE3NAGP+pnI3f21HHgs6X5r28iI7iNWGbOdcObpuukWQjOA1skZ+jqZDcIVHU 0Uz/Zk4NMi/bk1Zu/1ZkXmKp0dvWzDhCZZrK6y2gTxhUz02LNQaGgRIFlCWloVu0a4 Vcbx5jAy8UpJw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=syntacore.com; s=mta-03; t=1731422316; bh=kcBKHWOqWJd93VotvuEaZnhi/IDn7x3R36Qg7KqnjNM=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:From; b=i/d1e1PsRQU+HhW6u/bGBjgledQ/uJ/QZygRooAcVhzvNSHtJ+4RH5QW+0ZiTeFVm LCd9XzvOljR/Kmgl1dA+8XQmJCwWttzoCBlx2gzXXWDQhHDx3Qtnd5fPkzxuL+cp+m 4YbFwqmzHKwYFmadVDKwY6EXamf7B3Kvl2q5NddjWluTl3L6mG0d8F2nPKPaX1chEg jpVHjEurUWQCSeG21Ubuckd4dHp7DJFF6yxs57MdqzD7rPlcNRdTvmZlGnwPTMiLGX 6ldZtt543L4uc8UT4Bo9NRGUZ/UEWDHDSoc0s7uWelbfF9Ug1LqHbw1KgKZZw2rqNf 97hPFEZRLwL0A== From: Ivan Klokov To: CC: , , , , , , , , , , Ivan Klokov Subject: [RFC PATCH v6 1/2] target/riscv: Add RISC-V CSR qtest support Date: Tue, 12 Nov 2024 17:38:25 +0300 Message-ID: <20241112143826.88130-2-ivan.klokov@syntacore.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112143826.88130-1-ivan.klokov@syntacore.com> References: <20241112143826.88130-1-ivan.klokov@syntacore.com> MIME-Version: 1.0 X-ClientProxiedBy: T-Exch-05.corp.yadro.com (172.17.10.109) To S-Exch-01.corp.yadro.com (10.78.5.241) Received-SPF: permerror client-ip=89.207.88.253; envelope-from=ivan.klokov@syntacore.com; helo=mta-03.yadro.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, T_SPF_PERMERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The RISC-V architecture supports the creation of custom CSR-mapped devices. It would be convenient to test them in the same way as MMIO-mapped devices. To do this, a new call has been added to read/write CSR registers. Signed-off-by: Ivan Klokov Acked-by: Fabiano Rosas --- hw/riscv/riscv_hart.c | 55 ++++++++++++++++++++++++++++++++++++++++++ tests/qtest/libqtest.c | 27 +++++++++++++++++++++ tests/qtest/libqtest.h | 14 +++++++++++ 3 files changed, 96 insertions(+) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 613ea2aaa0..0b725ff9ce 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -21,6 +21,8 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/cutils.h" +#include "sysemu/qtest.h" #include "sysemu/reset.h" #include "hw/sysbus.h" #include "target/riscv/cpu.h" @@ -42,6 +44,55 @@ static void riscv_harts_cpu_reset(void *opaque) cpu_reset(CPU(cpu)); } +#ifndef CONFIG_USER_ONLY +static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val) +{ + RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(cpu_num)); + CPURISCVState *env = &cpu->env; + + int ret = RISCV_EXCP_NONE; + if (strcmp(cmd, "get_csr") == 0) { + ret = riscv_csrr(env, csrno, (target_ulong *)val); + } else if (strcmp(cmd, "set_csr") == 0) { + ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, + MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); + } + + g_assert(ret == RISCV_EXCP_NONE); +} + +static bool csr_qtest_callback(CharBackend *chr, gchar **words) +{ + if (strcmp(words[0], "csr") == 0) { + + uint64_t cpu; + uint64_t val; + int rc, csr; + + rc = qemu_strtou64(words[2], NULL, 0, &cpu); + g_assert(rc == 0); + rc = qemu_strtoi(words[3], NULL, 0, &csr); + g_assert(rc == 0); + rc = qemu_strtou64(words[4], NULL, 0, &val); + g_assert(rc == 0); + csr_call(words[1], cpu, csr, &val); + + qtest_send_prefix(chr); + qtest_sendf(chr, "OK %"PRIx64" "TARGET_FMT_lx"\n", res, (target_ulong)val); + + return true; + } + + return false; +} + +static void riscv_cpu_register_csr_qtest_callback(void) +{ + static GOnce once; + g_once(&once, (GThreadFunc)qtest_set_command_cb, csr_qtest_callback); +} +#endif + static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, char *cpu_type, Error **errp) { @@ -59,6 +110,10 @@ static void riscv_harts_realize(DeviceState *dev, Error **errp) s->harts = g_new0(RISCVCPU, s->num_harts); +#ifndef CONFIG_USER_ONLY + riscv_cpu_register_csr_qtest_callback(); +#endif + for (n = 0; n < s->num_harts; n++) { if (!riscv_hart_realize(s, n, s->cpu_type, errp)) { return; diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index 817fd7aac5..43bfa496e9 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -1202,6 +1202,33 @@ uint64_t qtest_rtas_call(QTestState *s, const char *name, return 0; } +static void qtest_rsp_csr(QTestState *s, uint64_t *val) +{ + gchar **args; + uint64_t ret; + int rc; + + args = qtest_rsp_args(s, 3); + + rc = qemu_strtou64(args[1], NULL, 16, &ret); + g_assert(rc == 0); + rc = qemu_strtou64(args[2], NULL, 16, val); + g_assert(rc == 0); + + g_strfreev(args); +} + +uint64_t qtest_csr_call(QTestState *s, const char *name, + uint64_t cpu, int csr, + uint64_t *val) +{ + qtest_sendf(s, "csr %s 0x%"PRIx64" %d 0x%"PRIx64"\n", + name, cpu, csr, *val); + + qtest_rsp_csr(s, val); + return 0; +} + void qtest_add_func(const char *str, void (*fn)(void)) { gchar *path = g_strdup_printf("/%s/%s", qtest_get_arch(), str); diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h index beb96b18eb..b516a16bd4 100644 --- a/tests/qtest/libqtest.h +++ b/tests/qtest/libqtest.h @@ -575,6 +575,20 @@ uint64_t qtest_rtas_call(QTestState *s, const char *name, uint32_t nargs, uint64_t args, uint32_t nret, uint64_t ret); +/** + * qtest_csr_call: + * @s: #QTestState instance to operate on. + * @name: name of the command to call. + * @cpu: hart number. + * @csr: CSR number. + * @val: Value for reading/writing. + * + * Call an RISC-V CSR read/write function + */ +uint64_t qtest_csr_call(QTestState *s, const char *name, + uint64_t cpu, int csr, + unsigned long *val); + /** * qtest_bufread: * @s: #QTestState instance to operate on. From patchwork Tue Nov 12 14:38:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Klokov X-Patchwork-Id: 13872323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A3A3D42B8C for ; Tue, 12 Nov 2024 14:39:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tAs2b-0001AZ-IF; Tue, 12 Nov 2024 09:38:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tAs2Y-00019E-D8; Tue, 12 Nov 2024 09:38:46 -0500 Received: from mta-03.yadro.com ([89.207.88.253]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tAs2V-0000OL-FN; Tue, 12 Nov 2024 09:38:45 -0500 DKIM-Filter: OpenDKIM Filter v2.11.0 mta-03.yadro.com A1D9FE0002 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=syntacore.com; s=mta-04; t=1731422317; bh=D2oeDNi+IPRrlNDIyqj63bFRcYYcJD6T4w+fEFO7ZTc=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:From; b=p8e+K0w0RKqEp3bKY2KjqkQqcOe5+mVlF9e+CPE7dbOiIUpg6AhDcivIzkg8ZwMDT cjxPfcX6cZrEMFqQQxz3V5CaSQ8fakeW8NM7Ypo5HW60axRS39o37HcoEfWGIDwEMC aJpWorgXe1VvgRdOmWInmNzwdSGihncPnntAbFlRru5KlLlAkhw1YryzHxv4FDSD6k c2vxvuBMyuxLIHy1AN8mSD2r7tUAxFVv80SHDXAbJVLr+zxSPA6rrRooQ5wHLBmxEQ uJFsU1djk2RSAWRrg7fijkXLAuzBoUH6sPR1R28dkNxqBPN2EAMb2yoBx5baFgNaUA afIJgIj10DcIg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=syntacore.com; s=mta-03; t=1731422317; bh=D2oeDNi+IPRrlNDIyqj63bFRcYYcJD6T4w+fEFO7ZTc=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:From; b=qnvdXE5BIhAh+XZG2x4JH9QQyiK73Ih0DwJvT7ju8zMQZ1jFC8HMJe21y7ZCMB51b v6pgIaO4nEmx0O28EQ1qrNOaFfamPkMvtVoILq6hwY4uBx4VJmukhNdrGV3EWeAcJr mZ/5iuU4BZKeNrDTPyFqLzpHErwRjmZm62+n4EAj+Aa8qxKGjJnfHuN101dqk6Iod9 eXn+ucuTxH645TA0spl2r7uDx4h9/PXAwN8Jc4hMEsNr+qHd2sig6Glu4GnRGy2qR5 d+Itk5gBEK/8vm7YaPXmUHcOVwwgJuafAuRovjiH9KsTFVxaZISJF/WKEKhZOp7hX5 41xQtc16Y9EVw== From: Ivan Klokov To: CC: , , , , , , , , , , Ivan Klokov Subject: [RFC PATCH v6 2/2] tests/qtest: QTest example for RISC-V CSR register Date: Tue, 12 Nov 2024 17:38:26 +0300 Message-ID: <20241112143826.88130-3-ivan.klokov@syntacore.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112143826.88130-1-ivan.klokov@syntacore.com> References: <20241112143826.88130-1-ivan.klokov@syntacore.com> MIME-Version: 1.0 X-ClientProxiedBy: T-Exch-05.corp.yadro.com (172.17.10.109) To S-Exch-01.corp.yadro.com (10.78.5.241) Received-SPF: permerror client-ip=89.207.88.253; envelope-from=ivan.klokov@syntacore.com; helo=mta-03.yadro.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, T_SPF_PERMERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Added demo for reading CSR register from qtest environment. Signed-off-by: Ivan Klokov Reviewed-by: Fabiano Rosas --- tests/qtest/meson.build | 2 +- tests/qtest/riscv-csr-test.c | 56 ++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/riscv-csr-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index aa93e98418..4ec5b0afbb 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -271,7 +271,7 @@ qtests_s390x = \ qtests_riscv32 = \ (config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watchdog-test'] : []) -qtests_riscv64 = \ +qtests_riscv64 = ['riscv-csr-test'] + \ (unpack_edk2_blobs ? ['bios-tables-test'] : []) qos_test_ss = ss.source_set() diff --git a/tests/qtest/riscv-csr-test.c b/tests/qtest/riscv-csr-test.c new file mode 100644 index 0000000000..ff5c29e6c6 --- /dev/null +++ b/tests/qtest/riscv-csr-test.c @@ -0,0 +1,56 @@ +/* + * QTest testcase for RISC-V CSRs + * + * Copyright (c) 2024 Syntacore. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +#define CSR_MVENDORID 0xf11 +#define CSR_MISELECT 0x350 + +static void run_test_csr(void) +{ + uint64_t res; + uint64_t val = 0; + + QTestState *qts = qtest_init("-machine virt -cpu veyron-v1"); + + res = qtest_csr_call(qts, "get_csr", 0, CSR_MVENDORID, &val); + + g_assert_cmpint(res, ==, 0); + g_assert_cmpint(val, ==, 0x61f); + + val = 0xff; + res = qtest_csr_call(qts, "set_csr", 0, CSR_MISELECT, &val); + + g_assert_cmpint(res, ==, 0); + + val = 0; + res = qtest_csr_call(qts, "get_csr", 0, CSR_MISELECT, &val); + + g_assert_cmpint(res, ==, 0); + g_assert_cmpint(val, ==, 0xff); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/cpu/csr", run_test_csr); + + return g_test_run(); +}