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([2a00:1370:8180:90b:6639:2dc0:6fb5:8401]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ff59859fbesm2429411fa.75.2024.11.14.08.59.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:59:19 -0800 (PST) From: Pavel Skripkin To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Pavel Skripkin Subject: [PATCH 1/2] arm/ptw: factor out wxn logic to separate functions Date: Thu, 14 Nov 2024 19:59:15 +0300 Message-ID: <20241114165915.6569-1-paskripkin@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241114165900.6399-1-paskripkin@gmail.com> References: <20241114165900.6399-1-paskripkin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=paskripkin@gmail.com; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The next patch will add support for WXN for short descriptor format. To prevent code duplication, wxn logic was factored out to separate functions. Signed-off-by: Pavel Skripkin --- target/arm/ptw.c | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9849949508..2a3933adec 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1130,6 +1130,26 @@ do_fault: return true; } +static bool arm_has_wxn(CPUARMState *env) +{ + /* TODO have_wxn should be replaced with + * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) + * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE + * compatible processors have EL2, which is required for [U]WXN. + */ + return arm_feature(env, ARM_FEATURE_LPAE); +} + +static bool arm_wxn_enabled(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + return arm_has_wxn(env) && (regime_sctlr(env, mmu_idx) & SCTLR_WXN); +} + +static bool arm_uwxn_enabled(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + return arm_has_wxn(env) && (regime_sctlr(env, mmu_idx) & SCTLR_UWXN); +} + static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw, uint32_t address, MMUAccessType access_type, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) @@ -1370,8 +1390,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, ARMCPU *cpu = env_archcpu(env); bool is_user = regime_is_user(env, mmu_idx); int prot_rw, user_rw; - bool have_wxn; - int wxn = 0; + int wxn = arm_wxn_enabled(env, mmu_idx); assert(!regime_is_stage2(mmu_idx)); @@ -1432,18 +1451,6 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, g_assert_not_reached(); } } - - /* TODO have_wxn should be replaced with - * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) - * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE - * compatible processors have EL2, which is required for [U]WXN. - */ - have_wxn = arm_feature(env, ARM_FEATURE_LPAE); - - if (have_wxn) { - wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; - } - if (is_aa64) { if (regime_has_2_ranges(mmu_idx) && !is_user) { xn = pxn || (user_rw & PAGE_WRITE); @@ -1455,10 +1462,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, if (is_user) { xn = xn || !(user_rw & PAGE_READ); } else { - int uwxn = 0; - if (have_wxn) { - uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; - } + int uwxn = arm_uwxn_enabled(env, mmu_idx); + xn = xn || !(prot_rw & PAGE_READ) || pxn || (uwxn && (user_rw & PAGE_WRITE)); }