From patchwork Fri Nov 15 08:47:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13875990 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B45E174EE4 for ; Fri, 15 Nov 2024 08:48:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731660491; cv=none; b=culUjmVIzQD3ZgnXkWaNRwrR3prD07DavvgBrA4chCoCv+NMpQDZgXqhrKXIiYNAsBqTOe0fr3eS9wKvA/ZwV4R8SQ0L3R7VLmZFhcojlzmcMGeYC9CiVw50qijbr79hJuUHVEFutxvG+TShoW9VxXu1r26pK7ef3F9FU/GIlJY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731660491; c=relaxed/simple; bh=ZaQEFikrQCPkgci4zERm89mOSxRy4C3e1t5aLqXhiC4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kI5A3WUPOVfIVV7gXpIh4d50GQrRMo5eledS/aLo0YldYPxxMV0Gge1qxwHg4H2ivdtIZ9Or5GPVFbrJEQ4nxJes6rM+Nxim5PLQA0/OtWwldz19Vltg3ujitlDjPyeZvvksnzdryePPxGmvKy9LYUzYzXIgrhLc3bIRNNK8hpo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GXIgM08Y; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GXIgM08Y" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C4897C4CECF; Fri, 15 Nov 2024 08:48:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731660491; bh=ZaQEFikrQCPkgci4zERm89mOSxRy4C3e1t5aLqXhiC4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GXIgM08YqYmfH9YNimxk42qitR3pz5NXCgdOBWwa7q/uA/GLG8INamFWyx24/naTm 2+t87oo+6+porPdkkWCBxNYQug6dpSUI7YiHTKx+uM4s+itfxWnTfPIxBA5NQysQjt ybzfiFnF+8VdzUe91aU4GcKiJyRNgMDmJisI9YX5CcoF42g/XM5mrE2vPMsoSN4Qna AB0xPVmPzafwZW+NZgIQzfLWYYlD+k1jXE7JkfINWv68Ro+/E2cd0VOKSW33BgPMSJ UWf/lPGfK+4pPJLm4wOKTwqUOjA33+plJlnQ3gbr2YDc3xSY9tqohJCmcRYE9ER6Iv utCaZxgkBKzJQ== From: Niklas Cassel To: Jesper Nilsson , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Frank Li , Niklas Cassel , linux-arm-kernel@axis.com, linux-pci@vger.kernel.org Subject: [PATCH v2 1/3] PCI: artpec6: Implement dw_pcie_ep operation get_features Date: Fri, 15 Nov 2024 09:47:50 +0100 Message-ID: <20241115084749.1915915-6-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115084749.1915915-5-cassel@kernel.org> References: <20241115084749.1915915-5-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1598; i=cassel@kernel.org; h=from:subject; bh=ZaQEFikrQCPkgci4zERm89mOSxRy4C3e1t5aLqXhiC4=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLNuXY9y/y8uLZ869znp1dx/z+700mZ8flVVZXC327eT fxZpcfSOkpZGMS4GGTFFFl8f7jsL+52n3Jc8Y4NzBxWJpAhDFycAjCRKUYM/z17mFvCPFt9Ipez ln9YfU7d6MfuQ9M8ex941Lyv7GYVUWL4X3BZ57nJh6fZOxyepRWKqyazPeavraqtWi5UW1MoEd3 DAwA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA All non-DWC EPC drivers implement (struct pci_epc *)->ops->get_features(). All DWC EPC drivers implement (struct dw_pcie_ep *)->ops->get_features(), except for pcie-artpec6.c. epc_features has been required in pci-epf-test.c since commit 6613bc2301ba ("PCI: endpoint: Fix NULL pointer dereference for ->get_features()"). A follow-up commit will make further use of epc_features in EPC core code. Implement epc_features in the only EPC driver where it is currently not implemented. Signed-off-by: Niklas Cassel Reviewed-by: Frank Li Acked-by: Jesper Nilsson --- drivers/pci/controller/dwc/pcie-artpec6.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index f8e7283dacd47..234c8cbcae3af 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -369,9 +369,22 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } +static const struct pci_epc_features artpec6_pcie_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = false, +}; + +static const struct pci_epc_features * +artpec6_pcie_get_features(struct dw_pcie_ep *ep) +{ + return &artpec6_pcie_epc_features; +} + static const struct dw_pcie_ep_ops pcie_ep_ops = { .init = artpec6_pcie_ep_init, .raise_irq = artpec6_pcie_raise_irq, + .get_features = artpec6_pcie_get_features, }; static int artpec6_pcie_probe(struct platform_device *pdev) From patchwork Fri Nov 15 08:47:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13875991 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 276941885BF for ; Fri, 15 Nov 2024 08:48:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731660494; cv=none; b=ijGTs6XNyVTUROJGby/J+1d/SJg3t3SVZRIg8q0HnAKS2NgrixQS8FlFsyzyWR+QQV8qOmjrNPaXyXRWfREzJ9ZtLd4IXfqRaT4xmzRxCz1PLTefXHVwqsK3rJwFYrlhCDowL9vM2wHFFvaAbIP/+M1UZ+voxIo/zpv2T2T30mM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731660494; c=relaxed/simple; bh=SlN/xkv2h1nTy/SSDUnI5IQ0q1BJajoSiTu2IIeDb/0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=O4kJ9jaSfGQTy8no3ZE/dAF+0TOxnKN4dPHXGeUUJ1zmCkUwjnEYiwdHjVWv16Ap0qY+FeZF/guuVBoGyaSXCZLWKA9Y2umDcyuen1L8xmNWQIT5AN7oRrvz0yG2J1qh2+tE2nXGogp6w+uzGHhNVQC5cohgM1xYoBqkZmJkSTk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cmg3V4tH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cmg3V4tH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BD8D9C4CECF; Fri, 15 Nov 2024 08:48:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731660493; bh=SlN/xkv2h1nTy/SSDUnI5IQ0q1BJajoSiTu2IIeDb/0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cmg3V4tHc/MM7B6k6bqYBk+8iCLggOOhRTETWGFYI/FCUHu6hNwICxNqDACRMccZk SRag8OOMtQ8sxKL8nF6VURpO4/QUwkyAQJkTHM7f282TjepJ7QgywH5o101G/rDqtX ZvZuf3VIQmGioF3ztQnT/mhdq4QoiR93cZiyjJPcQnax85IAdTkbEviHn3+V0j0Geg HJGsHIszGhHKAyRjTKVoYjtWkcSBLFLn9rCPeBLm5HG6h0wWiXLZtJ84xHQPaZBl58 8L9oL+/b4Il/27zB3lyU8iK+ndX9Cb6OLN0MrhtCAFACbEy4OVlQJBzO3wVJjB3lyq 43UIriOaNl0Cg== From: Niklas Cassel To: Manivannan Sadhasivam , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: Damien Le Moal , Frank Li , Jesper Nilsson , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v2 2/3] PCI: endpoint: Add size check for fixed size BARs in pci_epc_set_bar() Date: Fri, 15 Nov 2024 09:47:51 +0100 Message-ID: <20241115084749.1915915-7-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115084749.1915915-5-cassel@kernel.org> References: <20241115084749.1915915-5-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1826; i=cassel@kernel.org; h=from:subject; bh=SlN/xkv2h1nTy/SSDUnI5IQ0q1BJajoSiTu2IIeDb/0=; b=kA0DAAoWyWQxo5nGTXIByyZiAGc3CrqhPVIdOid5GHu/GV/jqvrdHKpCjmasbS3a1Uu/s76wz oh1BAAWCgAdFiEETfhEv3OLR5THIdw8yWQxo5nGTXIFAmc3CroACgkQyWQxo5nGTXJHNQEAu20a en/pfGWCTId9Nr9Ftb4bruLKDJWVawO07skWjesBAJg9PAXbG/ZYxuWJMOVx5D2sCnMTXWtRJzc Jr2UCx/YO X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA A BAR of type BAR_FIXED has a fixed BAR size (the size cannot be changed). When using pci_epf_alloc_space() to allocate backing memory for a BAR, pci_epf_alloc_space() will always set the size to the fixed BAR size if the BAR type is BAR_FIXED (and will give an error if you the requested size is larger than the fixed BAR size). However, some drivers might not call pci_epf_alloc_space() before calling pci_epc_set_bar(), so add a check in pci_epc_set_bar() to ensure that an EPF driver cannot set a size different from the fixed BAR size, if the BAR type is BAR_FIXED. The pci_epc_function_is_valid() check is removed because this check is now done by pci_epc_get_features(). Signed-off-by: Niklas Cassel Reviewed-by: Frank Li --- drivers/pci/endpoint/pci-epc-core.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index bed7c7d1fe3c3..c69c133701c92 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -609,10 +609,17 @@ EXPORT_SYMBOL_GPL(pci_epc_clear_bar); int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar) { - int ret; + const struct pci_epc_features *epc_features; + enum pci_barno bar = epf_bar->barno; int flags = epf_bar->flags; + int ret; - if (!pci_epc_function_is_valid(epc, func_no, vfunc_no)) + epc_features = pci_epc_get_features(epc, func_no, vfunc_no); + if (!epc_features) + return -EINVAL; + + if (epc_features->bar[bar].type == BAR_FIXED && + (epc_features->bar[bar].fixed_size != epf_bar->size)) return -EINVAL; if ((epf_bar->barno == BAR_5 && flags & PCI_BASE_ADDRESS_MEM_TYPE_64) || From patchwork Fri Nov 15 08:47:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13875992 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4448418A6A3 for ; Fri, 15 Nov 2024 08:48:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731660497; cv=none; b=ArSOmW+c3bl/ItYGO+bUYY47ISgY2/aSnmOSPdW38hU6gYF6wFO6WZ5EFx6gSDpwLIDAAEnxW2PeW39lQwEXrdNjRBybqCjQjXbbEvoW8CoU1DxJSRYRTh0aRwb0zQr0p8Fwm7Rxc0xcgueWt6b71frF0swq+r2eKHvCLvmylig= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731660497; c=relaxed/simple; bh=DBoTMYzQHH1EDKTLCGDdsEXwGCMBH/6QSLBPWIIU0nY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kXFKiavX8RvRYcjQkEEroBkV+7sdAXI2fk8+taO4eqGziUsDPLcjo5ibcFQ7skLYur7MQFRC2HzW46itiPkx7x9jWakCaQKYgCKle6F1/mECehum55U+tm813yFVz4VCNocpLjCfRH5Y0Q41nnKg6Ou+PEjsDioj0Q9R7uA7Kxo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=S5YNoptY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="S5YNoptY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 89207C4CED0; Fri, 15 Nov 2024 08:48:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731660496; bh=DBoTMYzQHH1EDKTLCGDdsEXwGCMBH/6QSLBPWIIU0nY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S5YNoptY6RwoR9vjrDVy/wjzty1wfSGXVkM/czGm23YCMU4nac6i2szUo8Ap0aC1B Id34IKtTExhKo5jJVIU7en3Q3BBFjF9Crt19VPtQ1k8I8kf7rAaraGW+NBaloevufD 9Akh936HxSJ6x4lWN7iGklGhJgNTKb49C37PhH2tl8YKQuu7N31w5PI3tHf3jVUC0/ sqaX9bqPXg8SlM0YSlHB6WXJnB1xIaqsQOdQr5JyfrLKcoVqw0qmNX2/34TMzEtpOS 7LVJjpwiyp6rqRPf45RxOjRIavPpizkYI57lD/W6wtAhBHA1nvmMxLLj7Ic3kpw9dF bD78M4yUilQgA== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Frank Li , Jesper Nilsson , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v2 3/3] PCI: dwc: ep: Add 'address' alignment to 'size' check in dw_pcie_prog_ep_inbound_atu() Date: Fri, 15 Nov 2024 09:47:52 +0100 Message-ID: <20241115084749.1915915-8-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115084749.1915915-5-cassel@kernel.org> References: <20241115084749.1915915-5-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4258; i=cassel@kernel.org; h=from:subject; bh=DBoTMYzQHH1EDKTLCGDdsEXwGCMBH/6QSLBPWIIU0nY=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLNuXbncZ5zqD8S/1HPSNNyU7LOIusn/of0F2T8zrG+X fJEfJ5+RykLgxgXg6yYIovvD5f9xd3uU44r3rGBmcPKBDKEgYtTACYSu5WRYUJ5cZ3v9wNbrL1X a0Sk5/0+vHJyaKjXY95zOyK5mLa+dmT4Z7Cxev+bI39YJ3/0Ovi6dDL/wnKPOXIhbZs27Nf9o8N rwQEA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA dw_pcie_prog_ep_inbound_atu() is used to program an inbound iATU in "BAR Match Mode". A memory address returned by e.g. kmalloc() is guaranteed to have natural alignment (aligned to the size of the allocation). It is however not guaranteed that pci_epc_set_bar() (and thus dw_pcie_prog_ep_inbound_atu()) is supplied an address that has natural alignment. (An EPF driver can send in an arbitrary physical address to pci_epc_set_bar().) The DWC Databook description for the LWR_TARGET_RW and LWR_TARGET_HW fields in the IATU_LWR_TARGET_ADDR_OFF_INBOUND_i registers state that: "Field size depends on log2(BAR_MASK+1) in BAR match mode." I.e. only the upper bits are writable, and the number of writable bits is dependent on the configured BAR_MASK. Add a check to ensure that the physical address programmed in the iATU is aligned to the size of the BAR (BAR_MASK+1), as without this, we can get hard to debug errors, as we could write to bits that are read-only (without getting a write error), which could cause the iATU to end up redirecting to a physical address that is different from the address that we intended. Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-designware-ep.c | 8 +++++--- drivers/pci/controller/dwc/pcie-designware.c | 5 +++-- drivers/pci/controller/dwc/pcie-designware.h | 2 +- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 507e40bd18c8f..4ad6ebd2ea320 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -128,7 +128,8 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, } static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type, - dma_addr_t cpu_addr, enum pci_barno bar) + dma_addr_t cpu_addr, enum pci_barno bar, + size_t size) { int ret; u32 free_win; @@ -145,7 +146,7 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type, } ret = dw_pcie_prog_ep_inbound_atu(pci, func_no, free_win, type, - cpu_addr, bar); + cpu_addr, bar, size); if (ret < 0) { dev_err(pci->dev, "Failed to program IB window\n"); return ret; @@ -229,7 +230,8 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, else type = PCIE_ATU_TYPE_IO; - ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar); + ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar, + size); if (ret) return ret; diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 6d6cbc8b5b2c6..3c683b6119c39 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -597,11 +597,12 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, } int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, - int type, u64 cpu_addr, u8 bar) + int type, u64 cpu_addr, u8 bar, size_t size) { u32 retries, val; - if (!IS_ALIGNED(cpu_addr, pci->region_align)) + if (!IS_ALIGNED(cpu_addr, pci->region_align) || + !IS_ALIGNED(cpu_addr, size)) return -EINVAL; dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 347ab74ac35aa..fc08727116725 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -491,7 +491,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, u64 cpu_addr, u64 pci_addr, u64 size); int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, - int type, u64 cpu_addr, u8 bar); + int type, u64 cpu_addr, u8 bar, size_t size); void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index); void dw_pcie_setup(struct dw_pcie *pci); void dw_pcie_iatu_detect(struct dw_pcie *pci);