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Mon, 18 Nov 2024 02:18:27 -0600 From: Suraj Gupta To: , , , , , , , , CC: , , , , Subject: [PATCH net-next 1/2] dt-bindings: net: xlnx,axi-ethernet: Add bindings for AXI 2.5G MAC Date: Mon, 18 Nov 2024 13:48:21 +0530 Message-ID: <20241118081822.19383-2-suraj.gupta2@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241118081822.19383-1-suraj.gupta2@amd.com> References: <20241118081822.19383-1-suraj.gupta2@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD77:EE_|CH3PR12MB8187:EE_ X-MS-Office365-Filtering-Correlation-Id: 6b9e3946-b2c2-4ddb-c370-08dd07a99952 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: RVuHH0wKIgE0CIfdDkV6Ufki9A0MdAjpigv1hm7YJBW/3I1UVRs1y6dTSkTUpJE2sGTxqTSAp3ow6ozEtYhkOojnh0mSVP3n9qB84Vt4wdBjzhgI9gi5xTjvSC8c629W8uPTPb0TTKgNSQbZ/9EE3YubkaY00uo/XbLG0jEdZZDsJnyHi/wuMPODvv2O0Dvi22DXcqUEcxiNE+QqM5YrQHhNAxBzLQg7toqBbRwCzFf14IPj1VDMFXuy1kMG9hj8sAqvAdTY2UTzbgYlgSmibTzFGEXeOPmpVWI2PawJr+gXy5YTG2/7SVotLHay3FdUPDasWLArQcEl2pGNdIncXBPMjSHd1OlHHYr7mBdtjF4HXJ5InseLYaGdy9xI1GLTWvwX/XLCx8ZOWJQrTczwJnUUW8EhxBo4+bb90gtV8MN3GxomFlBf68sTDj6mlvLea/8IbSbeYVjlSU+KstXFJMHIvPgwIvK3F9ypHwM5CINIiZgosRuZCLpTua1qa16NjsQnPbygPy6AhI0bgDtGR8Vx08GkugBvxOjk1TzkUSW0EusFCkoIvCwkt+ANqjvw4fbQpOgvelJRFyEY66u3jVm4u9Do87Nkizf3X1Ju/0NXfx+WwO9XHzYEIqLMUm1tB97s+10Yk+MhuXLPdsMTry77iWk3908VQTA3tOP+y9JmrjisEiqitH2RJyhkQ4Oxo+Wp8PyWtSwlUZlkfJqCUWHIHaMpf9SiqFstz2d5kZuzl9El/pC4HpMhA4/dXwXL6mxdXV4hWbO9iZqcls3q1DwqUuX1kWSw3Fki3q6SqPerKxjBJICwoMOwfTqdsUmryLppz7UJGnyqSjU3rixsrMCVjvNSYYklSXKWQySaC/GfU+/zkeeT56/PNsoO0/iCzI8mZ+lSsO0s6mgAhvkEpbv5ciimgk+Ud62WHYrBlSBRov/xHGkvUzpHyYsz7v013MoTIXuqvpFS4UgRhGjixeTuBrrrTp+yONU5AfEs13OTyxhWkkOj4mYLKh6gP5GpxKJgyLtafv1OCe2XV3daDpn2oCS/tLxfPQijp/Ca8xpGdtC2Zk5iTwzkg9z0DUC/whj3IxdMsRGmUGLEbJrLh2Va4qTYIoYhigeDzvMkwFGNJfPdBsPo7LixQnTjUA/bC5PwUv94yi5HvwzXaLtZDU1n7ow1yo+q7en9fFrRCXXF7QicugDK3baiZ1b75SUJB9bRQFExeDC2ZHo/qvyCJqquDph+ks4dyhjpIx9ucyTVCOSfcmNFZht34E4xvkod7o77WB9ODhDX8mtcNvRQztBZaPd5IZGVtIIDnT0+teswg9SUaxoLvhR7uVm9DHCFQN1+/hx11YJUpI8pnEU+CrV6iU8s9rpL/qOUWhk33qWjJAjX83PQHhK5BX6GYQYEqz3xrk2K4UVTZYqMyAQjag== X-Forefront-Antispam-Report: CIP:165.204.84.12;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:atlvpn-bp.amd.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2024 08:18:35.8902 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b9e3946-b2c2-4ddb-c370-08dd07a99952 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD77.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8187 X-Patchwork-Delegate: kuba@kernel.org AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed" property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP. max-speed is made a required property, and it breaks DT ABI but driver implementation ensures backward compatibility and assumes 1G when this property is absent. Modify existing bindings description for 2.5G MAC. Signed-off-by: Suraj Gupta --- .../bindings/net/xlnx,axi-ethernet.yaml | 44 +++++++++++++++++-- 1 file changed, 40 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml index fb02e579463c..69e84e2e2b63 100644 --- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml +++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml @@ -9,10 +9,12 @@ title: AXI 1G/2.5G Ethernet Subsystem description: | Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core provides connectivity to an external ethernet PHY supporting different - interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two + interfaces: MII, GMII, RGMII, SGMII, 1000BaseX and 2500BaseX. It also includes two segments of memory for buffering TX and RX, as well as the capability of offloading TX/RX checksum calculation off the processor. + AXI 2.5G MAC is incremental speed upgrade of AXI 1G and supports 2.5G speed. + Management configuration is done through the AXI interface, while payload is sent and received through means of an AXI DMA controller. This driver includes the DMA driver code, so this driver is incompatible with AXI DMA @@ -62,6 +64,7 @@ properties: - rgmii - sgmii - 1000base-x + - 2500base-x xlnx,phy-type: description: @@ -118,9 +121,9 @@ properties: type: object pcs-handle: - description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X - modes, where "pcs-handle" should be used to point to the PCS/PMA PHY, - and "phy-handle" should point to an external PHY if exists. + description: Phandle to the internal PCS/PMA PHY in SGMII or 1000base-x/ + 2500base-x modes, where "pcs-handle" should be used to point to the + PCS/PMA PHY, and "phy-handle" should point to an external PHY if exists. maxItems: 1 dmas: @@ -137,12 +140,17 @@ properties: minItems: 2 maxItems: 32 + max-speed: + description: + Indicates max MAC rate. 1G and 2.5G MACs of AXI 1G/2.5G IP are distinguished using it. + required: - compatible - interrupts - reg - xlnx,rxmem - phy-handle + - max-speed allOf: - $ref: /schemas/net/ethernet-controller.yaml# @@ -164,6 +172,7 @@ examples: xlnx,rxmem = <0x800>; xlnx,txcsum = <0x2>; phy-handle = <&phy0>; + max-speed = <1000>; mdio { #address-cells = <1>; @@ -188,6 +197,7 @@ examples: xlnx,txcsum = <0x2>; phy-handle = <&phy1>; axistream-connected = <&dma>; + max-speed = <1000>; mdio { #address-cells = <1>; @@ -198,3 +208,29 @@ examples: }; }; }; + +# AXI 2.5G MAC + - | + axi_ethernet_eth2: ethernet@a4000000 { + compatible = "xlnx,axi-ethernet-1.00.a"; + interrupts = <0>; + clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk"; + clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>; + phy-mode = "2500base-x"; + reg = <0x40000000 0x40000>; + xlnx,rxcsum = <0x2>; + xlnx,rxmem = <0x800>; + xlnx,txcsum = <0x2>; + phy-handle = <&phy1>; + axistream-connected = <&dma>; + max-speed = <2500>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy2: ethernet-phy@1 { + device_type = "ethernet-phy"; + reg = <1>; + }; + }; + }; From patchwork Mon Nov 18 08:18:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Suraj" X-Patchwork-Id: 13878275 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2056.outbound.protection.outlook.com [40.107.244.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D627A193435; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2024 08:26:52.0575 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 32d0a2d1-2591-4f5e-44ab-08dd07aac112 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017099.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9085 X-Patchwork-Delegate: kuba@kernel.org Add AXI 2.5G MAC support, which is an incremental speed upgrade of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP. If max-speed property is missing, 1G is assumed to support backward compatibility. Co-developed-by: Harini Katakam Signed-off-by: Harini Katakam Signed-off-by: Suraj Gupta Reviewed-by: Radhey Shyam Pandey --- drivers/net/ethernet/xilinx/xilinx_axienet.h | 4 +++- .../net/ethernet/xilinx/xilinx_axienet_main.c | 24 +++++++++++++++---- 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h index d64b8abcf018..ebad1c147aa2 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -274,7 +274,7 @@ #define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */ #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ -#define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */ +#define XAE_EMMC_LINKSPD_1000_2500 0x80000000 /* Link Speed mask for 1000 or 2500 Mbit */ /* Bit masks for Axi Ethernet PHYC register */ #define XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/ @@ -542,6 +542,7 @@ struct skbuf_dma_descriptor { * @tx_ring_tail: TX skb ring buffer tail index. * @rx_ring_head: RX skb ring buffer head index. * @rx_ring_tail: RX skb ring buffer tail index. + * @max_speed: Maximum possible MAC speed. */ struct axienet_local { struct net_device *ndev; @@ -620,6 +621,7 @@ struct axienet_local { int tx_ring_tail; int rx_ring_head; int rx_ring_tail; + u32 max_speed; }; /** diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index 273ec5f70005..52a3703bd604 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -2388,6 +2388,7 @@ static struct phylink_pcs *axienet_mac_select_pcs(struct phylink_config *config, struct axienet_local *lp = netdev_priv(ndev); if (interface == PHY_INTERFACE_MODE_1000BASEX || + interface == PHY_INTERFACE_MODE_2500BASEX || interface == PHY_INTERFACE_MODE_SGMII) return &lp->pcs; @@ -2421,8 +2422,9 @@ static void axienet_mac_link_up(struct phylink_config *config, emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK; switch (speed) { + case SPEED_2500: case SPEED_1000: - emmc_reg |= XAE_EMMC_LINKSPD_1000; + emmc_reg |= XAE_EMMC_LINKSPD_1000_2500; break; case SPEED_100: emmc_reg |= XAE_EMMC_LINKSPD_100; @@ -2432,7 +2434,7 @@ static void axienet_mac_link_up(struct phylink_config *config, break; default: dev_err(&ndev->dev, - "Speed other than 10, 100 or 1Gbps is not supported\n"); + "Speed other than 10, 100, 1Gbps or 2.5Gbps is not supported\n"); break; } @@ -2681,6 +2683,12 @@ static int axienet_probe(struct platform_device *pdev) lp->switch_x_sgmii = of_property_read_bool(pdev->dev.of_node, "xlnx,switch-x-sgmii"); + ret = of_property_read_u32(pdev->dev.of_node, "max-speed", &lp->max_speed); + if (ret) { + lp->max_speed = SPEED_1000; + netdev_warn(ndev, "Please upgrade your device tree to use max-speed\n"); + } + /* Start with the proprietary, and broken phy_type */ ret = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &value); if (!ret) { @@ -2854,7 +2862,8 @@ static int axienet_probe(struct platform_device *pdev) "error registering MDIO bus: %d\n", ret); if (lp->phy_mode == PHY_INTERFACE_MODE_SGMII || - lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX) { + lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX || + lp->phy_mode == PHY_INTERFACE_MODE_2500BASEX) { np = of_parse_phandle(pdev->dev.of_node, "pcs-handle", 0); if (!np) { /* Deprecated: Always use "pcs-handle" for pcs_phy. @@ -2882,8 +2891,13 @@ static int axienet_probe(struct platform_device *pdev) lp->phylink_config.dev = &ndev->dev; lp->phylink_config.type = PHYLINK_NETDEV; - lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | - MAC_10FD | MAC_100FD | MAC_1000FD; + lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE; + + /* Set MAC capabilities based on MAC type */ + if (lp->max_speed == SPEED_1000) + lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD | MAC_1000FD; + else + lp->phylink_config.mac_capabilities |= MAC_2500FD; __set_bit(lp->phy_mode, lp->phylink_config.supported_interfaces); if (lp->switch_x_sgmii) {