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Wed, 20 Nov 2024 07:04:04 -0500 (EST) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , linux-renesas-soc@vger.kernel.org, linux-pm@vger.kernel.org Cc: =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH v2 1/2] thermal: rcar_gen3: Use lowercase hex constants Date: Wed, 20 Nov 2024 13:03:35 +0100 Message-ID: <20241120120336.1063979-2-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241120120336.1063979-1-niklas.soderlund+renesas@ragnatech.se> References: <20241120120336.1063979-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The style of the driver is to use lowercase hex constants, correct the few outlines. Signed-off-by: Niklas Söderlund --- * Changes since v1 - Update a few more defines not related to the fuses missed and pointed out by Geert, thanks! --- drivers/thermal/renesas/rcar_gen3_thermal.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/thermal/renesas/rcar_gen3_thermal.c b/drivers/thermal/renesas/rcar_gen3_thermal.c index 810f86677461..95b636f79e07 100644 --- a/drivers/thermal/renesas/rcar_gen3_thermal.c +++ b/drivers/thermal/renesas/rcar_gen3_thermal.c @@ -21,11 +21,11 @@ /* Register offsets */ #define REG_GEN3_IRQSTR 0x04 #define REG_GEN3_IRQMSK 0x08 -#define REG_GEN3_IRQCTL 0x0C +#define REG_GEN3_IRQCTL 0x0c #define REG_GEN3_IRQEN 0x10 #define REG_GEN3_IRQTEMP1 0x14 #define REG_GEN3_IRQTEMP2 0x18 -#define REG_GEN3_IRQTEMP3 0x1C +#define REG_GEN3_IRQTEMP3 0x1c #define REG_GEN3_THCTR 0x20 #define REG_GEN3_TEMP 0x28 #define REG_GEN3_THCODE1 0x50 @@ -38,9 +38,9 @@ #define REG_GEN4_THSFMON00 0x180 #define REG_GEN4_THSFMON01 0x184 #define REG_GEN4_THSFMON02 0x188 -#define REG_GEN4_THSFMON15 0x1BC -#define REG_GEN4_THSFMON16 0x1C0 -#define REG_GEN4_THSFMON17 0x1C4 +#define REG_GEN4_THSFMON15 0x1bc +#define REG_GEN4_THSFMON16 0x1c0 +#define REG_GEN4_THSFMON17 0x1c4 /* IRQ{STR,MSK,EN} bits */ #define IRQ_TEMP1 BIT(0) @@ -57,11 +57,11 @@ /* THSCP bits */ #define THSCP_COR_PARA_VLD (BIT(15) | BIT(14)) -#define CTEMP_MASK 0xFFF +#define CTEMP_MASK 0xfff #define MCELSIUS(temp) ((temp) * 1000) -#define GEN3_FUSE_MASK 0xFFF -#define GEN4_FUSE_MASK 0xFFF +#define GEN3_FUSE_MASK 0xfff +#define GEN4_FUSE_MASK 0xfff #define TSC_MAX_NUM 5 From patchwork Wed Nov 20 12:03:36 2024 Content-Type: text/plain; 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Wed, 20 Nov 2024 07:04:08 -0500 (EST) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , linux-renesas-soc@vger.kernel.org, linux-pm@vger.kernel.org Cc: =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH v2 2/2] thermal: rcar_gen3: Reuse logic to read fuses on Gen3 and Gen4 Date: Wed, 20 Nov 2024 13:03:36 +0100 Message-ID: <20241120120336.1063979-3-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241120120336.1063979-1-niklas.soderlund+renesas@ragnatech.se> References: <20241120120336.1063979-1-niklas.soderlund+renesas@ragnatech.se> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The hardware calibration is fused on some, but not all, Gen3 and Gen4 boards. The calibrations values are the same on both generations but located at different register offsets. Instead of having duplicated logic to read the and store the values create a helper function to do the reading and just feed it with the correct register addresses for each generation, Signed-off-by: Niklas Söderlund --- drivers/thermal/renesas/rcar_gen3_thermal.c | 79 ++++++++------------- 1 file changed, 31 insertions(+), 48 deletions(-) diff --git a/drivers/thermal/renesas/rcar_gen3_thermal.c b/drivers/thermal/renesas/rcar_gen3_thermal.c index 95b636f79e07..5f54e235da2f 100644 --- a/drivers/thermal/renesas/rcar_gen3_thermal.c +++ b/drivers/thermal/renesas/rcar_gen3_thermal.c @@ -253,60 +253,43 @@ static irqreturn_t rcar_gen3_thermal_irq(int irq, void *data) return IRQ_HANDLED; } +static void rcar_gen3_thermal_fetch_fuses(struct rcar_gen3_thermal_priv *priv, + u32 ptat0, u32 ptat1, u32 ptat2, + u32 thcode0, u32 thcode1, u32 thcode2, + u32 mask) +{ + /* + * Set the pseudo calibration points with fused values. + * PTAT is shared between all TSCs but only fused for the first + * TSC while THCODEs are fused for each TSC. + */ + priv->ptat[0] = rcar_gen3_thermal_read(priv->tscs[0], ptat0) & mask; + priv->ptat[1] = rcar_gen3_thermal_read(priv->tscs[0], ptat1) & mask; + priv->ptat[2] = rcar_gen3_thermal_read(priv->tscs[0], ptat2) & mask; + + for (unsigned int i = 0; i < priv->num_tscs; i++) { + struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i]; + + tsc->thcode[0] = rcar_gen3_thermal_read(tsc, thcode0) & mask; + tsc->thcode[1] = rcar_gen3_thermal_read(tsc, thcode1) & mask; + tsc->thcode[2] = rcar_gen3_thermal_read(tsc, thcode2) & mask; + } +} + static void rcar_gen3_thermal_read_fuses_gen3(struct rcar_gen3_thermal_priv *priv) { - unsigned int i; - - /* - * Set the pseudo calibration points with fused values. - * PTAT is shared between all TSCs but only fused for the first - * TSC while THCODEs are fused for each TSC. - */ - priv->ptat[0] = rcar_gen3_thermal_read(priv->tscs[0], REG_GEN3_PTAT1) & - GEN3_FUSE_MASK; - priv->ptat[1] = rcar_gen3_thermal_read(priv->tscs[0], REG_GEN3_PTAT2) & - GEN3_FUSE_MASK; - priv->ptat[2] = rcar_gen3_thermal_read(priv->tscs[0], REG_GEN3_PTAT3) & - GEN3_FUSE_MASK; - - for (i = 0; i < priv->num_tscs; i++) { - struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i]; - - tsc->thcode[0] = rcar_gen3_thermal_read(tsc, REG_GEN3_THCODE1) & - GEN3_FUSE_MASK; - tsc->thcode[1] = rcar_gen3_thermal_read(tsc, REG_GEN3_THCODE2) & - GEN3_FUSE_MASK; - tsc->thcode[2] = rcar_gen3_thermal_read(tsc, REG_GEN3_THCODE3) & - GEN3_FUSE_MASK; - } + rcar_gen3_thermal_fetch_fuses(priv, + REG_GEN3_PTAT1, REG_GEN3_PTAT2, REG_GEN3_PTAT3, + REG_GEN3_THCODE1, REG_GEN3_THCODE2, REG_GEN3_THCODE3, + GEN3_FUSE_MASK); } static void rcar_gen3_thermal_read_fuses_gen4(struct rcar_gen3_thermal_priv *priv) { - unsigned int i; - - /* - * Set the pseudo calibration points with fused values. - * PTAT is shared between all TSCs but only fused for the first - * TSC while THCODEs are fused for each TSC. - */ - priv->ptat[0] = rcar_gen3_thermal_read(priv->tscs[0], REG_GEN4_THSFMON16) & - GEN4_FUSE_MASK; - priv->ptat[1] = rcar_gen3_thermal_read(priv->tscs[0], REG_GEN4_THSFMON17) & - GEN4_FUSE_MASK; - priv->ptat[2] = rcar_gen3_thermal_read(priv->tscs[0], REG_GEN4_THSFMON15) & - GEN4_FUSE_MASK; - - for (i = 0; i < priv->num_tscs; i++) { - struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i]; - - tsc->thcode[0] = rcar_gen3_thermal_read(tsc, REG_GEN4_THSFMON01) & - GEN4_FUSE_MASK; - tsc->thcode[1] = rcar_gen3_thermal_read(tsc, REG_GEN4_THSFMON02) & - GEN4_FUSE_MASK; - tsc->thcode[2] = rcar_gen3_thermal_read(tsc, REG_GEN4_THSFMON00) & - GEN4_FUSE_MASK; - } + rcar_gen3_thermal_fetch_fuses(priv, + REG_GEN4_THSFMON16, REG_GEN4_THSFMON17, REG_GEN4_THSFMON15, + REG_GEN4_THSFMON01, REG_GEN4_THSFMON02, REG_GEN4_THSFMON00, + GEN4_FUSE_MASK); } static bool rcar_gen3_thermal_read_fuses(struct rcar_gen3_thermal_priv *priv)