From patchwork Thu Nov 21 17:41:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 13882235 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC44E1A01CD; Thu, 21 Nov 2024 17:41:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732210907; cv=none; b=IiMrzIsU3vZn3BXGQOjyJ6nrOC+EQqxpTAGk90NM9opqe20jfBYxv7Z0X+A0eRBdtq3k61n/bOGDyP9injBMPbrHhsoh+S0+nzvjI/StEWuzNFnkw86ViHZUIjg1xfv45iQdyjtHTfyN81BKyfo7ZabKm4u2KOY1qv44Tlwz1lM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732210907; c=relaxed/simple; bh=vZMGVlzPw/7v2ZFp7bgQck20bK9sg0BZJrP7XmQ9X5Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rM/O5o+K54FzY/SkEiLV59RhpjwUKSyvb6AmURZh84kHjoYksQJbvTQ3UCGy328LHwfllt2rJhD50GI98cHfHgDOQs1ZsGouxaBXi+m/7VwdOJrrBKgQGLcr0XH0SiW40W1vOnwjGsfkuzXe+iPZIM4Adf2/PitJCn4Uhe/ek1I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=KwoxBPvC; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="KwoxBPvC" Received: by mail.gandi.net (Postfix) with ESMTPSA id B06972000C; Thu, 21 Nov 2024 17:41:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1732210897; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HNSGIUDWKtHK2V3krzyRKB3CsE+LudVK/AtAMHaXQPM=; b=KwoxBPvC0Zrft6aR7f763oIRvd7CMINTpkCKQP/bHCyzyolyQ5scMkb+NAdB7DBIqOVf3u Xlz3JO4Wu29Ce5OBWtm1j8aMzum1QQQ6tmCz2blMejXb6VzQH8b5aVoFgeLG2OtB4DAYTv b4ldBapMLak5ZXgUDWFzMm6rhwlllZ0GY1J7NOF/ONOOOX5auLPJ0oY7llWLk6kC6V8KSc 8FQ5aUTIt8ouNKfTUAjx6M6otK8zTYlRYFrqVHYhu1UF4Oe7/Zkr717Dp1YXjZOQ8dH/kD 3jbvJcIzy3wSucOaOWnK/ywWQ5pJcTI74TZ+u4DV9UN+JGOKredQvaCh6C0F/A== From: Miquel Raynal Date: Thu, 21 Nov 2024 18:41:11 +0100 Subject: [PATCH 1/5] clk: imx: clk-imx8mp: Allow LDB serializer clock reconfigure parent rate Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241121-ge-ian-debug-imx8-clk-tree-v1-1-0f1b722588fe@bootlin.com> References: <20241121-ge-ian-debug-imx8-clk-tree-v1-0-0f1b722588fe@bootlin.com> In-Reply-To: <20241121-ge-ian-debug-imx8-clk-tree-v1-0-0f1b722588fe@bootlin.com> To: Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Ying Liu , Marek Vasut Cc: Laurent Pinchart , linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Abel Vesa , Herve Codina , Luca Ceresoli , Thomas Petazzoni , Ian Ray , Miquel Raynal X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com From: Marek Vasut The media_ldb_root_clk supply LDB serializer. These clock are usually shared with the LCDIFv3 pixel clock and supplied by the Video PLL on i.MX8MP, but the LDB clock run at either x7 or x14 rate of the LCDIFv3 pixel clock. Allow the LDB to reconfigure Video PLL as needed, as that results in accurate serializer clock. Signed-off-by: Marek Vasut Reviewed-by: Abel Vesa Signed-off-by: Miquel Raynal --- drivers/clk/imx/clk-imx8mp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 516dbd170c8a356f293621b371b9ef9b9bec90a4..2e61d340b8ab7f626155563c46e0d4142caf3fa9 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -611,7 +611,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] = imx8m_clk_hw_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80); hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite_bus_flags("media_disp1_pix", imx8mp_media_disp_pix_sels, ccm_base + 0xbe00, CLK_SET_RATE_PARENT); hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80); - hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", imx8mp_media_ldb_sels, ccm_base + 0xbf00); + hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite_bus_flags("media_ldb", imx8mp_media_ldb_sels, ccm_base + 0xbf00, CLK_SET_RATE_PARENT); hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base + 0xbf80); hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = imx8m_clk_hw_composite("media_mipi_test_byte", imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100); hws[IMX8MP_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", imx8mp_ecspi3_sels, ccm_base + 0xc180); From patchwork Thu Nov 21 17:41:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 13882236 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FBC01B0F0C; Thu, 21 Nov 2024 17:41:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="RWoZGU5f" Received: by mail.gandi.net (Postfix) with ESMTPSA id D004620010; Thu, 21 Nov 2024 17:41:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1732210898; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZKTy8XWO2qgziAQ1aV4BgRlmD2JBLSeCDp8Nwyzn3qA=; b=RWoZGU5fJqpTbXKi5tH+r+d1vmD3mjfhf6zksxyRpNa2uNYJqMxwWp/aivD8zuRYvbeVR6 HaBQw6HXteslHcYc5HeiakgI80i3lGL4NvA0dVR49fCXFMkNaqK2+x1vIMmPZyaCPYDUea EiEcuu2XP80YdISzxDRiKnFalLoPHLRrs+BPSDuUxPflkp3mdDL0rueP/9UY9TKAsH6hhh T3NGDcPuhqZ9mQTaTLd35fNleQXRbFnRYg12+0mlyMKpkFqtd7yXICaPQg7eEkmXvMJj/b 7qTCJNRPyQTqux8xlrxIUqgH9YKhnerMsJ+IDdSQuq/HEUrdwwCHfsYqkgdD3Q== From: Miquel Raynal Date: Thu, 21 Nov 2024 18:41:12 +0100 Subject: [PATCH 2/5] clk: Add a helper to determine a clock rate Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241121-ge-ian-debug-imx8-clk-tree-v1-2-0f1b722588fe@bootlin.com> References: <20241121-ge-ian-debug-imx8-clk-tree-v1-0-0f1b722588fe@bootlin.com> In-Reply-To: <20241121-ge-ian-debug-imx8-clk-tree-v1-0-0f1b722588fe@bootlin.com> To: Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Ying Liu , Marek Vasut Cc: Laurent Pinchart , linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Abel Vesa , Herve Codina , Luca Ceresoli , Thomas Petazzoni , Ian Ray , Miquel Raynal X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com In the context of the clock core, "determine" means we calculate a possible clock rate based on its hardware capabilities and its current upstream parent frequency. This is opposed to "round" which tries to find the best parent and best rate and "recalc" which is about finding the next output clock based on a parent frequency change. The prototype is based on clk_recalc() which does exactly the same for the "recalc" situation. Signed-off-by: Miquel Raynal --- drivers/clk/clk.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index d02451f951cf057d068f980d985c95deb861a2d9..f171539bbb842f57698249a475c62f3f5719ccd1 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1927,6 +1927,18 @@ long clk_get_accuracy(struct clk *clk) } EXPORT_SYMBOL_GPL(clk_get_accuracy); +__maybe_unused +static unsigned long clk_determine(struct clk_core *core, unsigned long rate) +{ + struct clk_rate_request req = {}; + + clk_hw_init_rate_request(core->hw, &req, rate); + if (__clk_determine_rate(core->hw, &req)) + return 0; + + return req.rate; +} + static unsigned long clk_recalc(struct clk_core *core, unsigned long parent_rate) { From patchwork Thu Nov 21 17:41:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 13882237 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69E081B5820; Thu, 21 Nov 2024 17:41:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732210909; cv=none; b=UXWyl1Q3KHvsAM8jkbA4AQXhWFQmXmb3yMTOHkZSAfd+vZYF0EoL9RieaejnSKEoJ1hD5jK1sS9hRMT4r8sxbI9uyXvOH7LxiLebxpivrUgrHpC6cKDJ2htej88Bn1aLirQvOU9kzu/2kakk/+4YI6YCPJUOFt8Z/jhPCmb4uE0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732210909; c=relaxed/simple; bh=r+RIGjSXhFIM6oHafCjRoKK3MZLKYmcB9BrO3X79kSI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pae+G3FXd8A9F6nPoPa8T9a/MWEhYhAbSNjx5L2X+uDpZ/EmA0HDEu8bNFMIj0tkcBNP+yTtYTDGjZkEjLkYltqYfhrmYJvaV52U1IegeIYhp/svWM4UWEVz5pkdnroFaNb2vIf5XTLl9K9u1Xqz4agPyojatZyZaIx7nfYnvlA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Y85agxXt; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Y85agxXt" Received: by mail.gandi.net (Postfix) with ESMTPSA id 017F020002; Thu, 21 Nov 2024 17:41:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1732210900; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=g9fPs0nLthnmbo8a6LrEY10rX186VeNy9SlwRtv5peU=; b=Y85agxXtRhcAxZzQaTYfg/Fqro4DYf58mDGp1y2m/tvKQcRgdR/TTvqBShF6rleawyFLVC IL3KSEBqc9lFFlv8XSTrCWVE7Ya1BYJoyqXcfSCbfjV69dQjmX/PdKTVyRgr5zJeu7hK6G 8QIJEAuv3qhpsSXUiv6lQXu86m7nOjj0jX/WYxZmuwglh7Xnm6RtoJrgjNEVary+Nfx2Q6 D/XqaeYScbjs1uQ4vuWWzrVr1nPrz+Ys1W03dt9oE7tWDDdnFIpjlUXRQC1HDQ9GUDNqxZ iK2+XlZEwiGBprWAfMHfqxvln9cn4lB0BmnJ+r6gkj4PK7WuOPUASa/oLCCeUQ== From: Miquel Raynal Date: Thu, 21 Nov 2024 18:41:13 +0100 Subject: [PATCH 3/5] clk: Split clk_calc_subtree() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241121-ge-ian-debug-imx8-clk-tree-v1-3-0f1b722588fe@bootlin.com> References: <20241121-ge-ian-debug-imx8-clk-tree-v1-0-0f1b722588fe@bootlin.com> In-Reply-To: <20241121-ge-ian-debug-imx8-clk-tree-v1-0-0f1b722588fe@bootlin.com> To: Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Ying Liu , Marek Vasut Cc: Laurent Pinchart , linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Abel Vesa , Herve Codina , Luca Ceresoli , Thomas Petazzoni , Ian Ray , Miquel Raynal X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com This helper does two different things: - it calculates the new clock frequency - as part of this task, it also handles a possible parent change - it walks the clock subtree to further update frequencies as well (but the parent changes are no longer relevant there). In order to ease the understanding of the next step, let's split this helper into: - clk_calc_core_and_subtree() which performs the top clock update (with the parents handling) and then calls... - clk_calc_subtree() (which calls itself recursively) in order to perform the subtree updates. There is no functional change intended. Signed-off-by: Miquel Raynal --- drivers/clk/clk.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index f171539bbb842f57698249a475c62f3f5719ccd1..adfc5bfb93b5a65b6f58c52ca2c432d651f7dd7d 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -2268,8 +2268,18 @@ static int __clk_speculate_rates(struct clk_core *core, return ret; } -static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate, - struct clk_core *new_parent, u8 p_index) +static void clk_calc_subtree(struct clk_core *core) +{ + struct clk_core *child; + + core->new_rate = clk_recalc(core, core->parent->new_rate); + + hlist_for_each_entry(child, &core->children, child_node) + clk_calc_subtree(child); +} + +static void clk_calc_core_and_subtree(struct clk_core *core, unsigned long new_rate, + struct clk_core *new_parent, u8 p_index) { struct clk_core *child; @@ -2281,10 +2291,8 @@ static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate, if (new_parent && new_parent != core->parent) new_parent->new_child = core; - hlist_for_each_entry(child, &core->children, child_node) { - child->new_rate = clk_recalc(child, new_rate); - clk_calc_subtree(child, child->new_rate, NULL, 0); - } + hlist_for_each_entry(child, &core->children, child_node) + clk_calc_subtree(child); } /* @@ -2368,7 +2376,7 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core, top = clk_calc_new_rates(parent, best_parent_rate); out: - clk_calc_subtree(core, new_rate, parent, p_index); + clk_calc_core_and_subtree(core, new_rate, parent, p_index); return top; } From patchwork Thu Nov 21 17:41:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 13882238 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49B711BCA0F; Thu, 21 Nov 2024 17:41:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="gpQVV3Y5" Received: by mail.gandi.net (Postfix) with ESMTPSA id 268742000E; Thu, 21 Nov 2024 17:41:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1732210901; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6QcSacwVpu2OIjtCo7echKG6f3TnQvVOnEK3B7CH3u8=; b=gpQVV3Y5DwAdSa+7rGceOvI9ECqAtPMyocg8KvRcQPA8yGF20p1h20yVBtzR84fG8ClwUh 0I4xgOyZMm6GQNzGYZogpGCjCs6YJ8wDYl1UnCOMIDzL65A/s9ERj1nLXR45Q0V2uJfrAt CtdeJOAkuPUB4Uowb5Ow9nKWuBFV27oBJR+DXn1SfbAo8FxORpcH09MpzLBA54AM/gASvc +KIFiwh7QyRlWMBvcAvrDct8SRSN+sKjhq2ToA5w9FFbl9AnVm4I+FVUcKV7b461/kZYdw QOhIYphFMsAMNeSbRwnonySF58MMAvPn9qIPUSUHQaWGCRpXhJSkj/hY5pZQ1A== From: Miquel Raynal Date: Thu, 21 Nov 2024 18:41:14 +0100 Subject: [PATCH 4/5] clk: Add flag to prevent frequency changes when walking subtrees Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241121-ge-ian-debug-imx8-clk-tree-v1-4-0f1b722588fe@bootlin.com> References: <20241121-ge-ian-debug-imx8-clk-tree-v1-0-0f1b722588fe@bootlin.com> In-Reply-To: <20241121-ge-ian-debug-imx8-clk-tree-v1-0-0f1b722588fe@bootlin.com> To: Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Ying Liu , Marek Vasut Cc: Laurent Pinchart , linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Abel Vesa , Herve Codina , Luca Ceresoli , Thomas Petazzoni , Ian Ray , Miquel Raynal X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com There are mainly two ways to change a clock frequency. The active way requires calling ->set_rate() in order to ask "on purpose" for a frequency change. Otherwise, a clock can passively see its frequency being updated depending on upstream clock frequency changes. In most cases it is fine to just accept the new upstream frequency - which by definition will have an impact on downstream frequencies if we do not recalculate internal divisors. But there are cases where, upon an upstream frequency change, we would like to maintain a specific rate. As an example, on iMX8MP the video pipeline clocks are looking like this: video_pll1 video_pll1_bypass video_pll1_out media_ldb media_ldb_root_clk media_disp2_pix media_disp2_pix_root_clk media_disp1_pix media_disp1_pix_root_clk media_ldb, media_disp2_pix and media_disp1_pix are simple divisors from which we might require 2 or 3 different rates, whereas video_pll1 is a very configurable PLL which can achieve almost any frequency. There are however relationships between them, typically the ldb clock must be 3.5 or 7 times higher than the media_disp* clocks. Currently, if eg. media_disp2_pix is set to 71900000Hz, when media_ldb is (later) set to 503300000Hz, media_disp2_pix is updated to 503300000Hz as well, which clearly does not make sense. We want it to stay at 71900000Hz during the subtree walk. Achieving this is the purpose of the new clock flag: CLK_NO_RATE_CHANGE_DURING_PROPAGATION Please note, if the kernel was setting the ldb clock before a pixel clock, the result would be different, and this is also what this patch is trying to solve. Signed-off-by: Miquel Raynal --- In all cases, the LDB must be aware of the device configuration, and ask for a clever frequency, we will never cope with slightly aware drivers when addressing this kind of subtle situation. --- drivers/clk/clk.c | 9 +++++++-- include/linux/clk-provider.h | 2 ++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index adfc5bfb93b5a65b6f58c52ca2c432d651f7dd7d..94d93470479e77769e63e97462b176261103b552 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1927,7 +1927,6 @@ long clk_get_accuracy(struct clk *clk) } EXPORT_SYMBOL_GPL(clk_get_accuracy); -__maybe_unused static unsigned long clk_determine(struct clk_core *core, unsigned long rate) { struct clk_rate_request req = {}; @@ -2272,7 +2271,13 @@ static void clk_calc_subtree(struct clk_core *core) { struct clk_core *child; - core->new_rate = clk_recalc(core, core->parent->new_rate); + if (core->flags & CLK_NO_RATE_CHANGE_DURING_PROPAGATION) { + core->new_rate = clk_determine(core, core->rate); + if (!core->new_rate) + core->new_rate = clk_recalc(core, core->parent->new_rate); + } else { + core->new_rate = clk_recalc(core, core->parent->new_rate); + } hlist_for_each_entry(child, &core->children, child_node) clk_calc_subtree(child); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 200135e0f6d00d48b10e843259333b9733c97f38..baef0b442ac1d36ee935cbcaaaa4e2d95fe7654c 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -38,6 +38,8 @@ #define CLK_OPS_PARENT_ENABLE BIT(12) /* duty cycle call may be forwarded to the parent clock */ #define CLK_DUTY_CYCLE_PARENT BIT(13) +/* do not passively change this clock rate during subtree rate propagation */ +#define CLK_NO_RATE_CHANGE_DURING_PROPAGATION BIT(14) struct clk; struct clk_hw; From patchwork Thu Nov 21 17:41:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 13882239 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 423541C232B; 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arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="YXANeOT4" Received: by mail.gandi.net (Postfix) with ESMTPSA id 657C62000F; Thu, 21 Nov 2024 17:41:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1732210902; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yAUih0Mkszte9aiN7a8UUEUbUpUNBM3lVZGf6CK9gUM=; b=YXANeOT4VuQZKlUaFu1md2+8wKVPZNqSyV6u5suvZvIIrDJiDs/LUj13Wt89/OPEjRHOdq nO7m0KyEqW9lvmbiHodz6wikxK6g2+GOCZUpv/vNZ3SLeZoBavJDaigf3xgKj3YcpOjkfv AWmQks+Pez8OMjPWuGensS8q9N0MfyN/RhODto4VC1uYBiNrgmYwxcEI7IqQNQTbkASTdc dDalVzIMsMkQEZuTZKL+3LG9wz11qD7ZWlh0d4NvnvtlnDJUvpOEXrFDLhhfwNaFA4mrir tpz0WxKAshbYlKBcV3QDfWrMq64FXzEZXz7x7vHHgOf9r00+s5X1AfoJKnpvWA== From: Miquel Raynal Date: Thu, 21 Nov 2024 18:41:15 +0100 Subject: [PATCH 5/5] clk: imx: imx8mp: Prevent media clocks to be incompatibly changed Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241121-ge-ian-debug-imx8-clk-tree-v1-5-0f1b722588fe@bootlin.com> References: <20241121-ge-ian-debug-imx8-clk-tree-v1-0-0f1b722588fe@bootlin.com> In-Reply-To: <20241121-ge-ian-debug-imx8-clk-tree-v1-0-0f1b722588fe@bootlin.com> To: Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Ying Liu , Marek Vasut Cc: Laurent Pinchart , linux-clk@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Abel Vesa , Herve Codina , Luca Ceresoli , Thomas Petazzoni , Ian Ray , stable@vger.kernel.org, Miquel Raynal X-Mailer: b4 0.15-dev X-GND-Sasl: miquel.raynal@bootlin.com Having set the CLK_SET_RATE_PARENT flag to gain accuracy to the i.MX8 media related clocks (media_ldb, media_disp1_pix, media_disp2_pix) broke most simple setups using the LDB and one LCDIF. Indeed, pixel frequencies being set first, the top level PLL (video_pll1) was tuned to achieve the perfect frequency, and the media_disp*_pix divisor was set to 1 (acting like a passthrough). But shortly later, when setting the LDB clock to 7 times the pixel clock, the PLL machinery was recomputed, leaving the pixel divisors untouched. As a result, the attempted factor of 7 between the two clocks could never be observed. Set the CLK_NO_RATE_CHANGE_DURING_PROPAGATION flag to the LDB and LCDIF pixel clocks to force them to be kept as close as their initial target rate as possible across subtree walks. Fixes: ff06ea04e4cf ("clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal --- All patches in this series must be backported for this one to apply. --- drivers/clk/imx/clk-imx8mp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 2e61d340b8ab7f626155563c46e0d4142caf3fa9..2b916a4df97141dce46cefeb22ff584178a3929b 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -547,7 +547,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb_root", imx8mp_ahb_sels, ccm_base + 0x9000); hws[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mp_audio_ahb_sels, ccm_base + 0x9100); hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200); - hws[IMX8MP_CLK_MEDIA_DISP2_PIX] = imx8m_clk_hw_composite_bus_flags("media_disp2_pix", imx8mp_media_disp_pix_sels, ccm_base + 0x9300, CLK_SET_RATE_PARENT); + hws[IMX8MP_CLK_MEDIA_DISP2_PIX] = imx8m_clk_hw_composite_bus_flags("media_disp2_pix", imx8mp_media_disp_pix_sels, ccm_base + 0x9300, CLK_SET_RATE_PARENT | CLK_NO_RATE_CHANGE_DURING_PROPAGATION); hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1); @@ -609,9 +609,9 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_USDHC3] = imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3_sels, ccm_base + 0xbc80); hws[IMX8MP_CLK_MEDIA_CAM1_PIX] = imx8m_clk_hw_composite("media_cam1_pix", imx8mp_media_cam1_pix_sels, ccm_base + 0xbd00); hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] = imx8m_clk_hw_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80); - hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite_bus_flags("media_disp1_pix", imx8mp_media_disp_pix_sels, ccm_base + 0xbe00, CLK_SET_RATE_PARENT); + hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite_bus_flags("media_disp1_pix", imx8mp_media_disp_pix_sels, ccm_base + 0xbe00, CLK_SET_RATE_PARENT | CLK_NO_RATE_CHANGE_DURING_PROPAGATION); hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80); - hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite_bus_flags("media_ldb", imx8mp_media_ldb_sels, ccm_base + 0xbf00, CLK_SET_RATE_PARENT); + hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite_bus_flags("media_ldb", imx8mp_media_ldb_sels, ccm_base + 0xbf00, CLK_SET_RATE_PARENT | CLK_NO_RATE_CHANGE_DURING_PROPAGATION); hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base + 0xbf80); hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = imx8m_clk_hw_composite("media_mipi_test_byte", imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100); hws[IMX8MP_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", imx8mp_ecspi3_sels, ccm_base + 0xc180);